Energy and Power. Historical Scaling. Technology Scaling. CPU_power_dissipation

Transcription

1 CPU_pwer_dissipatin Energy and Pwer CMOS#Pwer:_switching_and_leakage cre-i5-2500t-2390t-i3-2100t-pentiumg620t.html Lecture ntes S. Yalamanchili and S. Mukhpadhyay (2) Histrical Scaling Technlgy Scaling GATE SOURCE GATE DRAIN t x SOURCE DRAIN BODY L 30% scaling dwn in dimensins à dubles transistr density Pwer per transistr v V dd scaling à lwer pwer 2 dd P = αcv f + V I + V dd st I dd leak Transistr delay = C gate V dd /I SAT v C gate, V dd scaling à lwer delay (3) (4) 1

2 Fundamental Trends ITRS Radmap fr Lgic Devices High Vlume Manufacturing Technlgy Nde (nm) Integratin Capacity (BT) Delay = CV/I scaling 0.7 ~0.7 >0.7 Delay scaling will slw dwn Energy/Lgic Op scaling >0.35 >0.5 >0.5 Energy scaling will slw dwn Bulk Planar CMOS High Prbability Lw Prbability Alternate, 3G etc Lw Prbability High Prbability Variability Medium High Very High ILD (K) ~3 <3 Reduce slwly twards RC Delay Metal Layers t 1 layer per generatin Surce: Shekhar Brkar, Intel Crp. (5) Frm: ExaScale Cmputing Study: Technlgy Challenges in Achieving Exascale Systems, P. Kgge, et.al, 2008 (6) Where Des the Pwer G in CMOS? Dynamic Pwer Cnsumptin v Charging and discharging capacitance Dynamic Pwer Dynamic pwer is used in charging and discharging the capacitances in the CMOS circuit. Shrt Circuit Pwer v Shrt circuit path between supply rails during switching v Nminally 10%-20% f dynamic pwer and can be ignred fr a first rder analysis VDD Vltage 0 T Time VDD C L i DD VDD i DD C L Leakage v Leaky transistrs Input t CMOS inverter Output Capacitr Charging Output Capacitr Discharging P DYNAMIC = C L x VDD x VDD x Frequency (7) (8) 2

3 Static Pwer Energy-Delay Interactin Technlgy scaling has caused transistrs t becme smaller and smaller. As a result, static pwer has becme a substantial prtin f the ttal pwer. Input = 0 Output = VDD Gate Leakage Junctin Leakage Sub-threshld Leakage Energy r delay Delay Energy V DD EDP V DD P STATIC = VDD x I STATIC Delay decreases with supply vltage but energy/pwer increases (9) (10) Static Energy-Delay Interactin Pwer Vs. Energy leakage r delay leakage delay V th SOURCE Static energy increases expnentially with decrease in threshld vltage Delay increases with threshld vltage GATE t x L DRAIN Pwer(watts) Pwer(watts) P2 P1 P0 P0 Time Time Same Energy = area under the curve Energy is a rate f expenditure f energy v One jule/sec = ne watt Bth prfiles use the same amunt f energy at different rates r pwer (11) (12) 3

4 Optimizing Pwer vs. Energy The Prblem Histrically perfrmance scaling was accmpanied by pwer scaling This is n lnger true à pwer densities are increasing Maximize battery life à minimize energy Thermal envelpes à minimize peak pwer (13) (14) The End f Dennard Scaling Chip Pwer Densities SOURCE GATE t x DRAIN L Vltage is n lnger scaling at the same rate Slwer scaling in pwer per transistr à increasing pwer densities Frm: ExaScale Cmputing Study: Technlgy Challenges in Achieving Exascale Systems, P. Kgge, et.al, 2008 Frm R. Dennard, et al., Design f in-implanted MOSFETs with very small physical dimensins, IEEE Jurnal f Slid State Circuits, vl. SC-9, n. 5, pp , Oct (15) (16) 4

5 The Pwer Wall What is the Prblem? Mukhpadhyay and Yalamanchili (2009) 2 P = αcvdd f + Vdd I st + Vdd I leak Pwer per transistr scales with frequency but als scales with Vdd v Lwer Vdd can be cmpensated fr with increased pipelining t keep thrughput cnstant v Pwer per transistr is nt same as pwer per area à pwer density is the prblem! v Multiple units can be run at lwer frequencies t keep thrughput cnstant, while saving pwer Based n scaling using Pentium-class cres While Mre s Law cntinues, scaling phenmena have changed n Pwer densities are increasing with each generatin n n (17) (18) 17 The Advent f Dark Silicn? In-rder cre Out f-rder cre Cannt affrd t turn n all devices at nce Hw d we manage the pwer and thermals? What are my Optins? 1. Better technlgy v Manufacturing v New Devices à nn-cmos? 2. Be mre efficient activity management v Clck gating v Pwer gating v Pwer management 3. Imprved architecture v Simpler pipelines 64-cre asymmetric chip multiprcessr layut and failure prbability distributin 4. Parallelism (19) (20) 5

6 Activity Management Clck Gating Pwer Gating Vdd input Cmbinatinal Lgic clk Pwer Management Sftware cntrlled pwer management v Optimize pwer and/r energy v Orchestrated by the perating system r applicatin libraries v Industry standard interfaces fr pwer management Pwer gate transistr cnd clk Cre 0 clk Turn ff clck t a blck f lgic Eliminate unnecessary transitins/activity Clck distributin pwer Cre 1 Turn ff pwer t a blck f lgic, e.g., cre N leakage Advanced Cnfiguratin and Pwer Interface (ACPI) n n Hardware pwer management v Optimized pwer/energy v Failsafe peratin, e.g., prtect against thermal emergencies (21) (22) Multiple Vltage Frequency Dmains Prcessr Pwer States Perfrmance States P-states Intel Sandy Bridge Prcessr v Operate at different vltage/frequencies Recall delay-vltage relatinship v Lwer vltage à lwer leakage v Lwer frequency à lwer pwer (nt the same as energy!) v Lwer frequency à lnger executin time Idle States - C-states v Sleep states v Differ is hw much state is saved SW r HW managed transitins between states! (23) Cres and ring in ne DVFS dmain Graphics unit in anther DVFS dmain Cres and prtin f cache can be gated ff Frm E. Rtem et. Al. HtChips 2011 (24) 6

7 Pwer States Pwer Gating Turn ff cmpnents that are nt being used Csts f pwering dwn Csts f pwering up Smart shutdwn v Mdels t guide decisins Intel Sandy Bridge Prcessr Frm: (25) (26) Simplify Cre Design Parallelism and Pwer IBM Pwer5 AMD Bulldzer Cre Supprt fr ut f rder executin, schedulers, branch predictin, etc. cnsumes mre energy per instructin ARM A7 Cre (arm.cm) Can fit many mre simpler cres n a dies Surce: IBM (27) AMD Trinity Surce: frwardthinking.pcmag.cm Hw much f the chip area is devted t cmpute? Run many cres slwer. Why des this reduce pwer? (28) 7

8 Parallelism Cncurrency + lwer frequency à greater energy efficiency Micrarchitectural Level Mdels Hw can we study pwer cnsumptin withut building circuits? v Mdels Cre Cre Cre Cre Cre Example 4X #cres 0.8x vltage 0.25x Frequency 0.8X pwer 1X in perfrmance Mdels can are available at multiple levels f abstractin. 2 dd P = αcv f + V I + V dd st dd I leak We are interested in micrarchitectural mdels (29) (30) TLB Prcessr Micrarchitecture Fetch Decde Execute/Writeback Fetch Queue Decder Memry Branch Predictin Queue Data TLB Register Files L1 Data L2 Data ALU MUL FPU LD ST NC Ruter Netwrk On-Chip Netwrk Energy/Pwer Calculatin Hw d we calculate energy r pwer dissipatin fr a given micrarchitecture? Energy/Pwer varies between: v Different ISA; ARM vs Intel x86 v Different micrarchitecture; in-rder vs ut-f-rder v Different applicatins; memry vs cmpute-bund v Different technlgies; 90nm vs 22nm technlgy v Different peratin cnditins; frequency, temperature (31) (32) 8

9 Architecture Activity (1) Architecture Activity (2) icache.read++; fbuffer.write++; Activity 1: Fetch Register Files ALU fbuffer.read++; idecder.lgic++; Activity 2: Decde Register Files ALU MUL MUL Fetch Queue Decder Queue FPU Fetch Queue Decder Queue FPU TLB Cllect activity cunts f each architecture cmpnent (thrugh simulatin r measurement). List f cmpnents differs between micrarchitectures. Activity cunts at each cmpnent differs between applicatins. Branch Predictin Data TLB L1 Data L2 Data LD ST NC Ruter On-Chip Netwrk (33) TLB Read/write accesses t caches, buffers, etc. Lgical accesses t lgic blcks such as decder, ALUs, etc. Tradeff f differentiating mre access types (accuracy) vs simulatin speed (cmplexity). Branch Predictin Data TLB L1 Data L2 Data LD ST NC Ruter On-Chip Netwrk (34) Pwer and Architecture Activity Things t cnsider (1) Fr example, At n th clck cycle, cllected cunters are: v Data cache: read = 20, write = 12; per-read energy = 0.5nJ; per-write energy = 0.6nJ; Read energy = read*per-read energy = 10nJ Write energy = write*per-write energy = 7.2nJ Ttal activity energy = read+write energies = 17.2nJ If n = 50 th clck cycle and clck frequency = 2GHz, Ttal activity pwer = energy*clck_freq/n = 688mW *Nte: n/clck_freq = n clck perids in sec pwer = time average f energy 1. Hw d we calculate per-read/write energies? Per-access energies can be estimated frm circuit-level designs and analyses. There are varius pen-surce tls fr this. Architecture Specificatin Technlgy Parameters Circuit-level Estimatin Tl Estimatin Results: Area, Energy, Timing, etc. (35) (36) 9

10 Things t cnsider (2) 2. Is per-access energy always the same? Per-access energy in fact depends n: hw many bits are switching hw they are switching (0 1 r 1 0) It is reasnable t assume cnstant per-access energy in lng-term bservatin (e.g., n = 1M clck cycles); the number f switching bits are averaged (e.g., 50% f bits are switching). Mst architecture simulatrs d nt capture bitlevel details due t simulatin cmplexity. Things t cnsider (3) 3. If a register file didn t have read/write accesses but held data, what is the energy dissipatin? Energy (r pwer) is largely cmprised f dynamic and static dissipatins. Dynamic (r switching) energy refers t energy dissipatin due t switching activities. Static (r leakage) energy is dissipatin t keep the electrnic system turned n. In this case, the register file has n dynamic energy dissipatin but cnsumes static energy. (37) (38) Thermal Issues Thermal Design Pwer (TDP) Heat can cause damage t the chip v Need failsafe peratin Thermal fields change the physical characteristics v Leakage current and therefre pwer increases v Delay increases v Device degradatin becmes wrse Cling slutin determines the permitted pwer dissipatin AMD Trinity APU This is the maximum pwer at which the part is designed t perate v Dictates the design f the cling system Max temperature à T jmax v Typically fixed by wrst case wrklad Parts are typically perating belw the TDP Opprtunities fr turb mde? (39) (40) 10

11 Trinity TDP Expliting the Physics Mst f time the part is perating well belw its thermal limit v Leaving perfrmance n the table Can temprarily bst frequency (and therefre pwer dissipatin) fr shrt perids f time, e.g., secnds Temperature changes slwly Surce: (41) (42) Explit package physics v Temperature changes n the rder f millisecnds Use the thermal headrm Max Pwer TDP Pwer Turb bst regin Bsting Intel Sandy Bridge Cnclusins Pwer/energy is the leading driver f mdern architecture design Pwer and energy management is key t scalability Need integrated pwer/energy, perfrmance, thermal management in fielded systems What abut energy/pwer efficient algrithms? 10s f secnds Lw pwer build up thermal credits (43) (44) 11

12 Explain the difference between energy dissipatin and pwer dissipatin Study Guide Distinguish between static pwer dissipatin and dynamic pwer dissipatin Be able t apply the simplified McPAT pwer mdel t a simple datapath and instructin sequence Explain dynamic vltage frequency scaling v What are pwer states? v Why is this an advantage? v What is the impact f DVFS n i) energy, ii) executin time, and iii) pwer (45) Study Guide (cnt.) Hw is thermal design pwer (TDP) calculated? When using bst algrithms, what determines the duratin f the high frequency peratin? Hw des a pwer virus wrk? Describe hw thrttling wrks Knw the pwer dissipatin in sme mdern prcessr-memry systems drawn frm the embedded, server, and high perfrmance cmputing segments (46) 12