Autonomic Power Management Schemes for Internet Servers and Data Centers. L. Mastroleon, N. Bambos, C. Kozyrakis, D. Economou

Transcription

1 IEEE GLOBECOM 2005 Autnmic Pwer Management Schemes fr Internet Servers and Data Centers L. Mastrlen, N. Bambs, C. Kzyrakis, D. Ecnmu December 2005 St Luis, MO

2 Outline Mtivatin The System Mdel and the DP Frmulatin A Justified Heuristic Simulatin and Evaluatin Cnclusins & Future Wrk 2

3 Mtivatin Typical Internet Server Typical Data Center The System Mdel and the DP Frmulatin A Justified Heuristic Outline Simulatin and Evaluatin Cnclusins & Future Wrk 3

4 Typical Internet Server Internet Server has multiple resurces (e.g. CPUs) Incming jbs are placed in a buffer Other tasks need als t be cmpleted Server has t apprpriately allcate its resurces Temperature f peratin is imprtant Incming Jb Traffic Internet Server Jb Buffer Other tasks requiring resurces Multiple Resurces e.g. CPUs 4

5 Typical Data Center At an apprpriately high level f mdeling abstractin, an internet server can be viewed as a caricature f a data center Jb Buffer Multiple Resurces e.g. Servers Incming Jb Traffic Other jbs requiring resurces 5

6 Outline Mtivatin The System Mdel and the DP Frmulatin The Mdel CPU Allcatin Envirnment & Thermal Envirnment Assciated Csts The Optimizatin Prblem Bellman s Equatin A Justified Heuristic Simulatin and Evaluatin Cnclusins & Future Wrk 6

7 The mdel Sltted time CPU Pl f Size M Thermal State Set T Jb Buffer f Size B Jb Buffer CPU Pl a CPU Allcatin Envirnment (respnsive) At the beginning f a slt: c is the# f CPUs used by buffer a is the # f available CPUs (M-a-c) is the # f unavailable CPUs u is the # f CPUs t use during this slt b c Thermal Envirnment (respnsive) 7

8 CPU Allcatin Envirnment & Thermal Envirnment CPU Allcatin Envirnment At the beginning f a slt the state is a After decisins the state is a * =(a+c-u) At the beginning f the next slt the state will be a The transitins a * a will be Markvian p a*a u Thermal Allcatin Envirnment State remains the same within a time slt Current state is t Next state will be t The transitins t t will be Markvian q tt (c,a,u) Statistically Independent Envirnments 8

9 Assciated Csts Csts incurred in each time slt: Backlg Cst C b (b) Increasing in b Pwer Cst (& Thermal Stress) C ut (u,t) Increasing in u & t (temperature) Recnfiguratin Cst C uc (u,c) Depends n the difference (u-c) 9

10 The Optimizatin Prblem At time 0: System starts with a full Buffer Objective: Empty the buffer with minimum verall cst At any time slt: The state is: (b, t, c, a) The management decisin is: u At mst ne jb will finish with prbability s(u) This is a transient prblem The slutin depends n the state but nt the specific time slt 10

11 Bellman s Equatin J(b,t,c,a) cst-t-g beginning frm state (b,t,c,a) J(b,t,c,a)=min u {ξc b (b) + (1-ξ)(C ut (u,t) + C uc (u,c)) +s(u) Σ q tt (c,a,u) p a*a u J(b-1,t,u,a ) +(1-s(u)) Σ q tt (c,a,u) p a*a u J(b,t,u,a ) } buffer state thermal state CPUs used CPUs available CPUs t use : b {0,..,B} : t T S=(b, t, c, a) : c {0,..,M} : a {0,..,M-c} Backlg cst Pwer cst : u {0,..,c+a} u Recnfiguratin cst ξ [0,1] : C b (b) : C ut (u,t) : C uc (u,c) 11

12 Outline Mtivatin The System Mdel and the DP Frmulatin A Justified Heuristic Key Insights The Frmula Simulatin and Evaluatin Cnclusins & Future Wrk 12

13 Key Insights u (c+a) b=0 u=0 u 1 if b>0 and (c+a) 1 (nt necessarily true) u(b+1,t,c,a) u(b,t,c,a) u(b,t,c,a) u(b,t,c,a ) if a a(nt necessarily true) The heuristic shuld incrprate the parameter ξ 13

14 The frmula The heuristic is described by the fllwing frmula: u(b,t,c,a)=min{h(c+a,t), b a 1 {b>0} (1+rund(f(ξ)h(c+a,t) ))} B M-c+1 h(c+a,t) limits the CPUs based n t f(ξ)=2 (3ξ-1) Nte f([ ])=[ ] 14

15 Outline Mtivatin The System Mdel and the DP Frmulatin A Justified Heuristic Simulatin and Evaluatin Simulatin Envirnment Simulatin Details Simulatin Results Cnclusins & Future Wrk 15

16 Simulatin Envirnment Evaluatin with simulatins using: OMNET++ Tw cases f arrivals: Cnstant Rate inter-arrival time ~ exp( 2 ) Bursty sequential cnstant rate and idle cycles with length ~ exp( 100 ) Executed ur simulatin fr ξ {0.1, 0.3, 0.5, 0.7, 0.9} Our benchmark was a cnstant CPU usage plicy 16

17 Simulatin Details In ur simulatin scenari we assumed the fllwing: Size f buffer : B=20 Set f thermal states : T={1,2,3,4,5} # f CPUs : M=8 s(u) : s(u)=exp(-0.2u) C b (b) : Cb(b)=b C ut (u,t) : Cut(u,t)=u t C uc (u,c) : Cuc(u,c)=0.2[u-c] [u-c] - 17

18 s b s b j l a t T / d e j l a t T / d e p t s C r e w P p p p l a t T r r d d b b J J g i n eu r a g e A v e ξ Simulatin Results Cnstant Rate arrivals 9.E+05 8.E+05 7.E+05 6.E+05 5.E+05 4.E+05 3.E+05 2.E+05 1.E Q u e Ti m Optimal Heuristic Cnstant Optimal Heuristic Cnstant

19 s b s b j l a t t s C T r / d j l a t T / d e p p e w e p P p r d l a r t d b T b J J ξ g i n eu r a g e A v e Simulatin Results Bursty arrivals 9.E+05 8.E+05 7.E+05 6.E+05 5.E+05 4.E+05 3.E+05 2.E+05 1.E+05 Optimal Heuristic Cnstant Optimal Heuristic Cnstant Ti m Q u e 19

20 Outline Mtivatin The System Mdel and the DP Frmulatin A Justified Heuristic Simulatin and Evaluatin Cnclusins & Future Wrk Cnclusins Future Wrk 20

21 Cnclusins Presented a nvel pwer management mdel fr internet servers and data centers Frmulated a DP that is agnstic t the arrival rate Created a lw cmplexity justified heuristic Simulated fr varius arrival patterns Substantial benefits especially when the arrivals exhibited strng tempral variatins 21

22 Future Wrk Future wrk will fllw in tw directins: Evaluatin with actual system parameters Traffic estimatin 22

23 Thank Yu! 23