ECE 545 Project Deliverables

Transcription

1 ECE 545 Prject Deliverables Tp-level flder: <Circuit_Name>_<Yur_First_Name> Secnd-level flders: 1_assumptins 2_blck_diagrams 3_interface 4_ASM_charts 5_surce_cde 6_verificatin 7_timing_analysis 8_results 9_benchmarking 10_bug_reprts [BONUS] 11_feedback [BONUS] The recmmended cntent f these flders is described belw: 1_assumptins The file assumptins.pdf, cntaining the descriptin f all assumptins (including pssible simplificatins) that yu have made. 2_blck_diagrams Third-level flders: A_detailed B_simplified Re: A_detailed Fr the detailed blck diagram, please fllw class examples and a few basic rules given belw: a. name and label all data, status, and cntrl signals in yur datapath that appear as signals in yur VHDL cde b. d yur best t keep yur signal names the same r similar t VHDL names and names used in the cipher specificatin (if necessary, deviate frm the names used in the cipher specificatin, e.g., replace S[2i+1] by S2ip1) c. label lwer level entities (such as "Hash") inside f the respective symbls d. explicitly label all prts f basic and lwer-level entities by placing prt names inside f symbls f respective cmpnents e. use arrws t indicate the directin f data flw f. explicitly label all bus widths, r include a legend that assciates thick lines with buses f a particular width, e.g., 128 bits, and all thin lines with single wires g. use mstly explicit cnnectins using buses and wires; use cnnectins by name nly fr cnnecting signals at the same level f hierarchy when they are lcated far frm each ther in yur blck diagram h. use either flyvers t indicate that wires d nt tuch, r slder pints (i.e., dts) t shw that cnnectins exist i. use hierarchical blck diagrams

2 j. clearly state the name f each entity at the tp f the respective blck diagram k. place all diagrams in ne PDF file, r name multiple PDF files, starting with the hierarchy level (1=tp), fllwed by a unique letter identifier, underscre, and the name f an entity (withut _Datapath), e.g., 1a_CipherCre, 2a_TEM, 2b_TEA, 3a_Sbx, etc. Re: B_simplified Please fllw Rules fr Reduced Cmplexity Blck Diagrams psted n the curse web page. Re: bth diagrams A. All diagrams must be submitted in PDF. Yu can draw diagrams using a graphical editr f yur chice (e.g., Xfig, Dia, MS Visi). Yu can als submit scanned versins f handwritten blck diagrams. B. [BONUS]: The cmplete editable versins f blck diagrams prepared using a graphical editr f yur chice will be rewarded with bnus pints. Please keep in mind that yu still need t submit the PDF versins f all blck diagrams. 3_interface terface with the divisin int the Datapath and Cntrller. Please clearly mark the width f each input/utput bus. Yu can draw this diagram using a graphical editr f yur chice (e.g., Xfig, Dia, MS Visi, MS Pwer Pint, etc.). 4_ASM_charts Cmments: A. If mre than ne FSM is used, please include a blck diagram illustrating cmmunicatin amng all FSMs. B. As a minimum, please include scans f yur handwritten ASM charts and the cntrller blck diagram in PDF. C. [BONUS]: The cmplete editable versins f ASM charts prepared using a graphical editr will be rewarded with bnus pints. Please nte that yu still need t submit PDF versins f all ASM charts.

3 5_surce_cde a. Please include all synthesizable VHDL files b. Please include als a file surce_list.txt listing all files in the rder they shuld be synthesized (bttm-up). 6_verificatin [THIS PART IS EXTREMELY IMPORTANT AND MAY DETERMINE YOUR FINAL GRADE] this flder include: A. Mdified reference sftware implementatin f yur algrithm, which yu have used t generate test vectrs. B. All test vectr files yu have used fr verificatin and debugging. C. All testbenches used t verify yur circuit peratin at varius levels f hierarchy. D. Reprt describing: Tls used fr cmpiling and running yur sftware implementatins and generating test vectrs Yur strategy fr verificatin: rder f tests and testbenches used, surce and frmat f test vectrs Highest level entity verified fr functinal crrectness and the results f its verificatin If the result f any verificatin was negative (i.e., yur circuit did nt perate as expected), please describe incrrect behavir and try t explain the pssible surces f errrs. Verificatin f lwer-level entities (ptinal if the tp-level unit was verified t wrk crrectly): Name f an entity Test vectrs and their surce Testbench used fr verificatin Result f verificatin, crrect r incrrect behavir Pssible surces f errrs. 7_timing_analysis Cmments: A. the file timing.pdf please prvide the exact frmulas fr the executin time f yur circuit expressed in clck cycles.

4 B. Please d yur best t cnfirm the executin time f yur circuit thrugh simulatin. Please clearly indicate in timing.pdf, which frmulas in yur reprt have been cnfirmed thrugh functinal simulatin). 8_results Please submit the dcument results.pdf cntaining the results fr the highest-level entity verified fr functinal crrectness. Please use the fllwing family f FPGAs t generate yur results: Kintex UltraScale A. resurce utilizatin a. LUTs b. Slices c. Flip-flps d. LUT-FF pairs e. BRAMs f. DSP units g. I/O pins B. numerical values f the fllwing timing parameters a. Minimum Clck Perid, T CLK b. Maximum Clck Frequency, f CLK c. Executin time fr majr peratins f yur circuit (in ns) based n the minimum clck perid after placing and ruting. C. analysis f the btained results; yur bservatins and cnclusins. Clearly indicate the name f the entity fr which these results were btained. 9_benchmarking - Results ptimized using Minerva - Excel graphs and charts summarizing all results - Analysis f the btained results; yur bservatins and cnclusins.

5 10_bug_reprts [BONUS] this flder, please include the fllwing subflders 1_specificatin 2_SW 3_Minerva 4_Other Each bug reprt shuld be placed in a separate subflder f these directries, and named: bug_<n>_mm_dd, where mm_dd represents the mnth and day when a given prblem was discvered, and <n> is a unique bug number. Fr each bug yu reprt, please include shrt descriptin. 1_specificatin please describe all mistakes yu have fund in the specificatin f the algrithm assigned t yu. These mistakes can include mistakes in the pseudcde, figures, tables, explanatins, etc. 2_SW please describe any mistakes, inefficiencies, and/r discrepancies (cmpared t the specificatin) yu have fund in the reference implementatin f yur circuit. 3_Minerva please include all infrmatin necessary t recreate the same prblem (in particular, surce files, versin f Vivad used, etc.).