Department of Electrical Engineering, University of Waterloo. Introduction


 Luke Long
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1 Sectin 4: Sequential Circuits Majr Tpics Types f sequential circuits Flipflps Analysis f clcked sequential circuits Mre and Mealy machines Design f clcked sequential circuits State transitin design methd State reductins Cunters Shift registers /59 Cmbinatinal Circuit Output = f ( present inputs) Intrductin Sequential circuit Output = f ( present and past inputs) Circuit remembers past histry Must cntain memry elements Time is variable that must be cnsidered Memry elements hld the present state f the system The past histry is recrded in the state As time prgresses, the system mves frm state t state 2/59
2 General sequential circuit mdel inputs k present state cmbinatinal circuit n utputs next state m memry state m Outputs are functins f inputs and present state Next state is functin f inputs and present state 3/59 Chsing the set f permissible states is a crucial part f sequential circuit design Chice f states has three issues: Identifying the number f unique states Identifying rules fr transitin frm state t state Finding a cding fr the state that simplifies the circuit (usually fairly bvius fr small systems) 4/59 2
3 Types f Sequential Circuits Fundamental Mde (asynchrnus) Shrtterm memry cnsists f signal prpagatin delay (gate delays) in the cmbinatinal circuit Frequently memry is nt distinct Fastest pssible circuit Cmbinatinal circuit with feedback Feedback can cause instability Difficult t design, analyse, debug Dn t use them unless frced t 5/59 Pulse r synchrnus Mde memry is prvided by flipflps Circuit nly changes state in respnse t a pulse input Unless pulse rate is t high, circuit is always stable Synchrnizatin is achieved thrugh clck pulses Circuit behavir depends nly n the inputs at the discrete times at which clck pulse ccurs 6/59 3
4 In fundamental mde ne must cnsider the differences in delay alng varius paths, and the effect f simultaneusly input changes With several different pulse inputs, in the wrst case the circuit must be designed as a fundamental mde circuit Hwever, in clcked sequential circuits ne is nly cncerned with Crrect cmbinatinal circuit Clck perid greater than the maximum prpagatin delay thrugh the cmbinatinal circuit 7/59 Flip  Flps A flipflp (FF) is the basic memry element f pulse mde circuit A flipflp stres ne bit f infrmatin RS (Reset/Set) Latch (Flipflp)* (unlcked versin) R S S S R R S R Tw states : Set : =, = 0 ; Reset: = 0, = 8/59 4
5 * Sme texts use the term latch and flipflp interchangeably Others restrict flipflp t elements with a pulse (clck) input, and latches t elements withut a pulse input, althugh a latch may have an enable input 9/59 Truth Table (Characteristic Table) R S n n+ n = present utput n+ = utput after input applied Output undefined  Output undefined If R = S = then = = 0 (NOR) and = = (NAND) If R and S g t 0 almst simultaneusly then the circuit can () Fall int either state (2) Oscillate, r (3) Remain at an indeterminate value fr an arbitrarily lng time, i.e. metastable state 0/59 5
6 A) (Clcked) RS FF R S Characteristic table as befre n  utput befre clck pulse n+  utput after clck pulse Characteristic equatin = Clck Pulse n+ S R SR n 0 X X n+ = S + R n with cnstraint: RS = 0 /59 B) Clck RS FF with asynchrnus Reset and Set Direct Clear and Preset clear R S preset Asynchrnus Reset and Set cntrls Used fr circuit initializatin 2/59 6
7 C) D (data) flipflp D D Characteristic Table D n n n+ = D cpies input t utput n clck pulse 3/59 D) T (tggle) flipflp T n n n+ = T n changes state n clck pulse when T = 4/59 7
8 E) JK flipflp Eliminate the indeterminate state f the RS flipflp n+ J = set K = clear JK simultaneusly = tggle JK n 0 characteristic equatin n+ = J n + K n J K n n /59 Flip  Flp Triggering T prevent repeated triggering f a JK flipflp when J=K=, clck pulse width must be less than prpagatin delay thrugh flipflp T avid clck pulse width prblems, prefer t trigger n edges f Tw appraches Masterslave flipflp Edge triggered flipflp 6/59 8
9 Master  Slave Flip  Flp Basic idea (RS flipflp) S master S Y slave S R R Y R = master is affected = 0 slave is affected Y 7/59 Master Slave JK Flip Flp J K Master Slave master affected slave affected (JK inputs ignred) (slave is an RS flipflp) 8/59 9
10 J  K master slave flipflps are susceptible t nise n cntrl lines while clck is high nise pulse J K Y Wuld prefer a system where the interval fr nise/glitch susceptibility is small 9/59 Edge Triggered Flip  Flps Basic ideal is t make the intervals where flipflp is susceptible t nise as small as pssible Example D flipflp utput changes here (psitive edge triggered) 20/59 0
11 Edge Triggered D Flip Flp A S R D B Changes state (if D) when makes a psitive transitin (0fi ) 2/59 in circuit, D must be present fr befre fi t setup = delay frm D t A utput D must stay cnstant fr t hld after fi t hld is delay thrugh S and R gates D t setup t hld Nte:  All flipsflps have a t setup and t hld cnstraints  If the cnstraints are nt met, the flipflp may g int metastable state. 22/59
12 Analysis f Clcked Sequential Circuits Analysis Prcedure Circuit equatins Excitatin table (Next state) Transitin Table and State equatins State diagram Timing chart SYNTHESIS IS JUST REVERSE! 23/59 Analysis Example x D A A D B B y A ( t + ) = A ( t ) x ( t ) + B ( t ) x ( t ) B ( t + ) = A' ( t ) x ( t ) 24/59 2
13 Alternatively A ( t + ) = Ax + Bx B ( t + ) = A' x Similarly y ( t ) = [ A ( t ) + B ( t ) ] x' ( t ) y = ( A + B ) x' 25/59 State Table Present Input Next Output State State A B x A B y /59 3
14 State Table Cntinued Next State Output Present State x = 0 x = x = 0 x = AB AB AB y y /59 Flip  Flp Characteristic Tables JK Flip  Flp J K ( t + ) 0 0 ( t ) N change 0 0 Reset 0 Set ' ( t ) Cmplement S R ( t + ) RS Flip  Flp 0 0 ( t ) N change 0 0 Reset 0 Set? Unpredictabe D Flip  Flp D ( t + ) 0 0 Reset Set T Flip  Flp T ( t + ) 0 ( t ) N Change ' ( t ) Cmplement 28/59 4
15 Mealy Machine Mre and Mealy Machines Output are pulses dependent upn the ttal input state ttal input state inputs + internal state Internal state inputs utputs q 0/0 q 2 29/59 Mre Machine Outputs are levels dependent upn nly the present internal state utputs q / internal state 0 inputs q 2 /0 try t use this frm when designing clcked circuits 30/59 5
16 Flip  Flp Excitatin Tables ( t ) ( t + ) S R X X 0 (a) RS ( t ) ( t + ) D (c) D ( t ) ( t + ) J K X 0 X 0 X X 0 (b) JK ( t ) ( t + ) T (d) T 3/59 Design Prcedure The (classical) apprach t clcked sequential circuit design fllws the steps: ) wrds r timing diagram 2) state transitin diagram 3) state table 4) reduced state table (if pssible) 5) assign binary values t states (state variable assignment) 6) develp transitin table 7) select flipflp type 8) excitatin table and utput table 9) simplified equatins 0) circuit diagram 32/59 6
17 Example Next State Present State x = 0 x = A B A B A B /59 Inputs f Cmbinatinal Circuit Present State Input Excitatin Table Next State Outputs f Cmbinatinal Circuit Flip Flp Inputs A B x A B JA KA JB KB X 0 X X X X X X X X 0 0 X 0 X 0 X 0 X 0 X X X 34/59 7
18 Blck Diagram ' K A' A B' A' KA J A JA Cmbinatinal circuit B' ' K KB B J JB External utputs (nne) B x External inputs 35/59 Lgic Diagram Bx B A X X X X A X X X X x JA = Bx' KA = Bx X X X X JB = x X X X X KB = ( A x )' 36/59 8
19 F Lgic Diagram Cntinued A B ' K J ' K J x 37/59 State Reductins Redundant states can be generated in ging frm a verbal descriptin t the state diagram Tw states are equivalent if, fr each member f the set f inputs, they give exactly the same utput and send the circuit t the same state r t an equivalent state M.M. Man When tw states are equivalent, ne f them may be remved Example Present Next state Output state x = 0 x = A D C B A E 0 C D A D B D 0 E C B 0 A and C are equivalent, B and E are equivalent 38/59 9
20 Reduced table 0 Present Next state state x = 0 x = utput (A,C) P D P (B,E) P 0 D D 0 A/ C/ P/ 0 B/0 0 0 D/0 0 0 D/0 0 E/0 /0 0 39/59 Registers A register is a bank f D flipflps (direct ) clear (0 clear ) I A (negative edge triggered) I n lad A n (lad s can disable circuit withut perfrming lgic n clck pulse) 40/59 20
21 RS versin lad I i S A i clear R D versin lad I i D A i clear Nte feedback t maintain value when lad = 0 4/59 Registers + Lgic Sequential Circuits n registers (present state) next state n Cmbinatinal m k inputs circuit utputs Use f ROM n registers (present state) n 2 (n +m) x(n + k) inputs m ROM k culd be PLA next state utputs culd be PLA N.B. If system is a Mre Machine, try t take the utputs directly frm registers if pssible (bth f abve cases) 42/59 2
22 Shift Registers serial in D D D D serial ut Abve is a sample shift register usually has an asynchrnus clear input used in serial t wrd cnversins many can be read in parallel many can be laded in parallel 43/59 Bidirectinal Shift Register with Parallel Lad A 4 (parallel utputs) A 3 A 2 A A i+ A i MUX D A i I 4 I 3 I 2 I (parallel inputs) s s 0 functin 0 0 n change 0 shift right 0 shift left lad I i s s 0 clear 44/59 22
23 Special Sequential Circuits 4.7. Serial Adder This circuit was develped n slide number 6 as the Carry Save Adder (CSA) least significant bits first serial input x y z S full adder C carry D serial utput The clck pulse recrds the carry advances inputs and utputs clear 45/59 Ripple Cunter (Asynchrnus Cunter) A 4 A 3 A 2 A K J K J K J K J ( negative edge triggered flipflps) Flipflps d nt change state simultaneusly Cnsider case where cunt pulse is the clck pulse: cunt pulse A A 2 A 3 flipflp setting delay Nte: In asynchrnus mde clck skew will ccur at each stage 46/59 23
24 Synchrnus Cunters A 4 A 3 A 2 A K J K J K J K J cntrl lgic (cmbinatinal circuit) This is a general versin f cunters. 47/59 Binary Cunter (Iterative Design) Cunters are cmmnly designed using an iterative cell apprach: A i ' K J A i  A E clear cell changes state if all cells t the right are and E = 48/59 24
25 A fur bit cunter has the frm: A 4 A 3 A 2 A K J K J K J K J E E  cunt enable C  (asynchrnus) clear C 49/59 E A A 2 A 3 flipflp setting delay max. clck rate < T where delay + T settling + T setup T delay = delay thrugh AND gate chain T settling = flipflp settling time T setup = flipflp set up time 50/59 25
26 Binary UpDwn Cunter The (iterative) cell has the frm: A i ' K J clear A I ... A U A i ... A D U = cunt up and D = cunt dwn U D 5/59 Up Cunter with Parallel Lad A i K J LE Functin X lad 0 cunt 00 n change C = A i ... A EL N.B. This is iterative design nniterative design is faster clear C I i L 52/59 26
27 MdulN Cunter Suppse we want,2,3,4,5,6,7,8,9 (md9 cunter) Ntes: any initial value any final value self crrecting A 4 A 3 A 2 A L parallel lad E up cunter clear I 4 I 3 I 2 I reset cunt 53/59 What is needed? Timing Signal Generatin T 0 T T 2 T 3 54/59 27
28 Cunter and Decder 2 bit 2 2 x 4 cunter decder enable T 0 T T 2 T 3 2 n states required n flipflps n x 2 n decder 55/59 Circular Shift Register ( Ring Cunter ) D T 0 T T 2 T 3 D D 0 D 0 circuit nrmally has an enable input requires a methd f lading initial pattern ( ) 2 n flipflps 56/59 28
29 If the circulating pattern is made 0 0 symmetric signals are generated T 0 T T 2 T 3 57/59 Jhnsn (SwitchedTail) Cunter The number f states in a circular shaft register can be dubled by cnnecting the cmplement f the last stage as the input t the first. A B C D D D ' Nrmally have enable input Als needs clear (fr resetting) Self starting (after clear) 58/59 29
30 Sequence number A B C Timing signal 3 flipflps, 6 AND gates N flipflps, 2N AND gates 6 timing signals 2N timing signals Drawback: Lcks int invalid sequences (Can be fixed) etc A ' C ' (extreme 0s ) AB ' ( 0 ) 3 0 BC ' ( 0 ) 4 AC (extreme s ) 5 0 A ' B ( 0 ) B ' C ( 0 ) 59/59 30