1. Transformer A transformer is used to obtain the approximate output voltage of the power supply. The output of the transformer is still AC.


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1 PHYSIS 536 Experiment 4: D Pwer Supply I. Intrductin The prcess f changing A t D is investigated in this experiment. An integrated circuit regulatr makes it easy t cnstruct a highperfrmance vltage surce using nly fur parts: a transfrmer, fullwave bridge rectifier, capacitr filter, and regulatr. A ener dide regulatr is als included as a simple illustratin f regulatr prperties. 1. Transfrmer A transfrmer is used t btain the apprximate utput vltage f the pwer supply. The utput f the transfrmer is still A.. Rectificatin A rectifier cnverts A t D. The peak vltage, V p, frm the rectifier is slightly less than the peak transfrmer vltage, V T. Vp = VT V d (1.1) V d is the vltage drp acrss the dide, typically ~ 0.8 V, and in a typical bridge rectifier the current flws thrugh tw dides. Since the vltage f the transfrmer secndary is always specified as an effective r RMS vltage, V e, and is related thrugh the peak vltage by the fllwing relatin V = 1.4V. (1.) 3. apacitr filter The filter capacitr stres charge s that it can smth the deep valley in the rectified wavefrm. The drp in capacitr vltage, i.e. the ripple, can be estimated using the relatins dv i= dt (1.3) i dv = dt hanging frm differential t delta ntatin t is the reciprcal f frequency, f, s T e i V = t (1.4) V = (half wave) (1.5) f where I is the current flwing ut f the capacitr. Fr a full wave rectifier I V = (full wave). (1.6) f In practice, a better apprximatin t ripple is slightly less and is given by I 0.7I V = (1.7) f
2 fr a full wave rectifier. By chsing a large capacitance the ripple can be reduced t any desired level, hwever this brutefrce apprach has several drawbacks. First f all, the capacitrs may be prhibitively large and/r expensive. Anther drawback is that even thugh the ripple may be negligible line vltage variatins are transferred t the utput vltage. A better apprach is t regulate the utput vltage. The current drawn frm the capacitr depends n the type f the regulatr used. We will cnsider tw types f regulatrs: I and eners. is the utput vltage f the regulatr and R is the external lad resistr cnnected t the regulatr, i.e. it is the resistance f the device r lad t which pwer is being transferred. Fr an I regulatr Fr a Zener regulatr I V / R c V =. (1.8) I = ( V V )/ R ( V V )/ R. (1.9) c Z A Z V is the average vltage n the capacitr; the peak rectified vltage, V A, can be used as an estimate fr V. V is the vltage f the ener dide and R is the resistr between the filter capacitr and the ener dide. When the lad resistr is attached directly t the capacitr withut a regulatr the current is given by the relatin I = V / R V R (1.10) c A / 4. Zener regulatr The vltage frm a ener regulatr is given by the fllwing expressin R r V = V + V I ( r, R ) (1.11) R + r R + r R is the resistr that supplies current t the ener, and is the ener equivalent r resistance. The ener can be visualied as a vltage generatr in series with a small equivalent resistance, r, (c.f. Fig. 3). Each f the terms in (1.11) has a physical meaning. In particular, the secnd term represents input regulatin; changes in the capacitr vltage, V c, have an effect n. Specifically, a change in the utput vltage, V0, is related t a change in V c by the equatin r dv = dv. (1.1) R + r V
3 The third term represents the utput regulatin, specifically hw changes in the utput current, I 0, impact V 0. hanges in V 0 are related t changes in I 0 by the equatin dv = di ( r, R ). (1.13) The maximum current that can be delivered t the external lad is I (max) V (min) V = I (min) (1.14) R V (min) is the lwest vltage n the capacitr and c I (min) is the minimum current needed t maintain lw resistance in the ener dide. If R draws mre current than specified by the preceding equatin, the ener is pulled ut f cnductin and acts like an pen circuit. 5. I Regulatr The peak vltage, V T, frm the transfrmer must be larger than the vltage needed fr the rectifier, V d, ripple, V, regulatr, V R, and utput vltage, V 0. V V V V V (1.15) T d R 6. Regulatr Specificatins The input regulatin is specified as a change in V 0 fr a permanent change f the input vltage, V i. Input regulatin: V when V changes frm t. i V1 V The effect f input ripple n is stated separately as attenuatin in db. V Ripple rejectin: RR( db) = 0 g( V/ V ( /0) V = V10 RR i i ) Output regulatin: V fr I change frm t I I 1. The temperature cefficient specifies the change in caused by a change in internal temperature. Temperature cefficient: = / V T V V 6. Pwer Dissipatin The heat that must be transferred frm the regulatr t surrunding air is P = ( V V ) I = ( V V / V ) I (1.16) p The average capacitr vltage, V, is estimated as the peak rectified vltage,, minus half the ripple. The internal temperature, T T, is j j A JA V p = T +Θ Ρ (1.17)
4 T is the air temperature arund the regulatr and A Θ is the thermal resistance JA in /watt. When a heat sink is used t imprve heat transfer, the resistance has three cmpnents; frm inside t the device case, frm case t sink, and frm sink t air Θ JA =Θ J +Θ S +Θ SA (1.18) B. Rectifier The arrangement f the dides in the bridge rectifier is shwn in the fllwing sketch. (The drawing is rearranged, but the cnnectins are the same as shwn in the lecture ntes.) The rectifier case is rund, and the pins are arranged as shwn. Only the psitive pin is labeled n the case. A Figure 1 D D 1) Refer t GI sectin 9 and test a 914 dide fr practice. Then check all the dides in yur bridge rectifier t be sure that it is wrking crrectly. The cmplete circuit f a basic pwer supply is shwn belw. Yu will assemble and test the rectifier prtin first (the part n the left side f the dashed line). ater yu will add the filter capacitr and then the regulatr. The variable transfrmer is used t adjust the A vltage applied t the rectifier. A Figure A Variable Transfrmer 5:1 Stepdwn Transfrmer Bridge Rectifier R 1 1K A + 100µf Regulatr I R V
5 (This is a cnvenient arrangement in ur teaching lab, but in a nrmal pwer supply the transfrmer wuld be selected t match the requirements f the supply.) nnect the secndary f the transfrmer t the red and green terminals f the circuit bx, nt the black terminal. ) During the lab use the transfrmer secndary vltage specified n the cmpnent sheet and calculate the peak rectified vltage, V, at pint A. Draw a sketch f A va() t cvering a full cycle. Hw much time is required fr a half cycle? On the scillscpe use D input cupling with er vlts as a reference (refer t GI sectin 5.3). Switch the input t grund and adjust the vertical psitin until the trace is alng a cnvenient hrintal line. In this case, a line near the bttm f the display is apprpriate since the bserved vltage is nly psitive. D nt change the scpe settings until yu have bserved the rectified wavefrm with and withut the filter capacitr in step 5. 3) Observe v (). Adjust the variable transfrmer until has the value calculated A t A in step. Is this the wavefrm yu expect?. Filter apacitr 4) During the lab r befre calculate the ripple vltage fr the capacitr specified. Use the peak vltage ( VA) calculated in step. Add a sketch f va() t with present t the sketch begun in step. Be sure that yu use the crrect plarity when the filter capacitr is added t the circuit. The negative side f the 100µf capacitr is marked with a minus sign and arrws n a blue band running dwn the side f the capacitr. Nrmally yu shuld turn ff the vltage t the circuit when cmpnents are changed. Hwever, in the next step a clearer image is btained by putting the capacitr in and ut f the circuit with the vltage n t see the effect n the wavefrm. Arrange the cmpnents s that this can be dne withut the danger f accidental cnnectins. The scpe settings shuld be the same used in step 3. 5) Tuch and remve the capacitr several times. mpare the change in wavefrm t the sketch yu drew in step 4. (An additinal sketch is nt required fr the lab reprt). After yu have bserved the effect f the capacitr, turn ff the vltage and cnnect fr the remainder f the experiment. Switch the scpe back t A cupling and change the gain s that it is cnvenient t measure the amplitude f the ripple. The capacitance f electrlytic capacitrs can be twice the nrmal value printed n the case; hence the bserved ripple may be smaller than expected. V
6 D. Zener Regulatr Remve R and add 1 R and the ener dide in the fllwing sketch. The ener dide perates with reverse vltage plarity, i.e. the bandend shuld be psitive. R is Figure 3 nt used initially. Assume r 10 Ω 6) alculate the ripple V R vltage n the V capacitr ( V ) and + IN4735 the change in V,, V 6.V R ZENER caused by V. (The peak value f the capacitr vltage ( V c ) is given n the cmpnent sheet. Since the ripple will be small, V can be used as the average value f v () t ). 7) Measure the ripple V and because it is small. alculate r frm the measured c c = V. Use A cupling and a cable t measure V and. 8) alculate the change in V that wuld be prduced by the specified change in 9) Use the digital vltmeter t measure V. Insert V R t draw utput current. alculate I, Observe the change in V. alculate r using and the measured I V. 10) alculate the maximum I that will leave a minimum f ma flwing thrugh the ener dide. The specified R draws t much current and causes the ener t cme ut f cnductin. alculate V with this R in the circuit. 11) Insert R and measure V V I. E. I Regulatr Remve R and the ener dide. Add the 7805 I regulatr. Specificatins and pin arrangement are given at the back f these instructins.
7 Figure V µf I V R This I has V =5V Use care, the pins n the regulatr can break if they are bent excessively. The capacitr at the utput reduces the danger that the regulatr will scillate. (the regulatr uses negative feedback, which can cause scillatin, as discussed in hapter 13 f the ntes). 1) alculate the minimum capacitr vltage that is acceptable fr this regulatr? alculate the capacitr ripple V fr the specified R. What is the smallest acceptable value f the capacitr vltage at its peak [ (peak)]? 13) Adjust the variable transfrmer s that (peak) is apprximately V larger than the minimum calculated in step 1. Measure the ripple vltage V. The fllwing prcedure shuld be used t bserve failure f the I regulatr when the capacitr vltage gets t lw. The vltage acrss the capacitr ( V ) and will c V be bserved n the dual trace, nt the differential mde. Set the vertical gain n bth channels at V/div. Use D cupling with er vlts as the reference. Use the same reference line fr bth traces near the bttm f the display. The difference between the tw traces shuld be the vltage acrss the regulatr. 14) Adjust the variable transfrmer t lwer belw the nrmal value. Yu shuld see that V V c drps at the lw pint n the capacitr discharge, which demnstrates that the regulatr fails when the capacitr ripple ges t lw. Increase until its minimum is slightly larger than that needed fr the regulatr V c t wrk crrectly. mpare the bserved minimum vltage needed acrss the regulatr t its specificatins. V 15) Estimate the change in caused by changing frm 7 t 5 vlts. Vc The current flwing thrugh the regulatr shuld be small t minimie heating effects when is changed. Hwever, sme current is required fr the regulatr t V c wrk crrectly. Use R =1K. Measure as sn as has been increased because V Vc there will be a slw drift due t heating in the regulatr. v V c
8 16) Use the variable transfrmer t change the minimum value f frm 7 t 5 v vlts. (Observe with the scpe.) Use the digital meter t measure befre and after the change. v V
9 Physics 536 Experiment 5 (A) 3. V = 15V A, R = 1K e 45. =100µ f, R = 1K 67. R =1K,V =17V, V =6.V c Z 89. I =5.ma, R =1.K R =470Ω,V =17V, R =1K R = 100Ω P R =1K R =100Ω 1 1. V c=1v,t A=40. Θ J=5 /W,ΘS=0.3 /W,Θ SA = /W Fr example, see T 6107 heat sink n text page 179 mpnents Transfrmers: variable and stepdwn Semicnductrs: 1N914 dide, 1N4635A ener dide, bridge rectifier, 7805 Iregulatr. apacitrs: 100µf, 0.1 µf Resistrs: 100Ω, 470Ω, 1K, 1.K
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