ENG2410 Digital Design Sequential Circuits: Part A

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1 ENG2410 Digital Design Sequential Circuits: Part A Fall 2017 S. Areibi Schl f Engineering University f Guelph Week #6 Tpics Sequential Circuit Definitins Latches Flip-Flps Delays in Sequential Circuits Clck Gating 2 Resurces Cmbinatinal Circuits Chapter #6, Man Sectins 6.1 Sequential Circuit Definitin 6.2 Latches 6.3 Flip-Flps A cmbinatinal lgic circuit has: A set f m Blean inputs, A set f n Blean utputs, and The utput depends nly n the current input values N Feedback, n cycles A blck diagram: Cmbinatrial Lgic Circuit 3 m Blean Inputs n Blean Outputs 4 Cmbinatinal vs. Sequential Circuits Cmbinatinal lgic are very interesting and useful fr designing arithmetic circuits(adders, multipliers) r in ther wrds the Data Path f a cmputer. Cmbinatinal circuits cannt remember what happened in the past (i.e. utputs are a functin f current inputs). In certain cases we might need t stre sme inf befre we prceed with ur cmputatin r take actin based n a certain state that happened in the past. Sequential circuits are capable f string infrmatin between peratins. They are useful in designing registers, cunters, and CONTROL Circuits. Examples: 1. Cunters: Remembering States 1. yu start with cunt 0 and then prceed with cunt 1 and then t cunt 2 2. The cunter is an example f a sequential circuit that needs t remember the previus state in rder fr it g t the crrect new state. 3. The utput f the cunter is based n the current state and als the inputs. 2. ATM Machine: 1. Yu insert yur card (state 0) 2. The system will then g t (state 1) that will ask yu t enter yur pin number 3. If successful then the machine will g t (state 2) that will ask yu fr the service required (withdraw cash, determine the balance, ) 4. The ATM machine is yet anther example f a sequential machine that will give the crrect respnse (utput) based n yur input and als n the current state. 3. Cntrl f Appliances: 1. A washing machine is an example f a sequential machine. 2. It starts with an initial state (des nthing!!) 3. It will wait fr sme input frm the user (setting the dials t perfrm a certain task). 4. Based n the input and current state it will mve frm ne state t anther (wash, then rinse then spin ) 5 6 Schl f Engineering 1

2 Sequential Circuits Infrmatin that is stred in the strage elements represent the state f the system. The utputs will depend n the inputs and present state f the strage elements. Strage Elements Types f Sequential Circuits Tw main types and their classificatin depends n the times at which their inputs are bserved and their internal state changes. Synchrnus State changes synchrnized by ne r mre clcks Asynchrnus Changes ccur independently 7 8 Signal Examples Over Time Clcking f Synchrnus Circuits Time Analg Digital Asynchrnus Synchrnus Cntinuus in value & time Discrete in value & cntinuus in time Discrete in value & time Changes enabled by a Glbal Clck 9 10 Basic Strage (Hw?) 1. Apply lw r high fr lnger than t pd But we are interested in string infrmatin indefinitely! 2. Feedback will hld value Hwever we want inputs t ur circuitry! SR (set-reset) Latches: Replace the inverters with NAND, NOR Gates Basic strage made frm gates The infrmatin can be changed S & R bth 0 in resting state Avid bth frm being 1 at same time 12 Schl f Engineering 2

3 Latches Operatin Are strage elements that can maintain a binary state indefinitely (as lng as pwer is delivered t the circuit) until directed by an input signalt switch states. Latches are asynchrnus circuits Latches are used t build mre cmplex synchrnus circuits such as Flip Flps. Reset, Q=0 Set, Q=1 Undefined! 13 Keep State 14 SR Latch Add Cntrl Input: SR Latch Similar made frm NANDs An additinal input determines when the state f the latch can be changed! S & R bth 1 in resting state Have t keep bth frm 0 at same time Can we avid the undefined state? D-type Latch Standard Symbls Latches N illegal state 1 Circle at input indicates negatin Schl f Engineering 3

4 Transparency f Latches Effects f Transparency The state f a latch is allwed t switchby a mmentary change in value n the cntrl input. As lng as C (the trigger ) is high, state can change! This is called transparency What is wrng with transparency? Clck Strage Element Output f ne latch may feedback As sn as the input changes, shrtly thereafter the crrespnding utput changes t match it. The final state will depend n hw lng the clck pulse stays at level lgic 1! (unreliable) We need t predict the utputsat a certain mment in time! Want t change latch state nce Depending n inputs at time f clck Flip-Flps Master-Slave SR Flip-Flp Ensure nly ne transitin Tw majr types 1. Master-Slave (level triggered) Tw stage Output nt changed until clck disabled 2. Edge triggered Change happens when clck level changes When Master is enabled, Slave is disabled! Output Q will nt change when inputs change S S C C R R Master SR Latch Slave Timing Diagram Have We Fixed the Prblem? Output n lnger transparent Cmbinatinal circuit can use last values New inputs appear at latches Nt sent t utput until clck lw In ne clck cycle we can predict what will happen Nte: Master-Slave = pulse triggered Trace the behavir Is it transparent? Schl f Engineering 4

5 JK Flip Flp Master-Slave JK Flip Flp The JK Flip Flp is a mdified versin f the SR Flip Flp. The JK flip flp perfrms three peratins: 1. Set Q t 1 2. reset Q t 0 3. cmplement the utput The J inputsets the flip flp t 1. The K input resetsthe flip flp t 0. When bth J and K are enabled, the utput is cmplemented Symbls Master-Slave Edge-Triggered Flip-Flps Inverted L indicates pstpned utput Circle indicates whether enable is psitive r negative An Edge Triggered Flip-Flp ignres the pulse while it is at a cnstant level and triggers nly during a transitin f the clck signal. New state latched n clck transitin Lw-t-high r high-t-lw Changes when clck high are ignred Clck Respnses Edge Triggered D-Flip-Flp We can classify Flip/Flps accrding t the respnse t the clck. D Latch D C S C R SR Latch Schl f Engineering 5

6 Characteristic Tables D FF Characteristic Table Define the lgical prperties f a flip flp by describing its peratins in tabular frm. They define the next state as a functin f the inputs and the present state. Q(t) refers t the present state prir t the applicatin f a clck edge. Q(t + 1) refers t the next state ne clck perid later. Clck edges are nt listed as inputs but are implied by the transitin frm t t t + 1. The Characteristic Equatin: Q(t + 1) = D(t) This indicates that the utput (next state) always fllws the input!! Edge-Triggered D Flip Flp: Graphic Symbls The triangle is called: dynamic indicatr Other Flip Flps Other types f flip flps can be cnstructed by using the D flip flp and external lgic. The tw mst cmmnly used are: 1. Edge triggered JK flip flps 2. T flip flps JK Characteristic Table Edge-Triggered JK Flip Flp Characteristic Equatin: Q(t+1) = J(t) Q (t) + K (t)q(t) Utilize the equatin t create a JK flipflp frm an existing D flipflp Q(t+1) = J(t) Q (t) + K (t)q(t) Schl f Engineering 6

7 JK- Characteristic Equatin T Flip Flp J K Q CLK Q ^ ^ ^ ^ ^ ^ ^ ^ 0 Q JK The T Flip Flp is a cmplementing flip flp. Hw can we btain a T Flip Flp frm a JK Flip Flp r D Flip Flp? T Q(t+1) = J(t) Q (t) + K (t)q(t) Q(t+1) = TQ (t) + T Q(t) T Flip Flp Symbls Edge-Triggered TheT flip flp can be btained frm a JK flip flp when inputs J and K are tied tgether. Arrw indicates edge trigger Characteristic Equatins Direct Inputs The D flip flp can be expressed as: Q(t + 1) = D The JK flip flp can be expressed as: Q(t + 1) = JQ + K Q The T flip flp can be expressed as: Q(t + 1) = TQ + T Q Set/Reset independent f clck Direct set r preset Direct reset r clear Often used fr pwer-up reset Characteristic Tables are used t 1. Derive the characteristic equatins, 2. Analyze Sequential Circuits Schl f Engineering 7

8 VHDL Design Styles VHDL Fr Sequential Circuits dataflw Cncurrent statements VHDL Design Styles structural Cmpnents and intercnnects behaviral (algrithmic) Sequential statements Registers State machines Test benches Several techniques have been discussed in class t describe the architecture f cmbinatinal lgic circuits: 1. Data Flw 2. Structural Statements used in Data Flw and Structural descriptins can be executed in parallel i.e. cncurrently. Anther technique t describe the architecture f any circuit is t use Behaviral descriptin. The prcess statementis usually used t describe sequential designs. The prcess statementcnsists f nly sequential statements VHDL Fr Sequential Circuits VHDL fr Psitive Edge Triggered D-FF T describe sequential circuits we usually use the prcess statement. A prcess statement cnsists f 1. Sensitivity list Prcess (CLK, RESET) This list enumerates exactly which signals causes the prcess statement t be executed. (Only events n these signals cause the prcess statement t be executed!) 2. Declarative regin Prcess (CLK, RESET) (declare lcal vars) Begin.. END -- psitive Edge-Triggered D flip-flp with reset -- VHDL Prcess Descriptin library ieee; use ieee.std_lgic_1164.all; entity dff is prt(clk, RESET, D : in std_lgic; Q : ut std_lgic); end dff; architecture pet_pr f dff is begin prcess (CLK, RESET) begin if(reset = `1 ) then Q <= `0 ; elsif(clk event and CLK = `1 ) then --yu can use rising_edge(clk) instead! Q <= D; end if; end prcess; end; Flip-Flp Timing Setup time (t s ) time that D must be available befre clck edge Hld time (t h ) time that D must be stable after clck edge Summary Cmbinatinal lgic are very interesting and useful fr designing arithmetic circuits(adders, multipliers) r in ther wrds the Data Path f a cmputer. Sequential circuits are capable f string infrmatin between peratins. They are useful in designing registers, cunters, and CONTROL Circuits. Latches are strage elements that are asynchrnus, transparent and are used t build mre cmplex synchrnus circuits such as Flip-Flps. Flip-flps avid the transparency prblem faced by latches and are either Master-Slave pulse active r edge triggered. Characteristic tables will be used t analyzethe behavir f sequential circuits Schl f Engineering 8

9 Cmparisn Synchrnus Easier t analyze because can factr ut gate delays Speed f the system is determined by the clck (maybe slwed!) Asynchrnus Ptentially faster Harder t analyze We will mainly lk at synchrnus 50 Analysis f the JK Circuit Prpagatin Delay The circuit applied t the D input is: D = JQ + K Q I. If J = 1 and K = 0, D = Q + Q = 1 (Set) II. If J = 0 and K = 1, D = 0 (Reset) III. If J = K = 0, D = Q, (N Change) IV. If J = K = 1, D = Q (Cmplement) Prpagatin delay time after edge when utput is available Psitive D-Type Edge Triggered Have We Fixed the Prblem? D C S C R Output n lnger transparent Cmbinatinal circuit can use last values New inputs appear at latches Nt sent t utput until clck lw In ne clck cycle we can predict what will happen But changes at input f FF when clck high trigger next state Transient state where S ges high caused by gate delays As clck faster, mre prblems Have t guarantee circuit settles while clck lw Nte: Master-Slave = pulse triggered Schl f Engineering 9

10 Clck Pulse Requirements Clck Gating Basically a max clck frequency Can gate clcks (t keep any FF frm changing states, fr example) Clck gating used t reduce pwer drain Hwever, can cause clck skew Clck edges at different times n different FFs Clck skew als caused by wire lengths ver chip T Flip Flp Master-Slave JK Flip Flp The T flip flp can als be btained frm a D flip flp by using an XOR as the input fr D. Q(t+1) = J(t) Q (t) + K (t)q(t) Schl f Engineering 10