ECE 497 JS Lecture - 14 Projects: FDTD & LVDS

Transcription

1 ECE 497 JS Lecture - 14 Prjects: FDTD & LVDS Spring 2004 Jse E. Schutt-Aine Electrical & Cmputer Engineering University f Illinis jse@emlab.uiuc.edu 1

2 ECE 497 JS - Prjects All prjects shuld be accmpanied with a shrt paper (3-5 pages) Paper surveys shuld be abut pages. P1. Write a prgram that simulates transients n a unifrm lssless line. P2. Write a mment methd cde t calculate the capacitance per unit length f a single micrstrip line. P3. Write a prgram that predicts the TDR respnse f a device frm the measured s parameters. P4. Write an FDTD prgram t calculate the frequency dependence f a micrstrip line P5. Develp an IBIS mdel fr a CMOS differential amplifier P6. Write a single TL prgram that will accept IBIS mdels at its terminatins P7. TBD n pwer distributin P8. LVDS versus single-ended design P9. Paper survey n related subjects 2

3 MOTIVATION Mdel signal cupling and distrtin in high speed circuit Predict prpagatin characteristics beynd TEM Extract frequency dependence f circuit parameters Full wave simulatin is necessary 3

4 Full-Wave Methds E r = r B t H r = r J + D r t B r = 0 D r = ρ v FDTD: Discretize equatins and slve with apprpriate bundary cnditins 4

5 Finite Difference Time Dmain Yee Algrithm E n n 1 c x (i, j,k)= E t x + ε y H z n 1/ 2 n (i, j, k) H 1/2 z (i, j 1, k) c t ε z H y n 1/ 2 n 1/ (i, j, k) H 2 y (i, j,k 1) ( ) ( ) Ex Ey x z y Hz Ez Hx Ey Ex Ez Hy Hy n +1/ H 2 n 1/2 c x (i, j,k)= H t x µ y E z n (i, j + 1, k) E n z (i, j,k) ( ) + c t µ z E y n (i, j,k + 1) E n y (i, j,k) ( ) Hx Ex Hz Ez Ey Ex Ey 5

6 2D-FDTD E y E x H z y x E n x i + 1 2,j = E x n 1 i + 1 2,j + t ε y H z n 1/2 i + 1 2,j+ 1 2 H z n 1/2 i + 1 2,j 1 2 E n y i, j = E y n 1 i, j t ε x H z n 1/2 i + 1 2,j+ 1 2 H z n 1/2 i 1 2,j+ 1 2 n+1/2 H 1 z i + 2,j+ 1 2 = H z n 1/2 i + 1 2,j t µ y E x n i + 1 2,j+1 E x n i + 1 2,j t - µ x E n 1 y i +1, j + 2 E n 1 x i, j + 2 6

7 2D-PML Frmulatin Simulatin Medium ε E x t ε E y t µ H z t = H z y = H z x = E x y E y x y ε E x t ε E y t µ H z t PML Medium +σe x = H z y +σe y = H z x +σ*h z = E x y E y x N reflectin frm PML interface x σ ε = σ * µ 7

8 PML-FDTD Frmulatin Perfectly Matched Layer (PML) artificial lssy medium reflectinless absrptin f EM waves independent f frequency r angle f incidence characterized by electrical cnductivity and magnetic cnductivity σ ε = σ µ The abve relatin ensures that the wave impedance f the PML medium is matched t that f the adjacent physical medium 8

9 PML-FDTD Frmulatin Mdified Maxwell s equatins: and where µ H sxz t +σ x H sxz = E y x ε E si +σ t i E si = iî H E = E sx +E sy +E sz and H = H sx +H sy +H sz i = x,y,z The abve equatins cntain twelve scalar equatins with twelve split field unknwns. Fr example, µ H sxz t +σ x H sxz = E y x 9

10 PML-FDTD Frmulatin The FDTD implementatin f these scalar equatins n a Yee grid is straightfrward. where n H sxz i, j,k = α n 1 mh sxz i, j,k β m n 1 E y i +1,j,k E y n 1 i, j,k x α m = µ t σ x 2 β m = µ t +σ x 2 / 1 µ t +σ x 2 10

11 CIRCUIT MODEL EM fields are simulated by the FDTD, where the PML is used as ABC The fields at sample psitins are recrded The current and vltage n the line are caculated by the fllwing integratins i(z,t) = H dl c v(z,t) = E dl [ ] After FFT, get the vltage and current matrices V(z,ω), [ I(z,ω) ] Calculate the circuit parameters L(ω), C(ω) 11

12 CIRCUIT MODEL Quasi-TEM mde f prpagatin in MTL s cnsisting f M lssless lines L(ω), C(ω) are the M M per unit length inductance and capacitance parameter matrices, respectively. V(z,ω), I(z,ω) are the line vltage and current vectrs. The circuit parameter matrices can be caculated by L(ω) = 1 jω ( d dz [ V(z,ω) ]I(z,ω) [ ] 1 ) C(ω)= 1 jω ( d dz [ I(z,ω) ]V(z,ω) [ ] 1 ) [ ] [ I(z,ω) ] dz d V(z,ω)= jωl(ω)i(z,ω) dz d I(z,ω)= jωc(ω)v(z,ω) V(z,ω), are the line vltage and current vectr matrices (M excitatins) 12

13 Numerical Results Verificatin f the FDTD-PML cde The cnductivities in PML are chsen with parablic prfiles The fields are excited with a single frequency surce (18 GHz) Nrmalized currents Time steps 13

14 Numerical Results Cupled lssless transmissin lines w s t z h y Parameters: w=s=0.3 mm, t=0.05 mm and h=0.25 mm 14

15 . Cupled Lines s/h= s/h=1.0 s/h= C 11 (nf/m) C 12 (nf/m) s/h=0.8 s/h=1. s/h= Frequency (GHz) w s w Frequency (GHz) h Parameters: w=0.3mm, h=0.25mm. Dielectric cnstant is 4.5. s/h=0.8 L 11 (nh/m) s/h=0.8 s/h=1.0 s/h=1.2 L 12 (nh/m) s/h=1.0 s/h= Frequency (GHz) Fr equency( GHz) 15

16 . EMI Simulatins 1 2 W 3 4 h w=1.2mm, h=1mm, ε r = 4.5 Prpagating signal (db) Prpagating signal (db) Frequency (GHz) Frequency (GHz) 16

17 2D-FDTD fr Intercnnects MOTIVATION * Take advantage f single mde prpagatin * Reduce cmputatinal dmain * Frmulate FDTD prblem in transverse directin STRATEGY E(x,y,z) E(x, y) H(x,y,z) H(x, y) z jβ z e jβ zz Use βz as input and btain transverse field prfiles fr different values f βz 17

18 . 2D-FDTD W h Parameters: w=h=1mm. The effective dielectric cnstant is C 600 L Capacitance (nf/m) D-FDTD 3D-FDTD Inductance (nh/m) D-FDTD 3D-FDTD Frequency (GHz) Frequency (GHz) 18

19 FDTD/PML Summary FDTD-PML prvides an accurate methd fr the extractin f intercnnect characteristics. Radiatin effects can be simulated accurately using FDTD-PML. 2D-FDTD is an efficient methd fr extracting the frequency dependence f intercnnects. Implementatin f absrbing bundary cnditin is critical t the accuracy f the methd. 19

20 References [1] K. S. Yee, Numerical slutin f initial bundary value prblems invlving Maxwell s equatins in istrpic media, IEEE trans. Antennas Prpagat., vl 14, pp , May [2] J. P. Berenger, " A perfectly matched layer fr the absrptin f electrmagnetic waves", J. Cmputatinal Physics, vl 144, pp , Oct [3] R. Mittra, W. D. Becker, and P. H. Harms, " A general purpse Maxwell slver fr the extractin f equivalent circuits f electric package cmpnent fr circuit simulatin." IEEE Trans. Circuits Syst. I, vl.39, pp , Nv [4] T. Dhaene, S. Criel, and D. D. Zutter, " Analysis and mdeling f cupled dispersive intercnnectin lines," IEEE Trans. MTT., vl40, pp , Nv [5] J. Zha and Z. F. Li, " A time-dmain full-wave extractin methd f frequency-dependent equivalent circuit parameters f multicnductr intercnnectin lines", IEEE Trans. MTT, vl 45, pp23-31, Jan [6] T. Daehne and D. De Zutter, " CAD-riented general circuit descriptin f unifrm cupled lssy dispersive waveguide structures, " IEEE Trans. MTT., vl. 40, pp , July

21 Lw-Vltage Differential Signaling (LVDS) Definitin: Methd t cmmunicate data using a very lw vltage swing (abut 350mV) differentially ver tw PCB traces r a balanced cable Criteria fr high-perfrmance cmmunicatin - Bandwidth - Lw Pwer - Lw Nise Slutin exists fr very shrt and very lng distances; hwever fr bard-t-bard r bx-t-bx, this is a challenge 21

22 Why LVDS? 1. Differential transmissin is less susceptible t cmmn mde nise 2. Cnsequently they can use lwer vltage swings 3. In PC bard (micrstrip) dd-mde prpagatin is faster 22

23 LVDS Attributes fr EMI 1. Lw utput vltage swing 2. Slw edge rates 3. Odd-mde peratin (magnetic fields cancel) 4. Sft utput crner transitins 23

24 LVDS Driver and Receiver - Majrity f current flws acrss 100-hm resistr - Switching changes the directin f current - Lgic state determined by current directin 24

25 Differential Signaling Technlgies RS-422 PECL LVDS Differential Driver Output Vltage ±2 t ±5V ± mv ± mv Receiver Input Threshld ±200 mv ± mV ±100 mv Data Rate <30Mbps >400Mbps >400Mbps Supply Current Quad Driver (n lad, static) 60 ma (max) 32-65mA (max) 8.0mA Supply Current Quad Receiver (n lad, static) 23mA (max) 40mA (max) 15mA (max) Prpagatin Delay f Driver 11ns (max) 4.5ns (max) 1.7ns (max) Prpagatin Delay f Receiver 30ns (max) 7.0ns (max) 2.7ns (max) Pulse Skew (Driver r Receiver) N/A 500ps (max) 400ps (max) 25

26 LVDS Standard Maximum Switching Speed Depends n line driver Depends n selected media (type and length) LVDS Saves Pwer Pwer dissipated in lad is small LVDS devices are in CMOS=>lw static pwer Lwers system pwer thrugh current-mde Design Practices Matching is critical Preserve balance 26

27 Prject P8 - LVDS Design Perfrm simulatin experiments t cmpare LVDS and single-ended signaling with CMOS driver and receiver. Emphasize speed, pwer and nise issues t validate the use f LVDS