Micro and Smart Systems

Transcription

1 Micr and Smart Systems Lecture 33 OpAmps Circuits and signal cnditining fr micrsystems devices Prf K.N.Bhat, ECE Department, IISc Bangalre

2 Tpics fr Discussin Amplifiers and Op Amp Cncepts Basic OpAmp circuits Signal cnditining 2

3 BJT Amplifier r e is the emitter base junctin ac resistance r e I EB E v i in e v in i r e e v i c L ltage gain A exp( EB ) v v i v i r r r I c L L L in e e e e I exp( / ) IE I E EB T E T EB T T kt T 25m at T 300K T 25m q re 25 Av 40 when L K IE ma I 3

4 I C C L BC Example: L =K, C =4. Then I C =2mA, BC =2. I C 4mA BC 4mA I E BC =2 BC swing C = 4 Maximum swing is 2peak and then it will get saturated 4

5 Operatinal Amplifiers The Operatinal Amplifier (r pamp) is a high gain, direct cupled amplifier perates with a Differential ltage between tw input terminals v 2 S The symbl fr pamp is as shwn 7 and has at least Five terminals v 3 It and cnsists f Multiple stages : 4 () An input stage t prvide high input resistance and certain amunt f vltage gain (2) Middle stages t prvide a high vltage gain (3) An utput stage t prvide a lw utput resistance S 6 v 0 5

6 Op Amp Terminals Terminal 2 is Inverting input. The utput that results frm input at this terminal will be inverted. Terminal 3 is Nninverting input. The utput that results frm input at this terminal will have the same plarity as input Terminals 4 and 7 are respectively negative and psitive DC pwer supplies S and S respectively Terminal 6 is the utput terminal v 2 v 3 S v 0 Symbl and terminals f OpAmp S 6

7 Opamp equivalent circuit and ideal mdel The utput ltage f the pamp is related t the pen lp gain A and the difference vltage i S S Equivalent Circuit A d Opamps with MOSFET have i =0 2 0 Ad A ( ) d Mdel f Ideal Op amp 0 d =A d i, 0, A Cmmn mde gain Ac= 0 Cmmn mde rejectin ati CM=A/Ac= Typical values f =75 7

8 Opamp transfer Characteristics ( versus d ) versus d is almst linear fr small values f d. As A is very arge the saturates when it exceeds psitive and negative values sat sat is set by the supply vltages f the p amp and is usually abut lt belw them. v 0 S S Slpe = A 0 d 8

9 Basic Op amp Circuits Inverting Amplifier S i A i in 2 i 2 Cnsider the ideal mdel : A d, i 0 and i 0 in 0. 0 ( ) i 0. i i ( 2) d Frm () and (2) A s 2 2 s in 2 9

10 Nninverting Amplifier i A S iin 2 i 2 Cnsider ideal pamp A = S and i = 2 S 2 2 S 0

11 Other cnfiguratins f the Opamp. ltage Fllwer. Buffer stage between tw stages t prevent lading 2.Integratr: T generate Saw tth frm square wave. S 3. Differentiatr: T generate square wave frm triangular wave i i S S i d C dt S S C i C i 2 i 2 d C dt i 2 S 2 t dt C s () i 2 i i d C dt S

12 Opamp Differential Amplifier 2 A 3 = B 2 4= 2 4 B () ( 2) 2 2 B 2 ( 2 ) 2 B

13 Instrumentatin Amplifier Dedicated Differential Amplifier with very high input esistance. Its gain can be adjusted with a single resistance g 2 S A i rg 2 2 A3 S2 ( ) rg S S2 A2 g rg i S S2 rg g g ( S S2 ) d 2 ( 2g ) 2 d ( SS2)( ) 2 2 g3 g

14 Merits f Instrumentatin Amplifier Extremely High Input impedance. High Cmmn Mde ejectin ati (CM) (ie. It is able t reject a signal that is cmmn t bth terminals but t amplify a differential signal ) The high CM is very useful fr receiving very small signals buried in large cmmnmde ffsets r nise 4

15 Instrumentatin Amplifier with Fixed Gain 2 S A 2 A3 S2 ( ) d S S2 A2 2 ( S2 S) 5

16 Signal cnditining fr Micrsystems Analg t Digital Cnverter (A/D cnverter r ADC) Output signals f mst physical systems (eg Sensrs) are Analg ie cntinuus functins f time. Need t cnvert them int binary frm t enable prcessing in the digital dmain t achieve higher efficiency and reliability ADC is the circuit which perfrms this cnversin and prvides an utput that digitally represents the input analg vltage level The input vltage is sampled at intervals T S and utput is digital in binary frm 6

17 Input utput scheme f a nbit ADC Analg input in DD ADC ref 000 (0 ) 00 ( 2) 00 (2 3) 0 (3 4) 00 (4 5) 0 (5 6) 0 (6v 7) (7 8) in n ( /2 ) ref ADC has an Analg eferenced vltage ref against which the analg input vltage is cmpared. The digital utput wrd tells us what fractin f ref the input vltage is. In a 3bit ADC number f bits n=3. There are 2 3 = 8 pssible utput cdes. The difference between each utput cde is ref /8 If ref = 8, every time the input vltage increases by vlt the utput cde increases by ne bit. 7

18 Illustratin f A t D Cnversin in a 3bit ADC Signal ( S ) Amplitude T s s Time, t (a) Analg Signal Sampled at intervals T S (0 ) 00 ( 2) 00 (2 3) 0 (3 4) 00 (4 5) 0 (5 6) 0 (6v 7) (7 8) (b) Sequential utput f Digital Signal 0 Time, t 8

19 Digital Output Quantizatin Errr In a 3bit ADC, If ref = 8, every time the input vltage increases by vlt the utput cde increases by ne bit. in n ( /2 ) ref 000 (0 ) 00 ( 2) 00 (2 3) 0 (3 4) 00 (4 5) 0 (5 6) 0 (6v 7) (7 8) Maximum Quantizatin Errr,QE = LSB Larger n f bits (n) gives better reslutin Smaller ref gives smaller steps but at the expense f nise Max QE= e ref 8 2 ref 8 3 ref 8 4 ref 8 5 ref 8 6 ref 8 7 ref 8 r f in 9