Design and Simulation of Dc-Dc Voltage Converters Using Matlab/Simulink

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1 American Jurnal f Engineering Research (AJER) 016 American Jurnal f Engineering Research (AJER) e-issn: p-issn : Vlume-5, Issue-, pp Research Paper Open Access Design and Simulatin f Dc-Dc Vltage Cnverters Using Matlab/Simulink 1 Marvin Barivure Sigal, ewis T. Osikib Center fr Electrical Pwer System Research (CEPSR) Department f Electrical Engineering Rivers State University f Science and Technlgy Prt Harcurt Rivers State Nigeria Abstract: The design f pwer electrnic cnverter circuit with the use f clsed lp scheme needs mdeling and then simulating the cnverter using the mdeled equatins. This can easily be dne with the help f state equatins and MATAB/SIMUINK as a tl fr simulatin f thse state equatins. An attempt has been made in this paper t simulate all basic nn-islated pwer cnverters. S that these mdels can be readily used fr any clse lp design (say using PI, fuzzy, r sliding mde cntrl etc.). Index Terms Switching cnverters, MATAB/SIMUINK, system mdeling, cascade cntrl, subsystems I. INTRODUCTION Cntrller design fr any system needs knwledge abut system behavir. Usually this invlves a mathematical descriptin f the relatin amng inputs t the prcess, state variables, and utput. This descriptin in the frm f mathematical equatins which describe behavir f the system (prcess) is called mdel f the system. This paper describes an efficient methd t learn, analyze and simulatin f pwer electrnic cnverters, using system level nnlinear, and switched state- space mdels. The MATAB/SIMUINK sftware package can be advantageusly used t simulate pwer cnverters. This study aims at develpment f the mdels fr all basic cnverters and studying its pen lp respnse, s these mdels can be used in case f design f any clse lp scheme. Als as a cmplete exercise a clsed scheme case has been studied using cascaded cntrl fr a bst cnverter. II. SIMUINK MODE CONSTRUCTION OF DC-DC SWITCHING CONVERTER System mdeling is prbably the mst imprtant phase in any frm f system cntrl design wrk. The chice f a circuit mdel depends upn the bjectives f the simulatin. If the gal is t predict the behavir f a circuit befre it is built. A gd system mdel prvides a designer with valuable infrmatin abut the system dynamics. Due t the difficulty invlved in slving general nnlinear equatins, all the gverning equatins will be put tgether in blck diagram frm and then simulated using Matlab s Simulink prgram. Simulink will slve these nnlinear equatins numerically, and prvide a simulated respnse f the system dynamics. A. Mdeling Prcedure T btain a nnlinear mdel fr pwer electrnic circuits, ne needs t apply Kirchhff's circuit laws. T avid the use f cmplex mathematics, the electrical and semicnductr devices must be represented as ideal cmpnents (zer ON vltages, zer OFF currents, zer switching times). Therefre, auxiliary binary variables can be used t determine the state f the switches. It must be ensure that the equatins btained by the use f Kirchhff's laws shuld include all the permissible states due t pwer semicnductr devices being ON r OFF. The steps t btain a system-level mdeling and simulatin f pwer electrnic cnverters are listed belw. 1) Determine the state variables f the pwer circuit in rder t write its switched state-space mdel, e.g., inductr current and capacitr vltage. ) Assign integer variables t the pwer semicnductr (r t each switching cell) ON and OFF states. 3) Determine the cnditins gverning the states f the pwer semicnductrs r the switching cell. 4) Assume the main perating mdes f the cnverter (cntinuus r discntinuus cnductin r bth) r the mdes needed t describe all the pssible circuit peratinal mdes. Then, apply Kirchhff's laws and cmbine all the required stages int a switched state-space mdel, which is the desired system-level mdel. w w w. a j e r. r g Page 9

2 American Jurnal f Engineering Research (AJER) 016 5) Write this mdel in the integral frm, r transfrm the differential frm t include the semicnductrs lgical variables in the cntrl vectr: the cnverter will be represented by a set f nnlinear differential equatins. 6) Implement the derived equatins with "SIMUINK" blcks (pen lp system simulatin is then pssible t check the btained mdel). 7) Use the btained switched space-state mdel t design linear r nnlinear cntrllers fr the pwer cnverter. 8) Perfrm clsed-lp simulatins and evaluate cnverter perfrmance. 9) The algrithm fr slving the differential equatins Fig Open-lp mdeling f Buck DC-DC cnverters and the step size shuld be chsen befre running any simulatin. The tw last steps are t btain clsed-lp simulatins []. III. SIMUATION OPEN-OOP MODEING OF DC-DC CONVERTERS A. Buck Cnverter Mdeling The buck cnverter with ideal switching devices will be cnsidered here which is perating with the switching perid f T and duty cycle D Fig. 1, [1]. The state equatins crrespnding t the cnverter in cntinuus cnductin mde (CCM) can be easily understd by applying Kirchhff's vltage law n the lp cntaining the inductr and Kirchhff's current law n the nde with the capacitr branch cnnected t it. When the ideal switch is ON, the dynamics f the inductr current i ( t) and the capacitr vltage v ( t) are given by, C di 1 ( V v ) in d t, 0 t d T, Q : O N d v 1 v ( i ) d t C R and when the switch is OFF are presented by, di 1 ( v ) d t, d T t T, Q : O F F d v 1 v ( i ) d t C R These equatins are implemented in Simulink as shwn in Fig. using multipliers, summing gain blcks, and subsequently fed int tw integratrs t btain the states i ( t ) and v ( t ) [][3] [4]. C blcks, and B. Bst Cnverter Mdeling The bst cnverter f Fig. 3 with a switching perid f T and a duty cycle f D is given. Again, assuming cntinuus cnductin mde f peratin, the state space equatins when the main switch is ON are shwn by, [1]. w w w. a j e r. r g Page 30

3 American Jurnal f Engineering Research (AJER) 016 di 1 ( V in ) d t d v 1 v ( ) d t C R and when the switch is OFF, 0 t d T, Q : O N di 1 ( V v in ) d t, d T t T, Q : O F F d v 1 v ( i ) d t C R Fig. 4 shws These equatins in Simulink using multipliers, summing blcks, and gain blcks, and subsequently fed int tw integratrs t btain the states i ( t ) and v ( t ), [][3][4] C C. Buck-Bst Cnverter Mdeling In Fig. 5 a DC-DC buck-bst cnverter is shwn. The switching perid is T and the duty cycle is D. Assuming cntinuus cnductin mde f peratin, when the switch is ON, the state space equatins are given by, [1] di 1 ( V ) in d t, 0 t d T, Q : O N d v 1 v ( ) d t C R and when the switch is OFF di 1 ( v ) d t, d T t T, Q : O F F d v 1 v ( i ) d t C R w w w. a j e r. r g Page 31

4 American Jurnal f Engineering Research (AJER) 016 Fig. 5 DC-DC Buck-Bst Cnverter These equatins are implemented in Simulink as shwn in Fig. 6 using multipliers, summing gain blcks, and subsequently fed int tw integratrs t btain the states i ( t ) and v ( t ), [] [3] [4]. C blcks, and D. Cuk Cnverter Mdeling Fig. 6 Open-lp f Buck-Bst DC-DC Cnverters The Cuk cnverter f Fig. 7 with switching perid f T and duty cycle f D is cnsidered. During the cntinuus cnductin mde f peratin, the state space equatins are as fllws, [1] di 1 1 ( v ) in d t 1 dv 1 c ( i ) d t C, 0 t d T, Q : O N di 1 ( v v c ) d t d v 1 v ( i ) d t C R 1 When the switch is OFF the state space equatins are represented by di 1 1 ( v v ) in d t 1 dv 1 c ( i 1 ) d t C, d T t T, Q : O F F di 1 ( v ) d t d v 1 v ( i ) d t C R 1 Fig.7 DC-DC Cuk cnverter w w w. a j e r. r g Page 3

5 American Jurnal f Engineering Research (AJER) 016 These equatins are implemented in Simulink as shwn in Fig. 8 using multipliers, summing blcks, and gain blcks, and subsequently fed int tw integratrs t btain the states and, [] [3] [4] Fig. 8 Open-lp mdeling f Cuk DC-DC cnverters E. Subsystems Each f the pwer electrnic mdels represents subsystems within the simulatin envirnment. These blcks have been develped s they can be intercnnected in a cnsistent and simple manner fr the cnstructin f cmplex systems. The subsystems are masked, meaning that the user interface displays nly the cmplete subsystem, and user prmpts gather parameters fr the entire subsystem. Relevant parameters can be set by duble-clicking a muse r pinter n each subsystem blck, then entering the apprpriate values in the resulting dialgue windw [4]. T facilitate the subsequent simulatin analysis and feedback cntrller verificatin, the pulse-widthmdulatin signal t cntrl the ideal switch can als be built int the masked subsystem Fig. 9(a) and Fig. 9(b). Fr each cnverter t verity it s wrking in pen lp cnfiguratin trigger pulses have been derived using a repeating sequence generatr and duty cycle blck. Functin blck cmpares the duty cycle and saw tth frm repeating sequence- derived trigger pulses are cnnected as an input t the switch cntrl. Hence inputs fr the masked subsystem are duty rati and input vltage, and the utputs are chsen t be inductr current, capacitr vltage, and utput vltage. When duble-clicking the pinter n the masked subsystem, ne enters parameter values f the switching cnverter circuit in a dialgue windw. The intuitive signal flw interface in SIMUINK makes this mathematical mdel and its crrespnding masked subsystem very easy t create. IV. SIMUATION COSED-OOP OF DC-DC CONVERTERS USING CASCADED CONTRO The simulatin mdel fr cascaded cntrl f DC-DC switching cnverters is build using the abvementined steps is as shwn in Fig. 10. The DC-DC buck, bst, buck-bst, and Cuk cnverters was previusly designed, and simulated n digital cmputer using Matlab package with the parameters given in Table 1, and Table. Inductr current and capacitr vltage fr pen lp simulatin f all cnverters are as shwn in Fig.11 (a, b, c, and d). Table 1 Buck, Bst, and Buck-Bst cnverters parameters V in C R f 4, 10, 4V Respectivel y 69 mh 0 F K H z V V in 1, 0, - 4V Respectiv ely 4 V Table Cuk cnverter parameters C C f 1 1 R V 69 mh 19 mh 47 F 0 F 100 K H z V Results f Clsed lp using a cascaded cntrl scheme fr a bst cnverter is shwn in Fig. 1(a). Here the utput vltage rises up t 1.3V (6.5%) fr the step variatin f lad frm 10 t 13 (30%). The utput vltage resumes its reference value (f 0V) within 15ms after the transient variatin f lad. As per fig 1(b), fr a step change at the input vltage frm 10V t18 V (80%) (at 0.5 Sec instant), a satisfactry perfrmance is btained in the utput vltage which has a rise up t.8v (14%), but it is quickly drpped t its set value w w w. a j e r. r g Page 33

6 American Jurnal f Engineering Research (AJER) 016 (0V) within 16 ms. Simulatin results verify that the cntrl scheme in this sectin gives stable peratin f the pwer supply. The utput vltage and inductr current can return t the steady state even when it is affected by line and lad variatin. V. CONCUSIONS This paper analysis nnlinear, switched, state-space mdels fr buck, bst, buck-bst, and Cuk cnverters. The simulatin envirnment MATAB/SIMUINK is quite suitable t design the mdeling circuit, and t learn the dynamic behavir f different cnverter structures in pen lp. The simulatin mdel in MATAB/SIMUINK fr the bst cnverter is build fr clse lp. The simulatin results btained, shw that the utput vltage and inductr current can return t steady state even when it is affected by input vltage and lad variatin, with a very small ver sht and settling time. Fig. 9(b) Subsystem fr Cuk cnverters Fig. 9(a) Subsystem fr Buck, Bst and Buck-Bst cnverters Fig.10 Simulink blck diagram representing clse lp Scheme f Bst cnverter using cascaded cntrl w w w. a j e r. r g Page 34

7 American Jurnal f Engineering Research (AJER) 016 Ripple (peak-t-peak = 0.11%) (a) Ripple (peak-t-peak = 0.43%) (b) Ripple (peak-t-peak = 0.1%) (c) w w w. a j e r. r g Page 35

8 American Jurnal f Engineering Research (AJER) 016 Ripple (peak-t-peak = 1.96%) Fig. 11 Output vltage and inductr cu rrent Open-lp fr (a) Buck (b) Bst (c) Buck-Bst (d) Cuk Cnverters (d) (a) (b) Fig. 1 Output vltage f SMC Bst Cnverter when (a) lad variatin (b) input vltage variatin References [1]. J.Mahdavi, A.Emadi, H.A.Tliyat, Applicatin f State Space Averaging Methd t Sliding Mde Cntrl f PWM DC/DC Cnverters, IEEE Industry Applicatins Sciety Octber []. Vitr Fema Pires, Jse Fernand A. Silva, Teaching Nnlinear Mdeling, Simulatin, and Cntrl f Electrnic Pwer Cnverters Using MATAB/SIMUINK, IEEE Transactins n Educatin, vl. 45, n. 3, August 00. [3]. Juing-Huei Su, Jiann-Jng Chen, Dng-Shiuh Wu, earning Feedback Cntrller Design f Switching Cnverters Via MATAB/SIMUINK, IEEE Transactins n Educatin, vl. 45, Nvember 00. [4]. Daniel gue, Philip. T. Krein, Simulatin f Electric Machinery and Pwer Electrnics Interfacing Using MATAB/SIMUINK, in 7 th Wrkshp Cmputer in Pwer Electrnics, 000,pp [5]. N. Mhan, T. Undeland, W. Rbbins, Pwer Electrnics Cnverters, Applicatins and Design, ISBN w w w. a j e r. r g Page 36