Propagation of High Speed Digital Signals in Printed Circuit Board Systems - Phase I. Michael B. Steer Jeff Kastan Mark S. Basel Sasan H.

Transcription

1 Prpagatin f High Speed Digital Signals in Printed Circuit Bard Systems - Phase Michael B. Steer Jeff Kastan Mark S. Basel Sasan H. Ardalan Center fr Cmmunicatins and Signal Prcessing Department f Electrical and Cmputer Engineering Nrth Carlina State University Raleigh, NC and Real Pmerleau Bell Nrthern Research Research Triangle Park NC AUGUST 1987 ccsr.tr-87/13

2 Abstract This technical reprt is a reprt n the first phase f a prject entitled Prpagatin f high speed digital signals in printed circuit bard 3Y3tem3 funded by Bell Nrthern Research as an enhancement prject within the Center fr Cmmunicatins and Signal Prcessing in the Electrical and Cmputer Engineering Department at Nrth Carlina State University. The gal f the first phase, which lasted 6 mnths, 1/1/87-6/30/87, was t identify the prblems encuntered in printed circuit design fr circuits with high speed digital signals and t develp a strategy fr addressing them. This wrking paper reprts n preliminary printed circuit bard measurements cmparing printed circuit bards with slid and with lattice grund and supply planes, initial develpments f a transmissin line simulatr fr efficiently simulating transmissin line structures, and a literature review f techniques fr the simulatin f transmissin line structures fund n printed circuit bards. Cntents 1 ntrductin 2 Prblem Definitin 3 Literature Review 4 Experimental Characterizatin 5 Simulatr Develpment 6 Technlgy Transfer 7 Plan f wrk 8 Cnclusins A Review f micrstrip transmissin line studies and simulatins 28 B CAPNET - a transmissin line simulatr simulatr C ZOSTRP - Prgram fr determining Micrstrip Parameters D Experimental characterizatin f Test Bard 87 2

3 1 ntrductin This is a reprt n an investigative prject lking at digital signal prpagatin in systems incrprating printed circuit bards (PCBs). This prject is cncerned with reflectin, crss-talk, and grund and supply nise phenmena in digital systems. n systems with digital devices that respnd t fast rise- and fall-time signals, these phenmena can result in false respnses and in sme cases can render a system unusable. The prject is cncerned with establishing criteria, that minimize and cntrl these effects, fr the design f printed circuit bards and thus develping cmputer aided design tls t augment existing tls fr their autmated design. The prject is in three phases with the wrk prgressing frm literature and prduct review t develpment and integratin f a cmputer aided design tl. Phase lasted six mnths and invlved a detailed literature and prduct search with the aims f identifying the prblems t be addressed, thse prducts which wuld assist in this prgram, requirements fr integrating the results f this study with existing circuit bard design systems, and utlining a wrk plan fr the last tw phases f the prject. This reprt is rganized int sectins which describe the wrk f the first phase. The prblem is defined in sectin 2 s that we can prperly address the high speed digital signal prpagatin in printed circuit bard systems. The results f the literature and prduct review f transmissin line mdels and simulatrs is presented in sectin 3 and appendix A. This and private cmmunicatin with leaders in the RF and micrwave CAD cmmunity have helped shape the plan f wrk presented in sectin 7. We prpse t fcus n develping a table based printed circuit bard simulatr which can use the results f existing sftware fr predicting cupling and EM, use experimentally derived data, and use heuristicly r analytically develped mdels. t is highly unlikely that anyne type f apprach t mdeling printed circuit bard structures wuld be feasible. Preliminary experimental characterizatin f printed circuit bards specifically fabricated fr this prject are presented in sectin 4. A particular aim f the experimental characterizatin wrk was determining the relative merits f printed circuit bards with slid and with lattice grund plans. Results are presented shwing that there is a significant difference s that bards with slid grund planes are preferred fr cntrlled impedance applicatins. A printed circuit bard simulatr - CAPNET - currently under develpment in the Center fr Cmmunicatins and Signal Prcessing is discussed in sectin 5. This simulatr will be cmputatinally efficient and is being develped as an assistant t an intelligent aut-ruter in laying ut printed circuit bard tracks. and as a stand alne simulatin tl. n sectin 6 we summarize the tangible technlgy that has been transferred t Bell Nrthern research (BNR). 2 Prblem Definitin The prblem addressed is hw t design a large digital system s that reflectins, crss-talk and ther distributed phenmena are sufficiently cntrlled that digital circuits functin 3

4 crrectly. The systems being cnsidered have clck speeds f up t 50 MHz but respnd t pulses with rise- and fall-times f - 3 ns (crrespnding t requiring the circuit bard tracks and assciated cmpnents t have 3 db bandwidths f 700 and 100 Mhz respectively). n view f prjected develpments in digital technlgy it was decided that characterizatin t 3 GHz was required. n a PCB system digital signals will prpagate at a speed f abut c (assuming,. fr PCBs f abut 5). - r abut 15 em per nansecnd. Branching, impedance changes f the cnductr paths, device lading and finite device drive capability will significantly affect rise- and fall-times - 3 ns fr cnductr lengths in excess f 2-12 em. Cntrlled impedance design f a PCB requires that a grund cnductr near the signal-carrying cnductr be used. The prximity f the cnductrs lcalizes fields s that crss-cupling effects and nnunifrm prpagatin characteristics are minimized. While nt practical in large PCB systems, using a micrwave-type circuit wuld slve the prblem and it shuld be pssible t adapt t printed circuit bard design many f the techniques develped fr the design f micrstrip circuits [2] [3] [4] [9], 3 Literature Review A preliminary search f the literature has nt uncvered any significant discussin f the prpagatin f fast rise- and fall-time digital signals in printed circuit bard systems. Hwever there is a large bdy f literature related t the subject that can be bradly categrized as general transmissin line thery r as prpagatin f signals in planar circuits. Basic transmissin line thery is well established [1]. Recent wrk, relevant t pulse prpagatin in PCB systems, has discussed digital signal prpagatin in telephne, cmputer and pwer line distributin netwrks [5,6]. Printed circuit bards are a class f planar circuits with multi-level metallizatin lines but withut a clearly defined reference grund plane. Hwever studies f prpagatin in planar circuits have largely been restricted t structures with single [4,7] r multi-level [2,8,9] metallizatin lines abve infinite grund planes. Thes- structures are typical f UHF and micrwave circuits and the effects f discntinuities and f cupling are reasnably well characterized. While mst f the wrk cited is cnfined t analg signals, the wrk can be extended t pulse prpagatin. We have undertaken an extensive literature review f micrwave transmissin lines, cupling and discntinuities. We reprt n this review in Appendix A. The emphasis f this review is n mdels f transmissin line structures and strategies fr simulating printed circuit bards. We have had several discussins with cmmercial vendrs and investigated several RF and micrwave simulatin and CAD packages. There is nthing suitable fr ur purpses but the mst prmising - bth because f user supprt and mdeling accuracy - are SUPERCOMPACT [11] and TOUCHSTONE [10]. These are linear frequency dmain analysis prgrams and d nt cntain the types f circuit elements typicly fund in printed circuit bards. Hwever they d prvide simulatin capability fr sme simple structures and aid in interpreting measurements and in mdel develpment. TOUCHSTONE is used 4

5 at BNR and at NCSU fr this purpse. 4 Experimental Characterizatin The aims f the initial experimental characterizatin f phase were establishing the measurement requirements fr characterizing circuit bard structures, determining the mdeling capability required, and cmparing the characteristics f bards with slid and with lattice grund planes with respect t their applicability t cntrlled impedance design. Transmissin line mdels f fur layer printed circuit bard transmissin lines, with track widths frm 8 mil t 100 mil, were develped by fitting the physical micrstrip transmissin line mdel f TOUCHSTONE [10] t measured data. Measurements were made using the test setup f Figure 1 and the test bard shwn in Figure 2. The nmenclature denting the tracks is described in Table 1. The nmenclature is f the frm mejri were ms indicates that we are dealing with a micrstrip line, z is either s indicating that the printed circuit bard has a slid grund plane r, if 1, that the bard has a lattice grund plane. f y is b then there is a bend in the middle f the transmissin line. The final character is the number denting the width f the track. The bards were cut t length using a diamnd saw and electrical cntact between the adapter tab and the printed circuit bard track was made using silver paste and the hlders were held in place using clamps. The track lengths in all cases were 248 mm with metallizatin thickness f 25 usi: and dielectric thickness f 0.35 mm. The grund plane clsest t a track was expsed by first grinding the side f the printed circuit bard ppsite the track until the metal first shwed, and then hand sanding until the entire grund plane was visible. Electrical cntact between a hlders and the grund plane was again ensured by again using silver paste. This measurement structure is the mst accurate methd fr characterizing printed circuit bard traces as it minimizes parasitics assciated with the cnnectin t the bard. Hwever it is destructive and and time cnsuming and is nt recmmended fr Phase measurements. The measurements reprted here prvide a reference fr the nndestructive measurement prcedure t be used in phase. Measurements and the results f mdeling the 8 mil wide line are shwn in Figures 3-6. The micrstrip line mdel was btained by fitting the mdel f Figure 7 t measured s parameters. Mdel fitting was achieved using TOUCHSTONE [10]. The measurements are mdeled reasnably well up t 10 GHz. Hwever there is a majr discrepance between the measured and calculated magnitude f is the transmissin S parameter and its magnitude is the rati f the vltage wave arriving at prt 2 t the incident vltage at prt 1, all measured in a 50 n measurement system. With the micrstrip mdels in TOUCHSTONE the nly lss mechanism accunted fr is metallic resistivity mdified by the skin effect. This results in a lss, expressed in db [tu, increasing as the square rt f frequency up t 10 GHz as is seen in Figure 5. The actual lss t 10 GHz - expressed in db/m - has almst linear dependence n frequency indicating a substantial lss due t radiatin r dielectric lss. 5

6 r< [ (f '<f,\jcf, PLAN, /v1a H5c/D511;fi' LAu/vc 14 f \ rce ( b) AC GROUND AC Cl<uAJD / \' j 0 f (t, c r < -c CrROV/Nj) AWAY {c) \METAL sucr.sce (rai CON7AC r tvj71/ L/t/NC-'-,{? MOt/tV!) Figure 1: Test setup fr printed circuit bard measurements, (a) test structure shwing reference planes, (b) detail f adaptr munting, and (c) detail f electrical cntact t grund plane f printed circuit bard. 6

7 EC1 1 0 tj _... GOA D cur SAvJ tajnt M s7 Y""\ S,....,..:' Ft r:i'::' :.::-:..::\. ': ;. 7 _.J><J>';"""""-';;'":---:.J&,;";;"';""""""_"';;"":"" ":"":::":'':'''::''':''- =--''':::'-''''':'''':':: '- l i 1. -r:'...y"": ".,;;---._----_._ -.. _- -_.:... :". -..:-: ". "..., -_ f r :--_------L/ --J rvts b 7 rvtsb7

8 Label Nminal Width DESCRPTON (mils) ms7 8 Micrstrip, Straight, Slid Grund ms6 13 ms5 16 ms4 20 ms3 25 ms2 50 ms1 100 ml7 8 Micrstrip, Straight, Lattice Grund ml6 13 ml5 16 ml4 20 ml3 25 ml2 50 mll 100 msb7 8 Micrstrip, Bend, Slid Grund msb6 13 msb5 16 rnsb4 20 msb3 25 msb2 50 rnsbl 100 mlb7 8 Micrstrip, Bend, Lattice Grund mlb6 13 mlb5 16 mlb4 20 mlb3 25 mlb2 50 mlbl 100 Table 1: Descriptin f nmenclature describing tracks. 8

9 8 mil Line n Slid Grund Plane SET EEsF - Tuchetne - 01/04/ PCBC (S11] PCB 08 [511] MEAS E+04 FREQ-MHZ 2. Cl+04 Figure 3: Cmparisn f measured and mdeled S11 magnitude versus frequency fr an 8 mil line abve a slid grund plane. (ms7 SET 3) 9

10 8 mil Line n Slid Grund Plane SET EEef - Tuchstne - Ol// pcac DB[522] PCB 08[522] MEAS s, E+04 FRED-MHZ 2.0E+O Figure 4: Cmparisn f measured and mdeled 8 22 magnitude versus frequency fr an 8 mil line abve a slid grund plane. (ms7 SET 3) 10

11 8 mil Line n Slid Grund Plane SET EEeF - TuchetnQ - 01/04/ PC8C [521] PCB 08[521] MEAS OE+04 Figure 5: Cmparisn f measured and mdeled S21 magnitude versus frequency fr an 8 mil line abve a slid grund plane. (ms7 SET 3) 11

12 8 mil Line n Slid Grund Plane SET EEsF - Tauen8tOne - 01/04/ PCBC ANG[S21J PCB ANG [521] MEAS EJ.OpCC -180.U FRED-MHZ Figure 6: Cmparisn f measured and mdeled 5 21 phase versus frequency fr an 8 mil line abve a slid grund plane. (rns7 SET 3) 12

13 PC B TRAct ;AJeRC;.S7RJ t. A c«ale,/l 1< Figure 7: Mdel f measurement set up. Mdel fitting is nt a straightfrward prcedure and the mdeling accuracy described here culd nt be btained by simply using the TOUCHSTONE ptimizer. The prcedure fllwed here was t use the measured physical length f a track and then t ptimize the phase match f 8 21 The magnitude match f 5 21 was achieved and finally a match t all the measurements was btained. Measurements and the mdeling prcedure were perfrmed fr track widths frm 8 t 100 mil ver slid and lattice planes and fr straight lines and lines with a single bend. A summary f the mdeling results are presented in Figure 8 and Tables 2 and 3. The calculated values were btained using the prgram ZOSTRP described in Appendix C. The calculated results are fr tracks with slid grund planes and it appears impssible t develp a physical mdel fr a track ver a lattice grund plane. The calculated characteristic impedance is reasnable agreement with that measured fr the slid grund plane test bard. Hwever the calculated lss is much less than that measured. The extra lss is either dielectric r radiative lss. One f the tasks f Phase will be determining the relative imprtance f each type f lss. 13

14 z \ \ ' \ \ (n) 60 X <, <, '0.-. X., <,... <, - <, "', "' " '-... x, <, <, <, <, "" <, "",<,0 Z <g 10D ()f Figure 8: Characteristic impedance versus track width w fr (a) calculated using ZOSTRP, (b) mdeled frm measurements with a lattice grund plane, and (c) mdeled frm measurements with a slid grund plane. 14

15 N. Nminal CHARACTERSTC MPEDANCE fel! Width calc- meas. meas. calc- meas. meas. ulated slid lattice ulated slid lattice (mils) (0) (0) (0) Table 2: Cmparisn f calculated and mdeled impedance, effective dielectric cnstant and lss f tracks. N. Nminal LOSS db/m Width calc- meas. meas. (mils) ulated slid lattice Table 3: Cmparisn f calculated and mdeled lsses. 15

16 N. Nminal LOADNG PER METER Width r c (mils) (0) (nh) (pf) Table 4: Calculated lading effects f lines at 1 GHz. 5 Simulatr Develpment n this sectin CAPNET a cmputer prgram fr the graphical capture, mdeling and analysis f transmissin line netwrks is intrduced. This prgram can be used t slve transmissin line netwrks s that the prpagatin f high speed digital pulses may be investigated. A cmplete descriptin f the technique used t slve the transmissin line netwrk and a descriptin f the prgram is presented in Appendix B. Basically, the prgram uses recursive tree structure representatins f the transmissin line netwrks, and recursive rutines t traverse the tree in rder t slve the netwrk. Fr a sinusidal excitatin f the netwrk, the prgram first cmputes and updates the prpagatin cnstant and characteristic impedance fr each sectin f transmissin line. Next, it recursively cmputes the impedances thrughut the netwrk string the impedances in the tree data structure. Finally, the current and vltage at all ndes are cmputed recursively starting frm the surce. The prgram des allw fr cascade sectins in the netwrk representing structures such as vias and bends as cmplex ABCD parameters. Time dmain results are btained by cmputing the frequency respnse f the netwrk at discrete frequencies and then using FFT's t cmpute time dmain respnses. The prgram currently mdels lads fr varius technlgies (TTL, LSTTL, STTL, etc. ) using functins which return impedance as functins f frequencies. The characteristic impedance and the prpagatin cnstant are calculated at each frequency directly frm the gemetry f the micrstrip line representing the printed circuit bard trace. The effects f lsses due t skin effect and lssy dielectrics and fringe effects are taken int cnsideratin. The prgram reads data abut different traces frm the file TRANS_TYPES.DAT which cntains a string fr the name f the trace ( "thin" fr example) and the thickness, height, width and dielectric cnstant f the material (see Figure 9. Thus a library f such traces and ther transmissin lines may be used. 16

17 C ROUTNES DESCRBNG LOADS 'include "graphpcnet.h" 'include math 'define pi #define RESST cmplex ttl(freq) flat freq; { cmplex z_ladj flat r,c,tmp,v; r=2000.0j c = 16e-12; v=2.0*pi*freq; tmp =.*r*cj tmp= 1 + tmp*tmpi z_lad.re = r/tmp; z_lad.im = (-1.0)*v*c*r*r/tmpj return(z_lad)j } cmplex sttl(freq) flat freq; { cmplex z_ladj flat r,c,tmp,vj r=280.0j c = 10e-12; v=2.0*pi*freq; tmp = r*c; tmp= 1 + tmp*tmp; z_lad.re = r/tmp; z_lad.im = (-1.0)*.*c*r*r/tmpj return(z_lad) j } cmplex ttlls(freq) flat freq; { cmplex z_lad; flt r.c.tmp,v; r= ; c = 10e-12; 1l=2.0*pi*freqj tmp :: v*r*c; tmp= 1 + tmp*tmp; z_lad.re = r/tmpi z_lad.im = (-1.0)*.*c*r*r/tmpi return(z_lad); } cmplex resist(freq) flat freq; { cmplex z_ladj } z_lad.re = RESSTj z_lad.im = 0.0; return(z_lad); cmplex via(freq) flat freq; { cmplex z_lad; } z_lad.re = 1.0e+8; z_lad.im = 0.0; return(z_lad)j FLE DESCRBNG TRACES USED SMULATON N PCB thin e via Figure 9: Trace file fr CAPNET. 17

18 Via d3 Lad Surce d1 d2 d4 dl :a 12.2 d2 :2 :M. d n d n Lad Figure 10: Example printed circuit bard trace. 19

19 .590 Printed Circuit Bard Resistive Respnse r e-2-t--_--f. -t J -_ Time (Nansec)" Figure 11: mpulse respnse. 20

20 Printed Circuit Bard Resistive Respnse J.. Time (Nansec).. Figure 12: mpulse respnse with expanded time scale. 21

21 .120 Printed Circuit Bard TTL mpulse Respnse 9.00e _-+ +-_--t-.. -f- ---_-4- -&--_ _ TTm (Nansec) Figure 13: mpulse respnse with TTL lad. 22

22 Printed Circuit Bard STTL mpulse Respnse TTme CNansec) Figure 14: mpulse respnse with STTL lad. 23

23 6 Technlgy Transfer The prducts f this prject delivered t BNR include a cmputer prgram fr simulating lssy micrstrip transmissin lines embedded in pssible lssy dielectric, establishment f a measurement capability, and establishment f a mdeling capability. Majr cntributins t BNR include clarificatin f the prblems that needs t be slved and frmulatin f a systematic plan t address them. The principal investigatr f this prject at Nrth Carlina Sate University has n many ccassins effectively acted as a cnsultant n printed circuit bard and system design issues that relate t transmissin lines and electrmagnetic fields. Furthermre he has acted as an academic advisr t varius members f the BNR staff undertaking graduate educatin. One result f university/industrial prjects such as this is change in the rientatin f curse cntent t help train peple in issues that are relevant t industry. 7 Plan f wrk This study invlves the investigatin f pulse prpagatin in printed circuit bard systems with emphasis n reflectins, crss-talk, and grund and pwer supply nise - phenmena that have been identified as having limiting effects n PCB perfrmance. With reference t these phenmena the fllwing issues are t be addressed. What sftware tls are available fr the simulatin and CAD f signal prpagatin in PCB systems? What lessns can be learned frm the well established prcedures fr the design and peratin f small planar analg circuits at micrwave frequencies? What design methdlgies can be adpted t imprve the rise- and fall-time perfrmance f new and existing PCB systems? What effect d multi-level bards have n pulse prpagatin perfrmance? Experimental characterizatin f pulse prpagatin in PCB systems. What new PCB materials are available with imprved high frequency perfrmance? Develpment f a cmputer prgram fr simulating the prpagatin f digital signals in PCB systems. Develpment f design rules fr the autmatic ruting design f PCB systems fr high frequency perfrmance. What is the effect f cupling and crss-talk n prpagatin perfrmance? prcedures can be fllwed t minimize this effect? What 24

24 What effect des the backplane have n intra-bard and inter-bard prpagatin perfrmance? Hw can this perfrmance be imprved? What is the effect f device lading and finite drive capability? What can be dne t minimize the effect n perfrmance f interchanging devices. Develpment f the plan f wrk fr phase was a majr aim f the first phase f the prject. t includes electrmagnetic characterizatin f the PCB systems, develpment f circuit mdels fr varius transmissin line discntinuities, and the develpment f linear transmissin line simulatin and CAD tls. As agreed upn the majrity f the measurements will be undertaken at BNR. The thrust f phase is t prduce usable results, althugh incmplete, in the first six mnths and t cmplete, dcument and augment the wrk in the final six mnths. Anther gal f phase will be develping methdlgies fr extending the transmissin line simulatr t nnlinear lads and drivers. t will be pssible t adapt this wrk t SCAMPER t imprve its ability t simulate cupled transmissin lines and ther PCB transmissin line structures. The Plan f wrk fr phase is as fllws Static Characterizatin f 4 layer bards Develpment f mdels fr printed circuit bard cnfiguratins fr fur layer bards. Experimental RF characterizatin f 4 layer bards. Reprt n PCB layut extractin. Experimental RF characterizatin f 6 layer bards. Develpment f mdels fr printed circuit bard cnfiguratins fr 6 layer bards. Reprt n decupling requirements based n experimental characterizatin and simulatins. Develpment f user friendly transmissin line prgram fr PCBs with linear lads. Reprt n efficient simulatin f transmissin line structures by numerical integratin prgrams like SCAMPER with prttype prgram and dcumentatin enabling incrpratin in SCAMPER. Reprt n future directins f prject. Enhancements t the transmissin line prgram fr PCBs Final reprt n Phase prepared in cperatin with BNR. 25

25 The final PCB CAD tl will be written in the C prgramming language and will be transprtable s that it can be used by engineers at BNR. Our current thinking is t prduce a prgram with inputs and utputs as fllws: nputs Characteristics f cnductr tracks (e.g. width, resistivity) n PCB and backplane. These may change with frequency. Physical tplgy. layut. This will include the specificatins f line lengths and physical Line terminatins and characteristics f drivers. Perfrmance specificatins including rise- and fall-time, crsstalk levels (nise margin), versht and undersht limits etc. Output» Characteristics f signals at the end f cnductr lines - e.g. rise-time, fall-time, versht, ringing. Circuit lading. Crsstalk, nise margin levels. Flag indicating whether specificatins at an individual nde have been met. Other utputs as yet unspecified. The third phase f this prject is envisaged t t cncentrate n integrating the sftware develped as part f this prject in existing PCB CAD tls - particularly thse at Bell Nrthern Research. At this stage it is planned t extend the the CAD tl develped in Phase tw mdules - ne mdule being a design rule generatr and design checker prir t aut-ruting and the ther mdule perfrming simulatin f the circuit bard system. t anticipated that the secnd mdule will functin as a pre- and pst-prcessr t a general purpse circuit simulatin package such as SCAMPER r SPCE. As much as pssible the mdules develped in the third phase will be interfaced directly t Bell Nrthern Research's current circuit bard design system. A mre detailed plan f wrk fr Phase will be frmulated when Phase is cmpleted and Phase is in prgress. There are tw main research aspects in Phase. The first is experimental characterizatin f digital systems incrprating printed circuit bards with the aim f identifying and mdeling thse structures that result in reflectins, crss-talk, and grund and supply nise. Prpsed slutins will als be verified experimentally. The secnd aspect is develpment f Cmputer Aided Design (CAD) tls fr the design f the transmissin netwrks in PCB systems. This CAD tl will be written in the C prgramming language and will be transprtable s that it can be used by engineers at BNR. 26

26 8 Cnclusins The majr results f phase f the prject were identificatin f the prblems encuntered in the design f printed circuit bards with high speed digital signals, a literature review f the printed circuit bard simulatin appraches, and develpment f a plan f wrk fr phase f the prject. As well it was cncluded that circuit bards with slid rather than lattice grund and supply planes shuld be used fr cntrlled impedance applicatins. References [1] J.D. Kraus, K.R. Carver, Electrrtiaqnetics, McGraw-Hill, New Yrk, 1973, 2 nd Editin. [2] Y. Fukuka, Q. Zhang, D.P. Neikirk, T. th, Analysis f multilayer intercnnectin lines fr a high-speed digital, integrated circuit, EEE Trans, Micrwave Thery Tech.,!',lTT-33, June 1985,527. [3] C.D. Taylr, G.N. Elkhuri, T.E. Wade, On the parasitic capacitances f multilevel parallel metallizatin lines, EEE Trans. Electrn Devices, Nvember 1985, ED-32, [4] H.A. Wheeler, Transmissin-line prperties f a strip n a dielectric sheet n a plane, EEE Trans. Micruiae Thery Tech., rvtt-25, August 1977, [5] E.D. Sunde, Theretical fundamentals f pulse transmissin, and, The Bell SY/Jtem Technical Jurn., June and July, [6] F.K. Amura, J.B. O'Neal, Analysis f distributin line carrier prpagatin using the bus impedance, matrix, submitted t EEE PES cmmittee n Pwer Sy.stem Cmmunicatin, [7] K.C. Gupta, Ramesh Garg,.J. Bahl, Micrstrip Lines and Sltlines, Dedham:Artech Huse, [8].V. Lindell, On the quasi-tem mdes in inhmgeneus multicnductr transmissin, lines, EEE Trans. Micruiave Thery Tech. vtt-29, August 1981, [9] H.B. Bakglu, J.D. Meindl, Optimal intercnnectin circuits fr VLS, EEE Trans. Electrn Devices, May 1985, ED-32, [10] TOUCHSTONE, EEsf nc., vvestlake Village, CA. [11] SUPERCOMPACT, Cmmunicatins Cnsulting Crp., Patersn, NJ. 27

27 Appendix A. Review f micrstrip transmissin line studies and simulatins 28

28 An verview f Micrvstrip Transmissin Line Systems Cuntless papers have been written n almst every aspect f micrstrip transmissin line systems (MTL) in the last decade. While many prvide helpful infrmatin fr specific prblems, few address the system level prblem. Simulating special cases is ne thing but handling an entire MTL system such as fund in a printed circuit bard (PCB) r a VLS chip is utside f their range. This paper reviews what's been studied in the areas f MTLs, cupling and discntinuities. We'll als lk at what useful infrmatin can be gleaned frm these scres t papers and which nes can prvide useful tls fr further wrk. 29

29 A Review f Micrstrip Transmissin Line Studies and Simulatins There have been cuntless papers written n transmissin lines and micrstrip transmissin lines in particular in recent years ranging frm detailed electrmagnetic fields analysis t experimental studies f just abut anything ne is interested in. n this paper we'll lk at several majrs aspects f these publicatins and. in particular thse dealing with simulatin f micrstrip and cupled micrstrip lines. The significant papers f interest t this review and the micrstrip print circuit bard (PCB) transmissin line simulatr prject can be lumped int three general categries: 1. Micrstrip Transmissin Line Thery 2. Cupled Transmissin Lines 3. Discntinuities and Characterizatin f Micrstrip Lines The papers n General Transmissin Line Thery wn't be discussed in this review except as they pertain t the ther papers. The papers dealing with general Micrstrip Thery are "nly" imprtant as they prvide backgrund infrmatin and ideas that the simulatin and characterizatin papers use as their basis. Of mst interest are thse papers dealing with cupling phenmenn in micrstrip lines; especially thse that simulate multiple cupled lines. The handling f cupled lines is the single mst difficult task in simulating an entire system f intercnnect lines, whether they be n an e r a printed circuit bard. Since each line can cuple t any ther line in the system, the prblem becmes hrrendus if a simple brute frce SPCE simulatin using lumped element mdels is used. We'll see hw many peple have attempted t handle this prblem in different 30

30 A Reyiw f Mir t[ip Transmissin Line Studies a.nd SimulatiQDs There have been cuntless papers written n transmissin lines and micrstrip transmissin lines in particular in recent years ranging frm detailed electrmagnetic fields analysis t experimental studies f just abut anything ne is interested in. n this paper we'll lk at several majrs aspects f these publicatins and in particular thse dealing with simulatin f micrstrip and cupled micrstrip lines. The significant papers f interest t this review and the micrstrip print circuit bard (PCB) transmissin line simulatr prject can be lumped int three general categries: 1. Micrstrip Transmissin Line Thery 2. Cupled Transmissin Lines 3. Discntinuities and Characterizatin f Micrstrip Lines The papers n General Transmissin Line Thery wn't be discussed in this review except as they pertain t the ther papers. The papers dealing with general Micrstrip Thery are Bnly " imprtant as they prvide backgrund infrmatin and ideas that the simulatin and characterizatin papers use as their basis. Of mst interest are thse papers dealing with cupling phenmenn in micrstrip lines; especially thse that simulate multiple cupled lines. The handling f cupled lines is the single mst difficult task in simulating an entire system f intercnnect lines, whether they be n an e r a printed circuit bard. Since each line can cuple t any ther line in the system, the prblem becmes hrrendus if a simple brute frce SPCE simulatin using lumped element mdels is used. We'll see hw many peple have attempted t handle this prblem in different 31

31 ways, each having its' wn tradeffs, advantages and weaknesses. The last grup f papers is imprtant in develping realistic mdels and fr measuring situatins in the real wrld if the result f the wrk is t have any credibility. T many papers cmpare their theretical results with ther's theretical calculatins which desn't have the same meaning as cmparisn t real experimental measurements. n a recent database search f all abstracts cncerning micrstrip transmissin lines, ver 700 papers were fund t have been published ver the past few years n this subject. Everything frm measurement methds t design guides fr micrstrip transmissin line (MTL) layuts were retrieved. Many f these papers were geared twards analysing in detail the varius.phenmeun and prblem areas invlved in using MTLs n circuit bards, VLS chips.and mnlithic micrwave integrated circuits (fmcs). The publicatins f particular interest fr this prject were thse studying the characterizatin f MTLs, discntinuities in MTLs (bends, vias, etc.), and cupling between lines. T summarize very briefly, many f these papers were well written and had sund methds and cnclusins. The handling f discntinuities was prbably the mst straightfrward f the methds since a discntinuity is usually very lcalized (spatial) and deriving either an RLC lumped mdel r an S parameter representatin f it is fairly simple. The characterizatin f the lines, including dispersin, characteristic impedance, attenuatin and radiatin as functins f frequency were als handled fairly well. The real nagging prblem is cupling/crsstalk between lines. At first glance there seems t be several very different methds fr handling this prblem but n clser exami 32

32 natin we see that there are nly tw majr appraches in use. The first is t mdel the cupling as either a lumped r distributed lumped" RLC system and use a circuit analysis prgram like SPCE t calculate the system respnse. The variatin between papers f this genre cncern the methd f calculatin used t cmpute the [L] and [el matrices. As might be expected, the tradeff in accuracy vs cmputatin time is present with this methd; the mre"distributed" the mdel the higher the accuracy but at a price f lnger cmputatin time. Als, fr systems f MTLs f mre than a few lines, the cmputatin times becme hrrendus and methds t relieve this burden were the next area investigated by researchers in this field. The ther methd fr handling cupled lines invlves cming up with a netwrk f sme srt t include befre and after the system f uncupled MTLs that handles the cupling while the lines themselves are mdeled as simpie uncupled lines. The mst cmmn netwrk fr this methd cnsist f resistrs and vltage and current cntrlled surces. The differences in the papers using this general methd cncerns hw the decupling is perfrmed and the cntrl equatins that gvern the dependent surces. All f the papers either assume strict TEM mde prpagatin r at least quasi- TEM prpagatin. Mst make the assumptin that the "n" cupled lines under study are all parallel and many assume further that they are all in the same plane. Almst all f the MTL papers cncern themselves with just the transmissin lines themselves and few, if any, take int accunt the effect f nnlinear lads n the signals n the lines. n fairness, it's nted that methds using SPCE r similar prgrams can incrprate these effects separately but this just further increases the amunt f cmputatin time required. 33

33 Fr a circuit simulatr f any type t be f practical use, the respnse time must be kept as fast as pssible fr the user t keep "n track" their line f investigatin. Furthermre, since changes in a circuit design r layut are usually incremental (the slate is seldm wiped clean every time a prblem is encuntered r a change is made t a design) there shuld be a methd f using this t the simulatrs advantage and nt have t recmpute everything, including thse areas far remved frm the place f change. Many VLS CAD tls in use tday use this fact in changes layuts t insert r remve parts f the design and simulatrs such as ASTAP tradeff initial cmputatin time fr faster respnse calculatin f small changes in the initial circuit and cnditins. What needs investigatin in this area is better methds f handling cupling and better methdlgies in appraching a cmplex system that allws Cr incremental changes in the design withut requiring the recalculatin f every parameter invlved. Sme use f the hierarchy f a layut shuld be incrprated; hierarchy is explited in the design f the circuits themselves s why nt use it in the analysis f the MTL prblem? CQuplin f micrstrip transmissin lines: what's been accmplished? T understand what still needs t be dne, ne must examine what has already been accmplished. Hw well d sme f these methds wrk? Hw d they wrk and is there a better way? 34

34 The first step is t decide what's imprtant and what isn't. deally, we'd like t handle the cupling between all the lines in a system, regardless f layut and physical distance between lines. n practice with hundreds if nt thusands f lines we need t ask; is this REALLY necessary? D we indeed need t knw the effects f a line n ne side f a system t ne n the ther side? Cmmn sense must als be incrprated int the design f such a simulatr but we must be careful that "cmmn sense" desn't get us int truble; cmmn sense tells us that the sun revlves arund the earth, desn't it? Obviusly lines that are immediately adjacent t each ther are ging t have the mst prblem with cupling and perhaps that is where we shuld lk first. The wrst case cnditin is when tw lines run parallel fr lng runs, allwing the highest degree f crsstalk between them. Lines crssing at right angles have less crsstalk and lines that are far remved frm the line in questin have (prbably) the least effect. Many f the theretical studies dne have assumed that the cupled lines run parallel t each ther and sme assume further that they have the same dimensins; width, length, etc. Fr strictly theretical studies this culd be cnsidered a valid set f assumptins but fr the practical circuit designer creating electrnic systems fr a living, these are extremely limiting rules. Designing a PCB, fr example, with n bends, n vias and n crssing lines wuld be difficult at best... especially if the lines must be in the same plane! Several papers have been published by Vijai Tripathi and his assciates at Oregn State University mdeling cupling and crsstalk in micrstrip transmissin line systems. Mst f their wrk invlves generating lumped element mdels f ne srt r anther t 35

35 be used in SPCE r a similar circuit analysis tl. n ne such paper (Tri 87) the case f multilevel intercnnectins as cmmnly fund in integrated circuits and PCBs is analyzed fr their time dmain characteristics. Their methd invlves the straightfrward slutin f the general transmissin line equatins: am = -[R][i] - [L]alil az at alil = -[G][v] - [Gla M az at The result is used in a SPCE mdel utilizing vltage cntrlled vltage surces and vltage cntrlled current surces tgether with linear uncupled transmissin line mdels t mdel the system f intercnnects. An example f this fr N parallel transmissin lines is shwn in Figure 1. A 1985 paper (Tri 85) cncerns much the same things as the previus paper but prvides a better backgrund f the slutin f the transmissin line equatins and the cnstruetin f the mdel used in SPCE. Anther apprach t the prblem is fund in a paper by F.Y Chang (Cha 70) where he intrduces the use f "cngruence" transfrmers t mdel the effects f crss talk. Actually this is an intermediate step since the system f transmissin lines is ultimately mdeled by a resistive netwrk and vltage cntrlled vltage surces... the cngruence transfrmers help t visualize and set up the prblem. This transfrmer is shwn in Figure 2; the right hand side r primary side represents the vltage and current (e and J) 36

36 fund at the input terminals t the system. The left hand r secndary side represents the applied vltages and currents (V and ) t the system f transmissin lines. The turns ratis fr the transfrmer are cntained in the matrix [X] and they represent the amunt f cupling frm each line t each f the ther lines. t is this turns rati matrix, [X], that's the key t analyzing the cupling prblem and unfrtunately it is prbably the least talked abut in the paper. T understand this paper better and in particular the calculatins f the turns rati matrix, tw ther papers are almst required reading (Wee 70) and (Gre 65). Furthermre, a key assumptin that structure supprts TEM mde prpagatin is made, allwing the inductance matrix t be calculated directly frm the capacitance matrix. f we assume TEM prpagatin, then the velcity f prpagatin is related t the inductance and capacitance per unit length by; V = VLC and thus L = l/vj C- 1 A third step is necessary t find the transient respnse f this system, requiring the creatin f a resistive netwrk representatin f 'the a-cnductrs. After additinal manipulatin, the netwrk indicated in Figure 3 is arrived at which cntains nly vltages cntrlled surces and resistrs. The terminal vltages and currents are immediately available frm utside the netwrk. This is an interesting methd but it t invlves cnsiderable cmputatin especially in calculating the capacitance matrix, inverting it t find the inductance matrix, and calculating the turns rati matrix. Any changes t the tplgy f the circuit wuld require recalculatin f all these matrices and it is dubtful that this methd wuld have 37

37 sufficient speed t be a credible tl fr designers f cmplex intercnnect systems. A fllw-up paper t Tripathi's wrk n SPCE mdels fr cupled transmissin line systems is an article by Rme and Santmaur (Rm 87) in which they derive a simplified mdel frm the general mdel purpsed by Tripathi. n ding s, they've had t make several simplifying assumptins and restricted the type f transmissin line systerns that can be mdeled with their methd. The first f the assumptins, like many thers, assumes strict TEM mde wave prpagatin. Thus they slve the telegraphists equatins relating vltages and currents as functins f psitin and time. Their methd cnsists f calculating an equivalent netwrk fr the system f transmissin lines that cnsists f n uncupled lines and a transfrmatin netwrk at the beginning and end f the lines cntaining dependent surces which mdel the cupling effects. Their algrithm (in utline) is: 1. Cmpute eigenvalues f [L] and [C) given the number f lines, n. 2. Cmpute [M], the matrix f right eigenvectrs f [L] & [C] 3. Derive the cntrl law" fr each dependent surce in the transfrmatin netwrk. 4. Calculate the characteristic impedance, Z and the time delay per unit length, W fr each line. n calculating these varius parameters and cntrl laws, tw key assumptins have been made n the physical layut and the effects f nearfar cupling n a given line. n rder t keep [L) and [C] tridiagnal (fr calculatin simplicity) it is assumed that each line is cupled nly t thse immediately adjacent t it. Any ther lines mre than ne remved frm the line in questin are assumed therefre t have n effect n the 38

38 line. The lines are als assumed t be f identical length and equally spaced. The reasning behind this assumptin underlies the fact that wrst case cupling and crsstalk ccurs fr lng runs f parallel lines such as might be seen in a data bus system. By making these assumptins, they have reduced (L] and [C) t tridiagnal, symmetric Teplitz matrices which have nice cmputatinal prperties. Using the assumptin f TEM mde prpagatin and unifrm, equal length lines, Das and Prasad (Das 84) have perfrmed an analysis f the cupled line prblem using a Green's functin frmulatin. The cupling capacitance and inductance n a per unit length basis were calculated fr the cnfiguratin shwn in Figure 4. Clsed frm equatins were derived and the cupling cefficients due t the line capacitance/inductance can be fund directly fr the case f: 1. Symmetric striplines; cplanar cnductrs appearing midway between grund planes. 2. Single layer micrstrip structures 3. Offset parallel striplines; parallel lines f equal width n different layers. The chief disadvantage t their methd is that nly tw lines at a time can be handled. The main advantage is the use f clsed frm equatins requiring n iteratins t calculate the cupling cefficients. T the "immediately adjacent" assumptin is used [i.e. nly lines right next t each ther are imprtant) than this technique culd prve very useful and ptentially faster than ther, mre general methds. A unique apprach t the cupled line prblem that is mre realistic than mst is ne used by Razban in a paper cncerned with the transient analysis f cupled lines. The 39

39 parallel lines are gruped int bundles called "tubes' where all the lines in a tube are equally spaced and f the same length. The cupling between lines in a tube are analyzed using the methd f characteristics (Bra 76) and each tube is mdeled as an equivalent circuit cnsisting f resistrs and dependent vltage surces (see Figure 5). When tubes f different rders meet (i.e. tubes with different numbers f cupled lines), the interface is handled as shwn in Figure 5. The resistrs and surces are fund as a result f applying "dilatatin" and "shrinkage" peratrs. The figures shw the case where an interface between tw sets f tubes, p and q (N p > N q ) is mdeled. The dilatatin peratr is used t handle signals running frm Tp t Tq and the shrinkage peratr handles the signals ging the ther way. Prviding bth a theretical and experimental apprach t the prblem, Seki and Hasegawa have written a paper cncerned with cupling/crsstalk in high speed VLS circuits (Sek 84). Even thugh their main cncern was in l'c the same theries and cnclusins shuld hld fr PCB micrstrip transmissin lines as they made n scale assumptins that wuld limit the wrk t micrn size structures. What is unique abut their methd is the use f a peridic, infinite bundary cnditin. n ther wrds, they assume that the n-cnductr MTL circuit under study is repeated infinitely many times n either side. They shw later in the paper that this is nt such a bad assumptin and the slutins give very gd first rder results and lend themselves t transient analysis well. The ther assumptin made cncerns the methd f excitatin f the n-lines; they assume that the phase angle difference fr vltage and current frm ne line t the next is a cnstant. 40

40 The slutin fr vltage and current as a functin f distance fr any f the lines allws the pulse respnse t be calculated directly by perfrming a numerical inverse Laplace transfrm f these tw equatins. What makes this paper all the mre interesting is their cnclusins that they draw as a result f several "experiments" run using this methd fr varius circuit tplgies. n particular they calculated the pulse respnse f a terminated line adjacent t a driven line fr cases where all ther lines were terminated r left pen. Their results match this authrs experience with such cases which shw much higher crsstalk amplitude fr the unterminated case versus the terminated lines. The last paper that will be discussed here cncerning cupling in MTL systems is ne by Yang, Kng and Gu which is a perturbatinal analysis f nnunifrmly cupled lines. n their case, nly pairs f lines were studied but the lines culd have nnunifrm cupling cefficients as a functin f distance dwn the lines. nstead f perfrming a numerical integratin f the cupled transmissin line equatins, the authrs elected t perfrm a cdirectinal-cntradirectinal transfrmatin -fr the decmpsitin f cupled-mde equatins. The methd f characteristics is then used t find a set f differential equatins alng a characteristic curve. Rather than integrate this equatin numerically (tedius since the d.e.'s are cupled) a perturbatinal series was intrduced. The result f all this is a set f zer rder equatins that have clsed frm slutins. Furthermre, all higher mde terms are generated frm a single integratin ver the previus terms. The key advantage then is a set f first rder, clsed frm 41

41 equatins gverning the cupling' phenmenn between the lines. The ther significant advantage t their apprach that the higher rder terms can be directly interpreted as reflectins alng the lines. A!3 we've seen, there are numerus papers discussing the prblem f cupling in MTL systems but virtually nne cncerned with the verall MTL prblem. A!3 we nted earlier, mst f these papers are gd fr largely academic studies but have s many limitatins and assumptins made that they are nt real useful fr studying a cmplex MTL systems such as fund in a PCB. As tls fr analyzing specific situatins and fr creating a database t be used by a simulatr they are imprtant, but nt fr handling a cmplex MTL prblem by themselves. Micrstrip Discntinuities When perating at high frequencies (synnymus with fast rise/fall times in digital circuits) the effect f simple bends r 'T' junctins becme increasingly imprtant. Bends (especially right angle bends), vias, tees, step-widths and ther shapes all have the unpleasant effect f adding unwanted inductances and capacitances t the circuit. What appears t be a simple intercnnectin n a schematic can becme a meandering line n a PCB r C. The extra cmpnents "hidden" amng the bends and vias can have a significant rle in the unding f an therwise sund design. By themselves a few discntinuities may have little effect n the transmitted signal but in cnjunctin with all the ther pitfalls f transmissin lines, the integrity f the system can be dis- 42

42 rupted. There are tw philsphies when it cmes t evaluating the effects f discntinuities (particularly micrstrip discntinuities) n circuit perfrmance. One can calculate the parasitic elements f a discntinuity and use a lumped parameter mdel in a SPCE type simulatr. This by nature is a srt f "after the fact" apprach since ne needs t knw the physical layut t calculate the equivalent circuit. f sme frm f autruting f the intercnnect lines is used, then the ruter must be run and its utput passed t a parasitic element extractr t btain the SPCE mdels. On the ther hand, knwledge f the relative discntinuity f varius features can be used befre hand t guide the ruting prcess. A critical subcircuit culd be simulated in part n SPCE and the sensitivity t varius discntinuities culd be examined. These results culd then be used by the ruter, alng with discntinuity design rules, t select apprpriate ruting... shuld fur bends r tw vias be used? There are prs and cns t bth sides but in ne frm r anther discntinuities msut eventually be taken int accunt. As digital circuit speeds increase t ever faster rates, the adverse effects f such simple structures as bends and vias will draw clser t the surface, waiting fr the unsuspecting designer t stumble acrss them. Several papers have been written in recent years cncerning varius aspects f micrstrip transmissin line discntinuities, ranging frm theretical calculatins t experimental techniques and measurements. As many f them are similar in their results, 43