First International Computer,Inc Protable Computer Group HW Department

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1 irst International omputer,inc Protable omputer roup W epartment oard name : Mother oard chematic. chematic Page escription : Project : P. PI & IRQ & M escription : Version : 0. Initial ate : January, 00. lock iagram :. Nat name escription :. oard tack up escription :. chematic modify Item and istory :. power on & off & equence :. Layout uideline :. switch setting Manager ign by: ngus o rawing by : parc an Total confirm by: LN ircuit check by: udio ircuit check by: I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number R ev 0. 0,, 00 ate: heet of

2 . chematic Page escription : P chematic Ver : 0... chematic Page escription. lock iagram. NNOTTION. chematic Modify. Timing iagram. R Layout uideline. anias eleron(/). anias eleron(/) 0. POWR (PU OR). Thermal / VR_PWR / RT. lock enerator. lock uffer. PN00 (/). PN00 (/). PN00 (/). PN00 (/). PN00 (/). R RI TRMINTION 0. R O-IMM. R PULL UP. VT LV Transmitter. L onnector IL PIINT IRQ IRQ IRQ IRQ IP IP UMTR R Q RQ0 / NT0 RQ / NT RQ / NT RQ / NT RQ / NT Mini PI(Wireless LN) ardus MiniPI/N MiniPI/ardus MiniPI IP MiniPI ardus Mini PI(Wireless LN). RT onnector.vt (/).VT (/). VT (/). Power ood & an ontroller. 0 ardu ontroller 0. RU POWR W./NN. alexico MINI PI. VT0L PY. U NN. / -ROM NN. VT uper I/O. LP PMU0. LP K MX. INT K / rid P onnector. M onnector 0. IP witch & utton. irm Ware ub / LI witch. Reset ircuit. OVP / RW. L udio odec. MT0 udio mplifier. earphone Out/ PI. PI & IRQ & M escription : IRQ hannel IRQ0 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ0 IRQ IRQ IRQ IRQ IRQ esciption ystem timer Keyboard (asacde) LN / MOM erial Port UIO / V / U LOPPY IK L PT R T PI (isable by default) IR (MOM/LN) ardbus P/ mouse PU ROM. MI In. IN&IN. Power (PMUV/V) 0. harge ircuit. IN & attery elect. MIN TTRY NN. V & V. V & V. VM & VM..V & VP. ystem Power (). ystem Power (). Inverter ontroller M hannel M0 evice IR M P M LOPPY IK M UIO M (ascade) M Unused M Unused M Unused (disable by default) (MOM / LN) I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number R ev chematic Page & PI & IRQ & M escription 0.,, 00 ate: heet of

3 . lock iagram : LK I0 P IN P V/V P RT L Thermal ensor -Video Port P P P RJ- P PMUV/V P V/V P VM/VM P.V/M P R.VM P.V/M P Over Voltage Protect P attery charger P0 attery elect P P LN Phy VT0L U, P Mini PI TV Out VTM VT LV Tx U.0 P P P P U0, MII U PMI N0 P P it PI U Intel anias eleron Processor ost us VI PN00 u P~P VT P,, P, ub Interface I U LP U K/ TRL LP MX INT K/ PMI LOT0 P0 Mem us I U P ROM P P -Link P PU OR P0 PU VP P R RI TRMINTION R OIMM L ROM ( /W ub) M N NN P P P P0 ' O L P M NN P LP PMU0 P udio MP PON P Mic IN P LK uffer R Pull up PI Pull up/own LI/IP W MIN W NN P P P P P0, P0 T ON P attery Voltage sense P N P P0 RT P RT P I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number R ev LOK IRM 0. 0,, 00 ate: heet of

4 . Nat name escription :.oard tack up escription Voltage Rails IN PMUV PMUV V V V V VM VM VM Vcore_PU VP.VM R_.VM.VM.V.V.V Primary system power supply.0v always on power rail by LT or IN.V always on power rail by LT or IN.0V always on power rail by ON or PU0.V always on power rail by ON or PU0.V power rail.0v power rail V switched power rail.v switched power rail.0v switched power rail ore Voltage for PU.V~0.V.0V for TL+ Termination Voltage.V for PU PLL Voltage.V R Termination Voltage.V switched power rail.v power rail.v always on power rail.v power rail for R POWR RIL VOR_PU VP.VM TINTION anias anias MontaraM anias (PLL) IM (PLL) P Layers Layer Layer Layer Layer Layer Layer VOLT 0.~.V 0.-.0V.V 0 URRNT omponent ide, Microstrip signal Layer round Plane tripline Layer(TL,LOK,R) tripline Layer(nalog,LV,other) Power Plane older ide,microstrip signal Layer Part Naming onventions N L Q R RP U Y = = = = = = = = = = apacitor onnector iode use Inductor Transistor Resistor Resistor Pack rbitrary Logic evice rystal and Osc Net Name uffix 0 = ctive Low signal.vm.v MontaraM (LV,, VO) IM (OR) MontaraM (R, LVIO) R RM R.V.V.VM R RM.V.V VM V 0. (0.0, 0.0, 0.0) 0.. (.0, 0.0) (Run.0(Idle). Mark) IM (U).V 0.0 IM (IO).V 0. R 0. MiniPI W IO LP K 0.00 (Idle) O 0.0 (Idle) LK N 0. LV 0. R.V RTL00L 0. MiniPI PMI V ignal onditioning Q L_ = = = amped (by a resistor) Isolated (by a Q-switch) iltered (by an inductor or bead) V VM V V PMUV IM (U) MP00 ROM INT K/ INT M INVRTR PMI V IM U PMU0.V (Idle) 0. (Run) 0.0 (Idle) 0.~0.(Run) 0.0 (Idle) 0. (Run) 0.0 PMUV I_ (Idle) 0. 0U (Run) I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number R ev NNOTTION 0. 0,, 00 ate: heet of

5 .chematic modify Item and istory : I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number Rev Version Notice 0., 0, P 00 ate: heet of

6 . power on & off & equence : Power On equencing Timing iagram VI VR_ON Tsft_star_vcc Vboot Vid Vcc-core Tboot Tboot-vid-tr PU_UP Tcpu_up Vccp Vccp_UP Tvccp_up Vccgmch MPWR Tgmch_pwrgd LK_NL# IMVP_PWR Tcpu_pwrgd TTRY ONLY POWR ON TIMIN POWW0 PMUV/PMUV UPN N RUM TIMIN POWW0 PMUV/PMUV ON ON V MINW0_I To I V PM_RMRT0 PM_LP_0 To I_M rom I_M PM_RTRT0 PM_LP_0/0/0 PU0 UTT_0 To I rom I rom I_0 rom I_0 PM_LP_0/0 PU0 UTT_0 V VM rom I_M rom I_0 rom I_0 VM,V PM_PWROK PM_PWROK Y_PWROK VRON_VP.V N R_PWR Y_PWROK VP,.VM VRON_VP VP/.VM VOR_ON VOR_ON VR_ON VR_ON VOR_PU VOR_PU K0_PWR0 To clock generator To OM and I K0_PWR0 PM_VT To clock enerator ToI and OM PM_VT rom I to PU PU_PWROO rom I to PU PU_PWR PI_RT0 PI_RT0 To OM/other PI device TL+_PURT0 To OM/other PI device TL+_PURT0 rom OM to PU rom OM to PU I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number R ev Montara M power on/off s timing 0. 0,, 00 ate: heet of

7 . Layout uideline : Montara-M R Layout uidelines Note that all length matching formulas are based on M die-pad to O-IMM pin total length LOK LNT TR / P NOT roup locks ata ontrol ommand P R ignal roups eedback ignal Name K[:0] K#[:0] Q[:0] Q[:0] M[:0] K[:0] #[:0] M[:,:0] [:0] R# # W# M[,,,] M[,,,] RVNOUT# RVNIN# lock ignals Topologies and Routing uidelines M Pin P Package Length Range L Min:0." Max:.0" Length Matching ormulas ignal roup ontrol to lock ommand to lock P to lock trobe to lock ata to trobe O-IMM P Minimum Length Maximum Length lock -.0" lock -.0" lock -.0" lock -.0" lock + 0." lock +.0" lock + 0." lock + 0." trobe - mils trobe + mils mil trace, mil pair space lock length tolerenve within the pair : +/- 0 mil lock to lock Length Matching : +/- mils Minimum Pair to Pair pacing : 0 mils Minimum pacing to other ignals : 0 mils LKPU[..0] LKN[..0] LKITP[..0] MLK_I MLK_M PLK_TI PLKI PLK PLK PLKU0 PLKOP PLKW PLKIO PLKLN MLK_IO MLK_I MLK_ MLK_I MLK_ " ~ "." ~.0 " MX :."."~.0"."~.0"." ~." / 0 mils ( mil space between + & - ) / 0 mils / 0 mils / 0 mils / 0 mils.ifferentials pairs with the same length (within 0 mil).pu & N trace mismatch within 0 mil * MLK_I & PLK_M PLK_TI Length mismatch within 00 mils.making PI length with minimum various.max skew = ns ata ignals Topologies and Routing uidelines M Pin P Package Length Range L L L L O-IMM0 P O-IMM P ohm % Minimun pacing to Trace Width Ratio, Q/M : to Q : to Minimum pacing to other ignals : 0 mils Trace Length L : Min 0.", Max." L : Max 0." L : Min 0.", Max.0" L : Max.0 " Length Matching : Q to K/K# Q OIMM0 P+L+L Q, OIMM P+L+L+L Min : lock -.0", Max : lock + 0." Q/M to Q : +/- mils Q/M to Q Mapping ignal Mask Relative To Q[..0] Q[..] Q[..] Q[..] Q[..] Q[..0] Q[..] Q[..] Q[..] M[0] M[] M[] M[] M[] M[] M[] M[] M[] Q[0] Q[] Q[] Q[] Q[] Q[] Q[] Q[] Q[] Mismatching +/- mil +/- mil +/- mil +/- mil +/- mil +/- mil +/- mil +/- mil +/- mil ontrol ignals Topologies and Routing uidelines M Pin P Package Length Range L O-IMM0, P ommand ignals Topologies and Routing uidelines M Pin P Package Length Range L L L 0 ohm % L L O-IMM P ohm % ohm % Trace spacing to trace width ratio : to Minimum pacing to other ignals : 0 mils Trace Length L : Min 0.", Max." L : Max.0" Length Matching : TRL(P+L) to K/K# Min : lock -.0", Max : lock + 0." Trace spacing to trace width ratio : to Minimum pacing to other ignals : 0 mils Trace Length L : Min 0.", Max.0" L Max.0" L : Max.0" L+L : Max.0" L : Max.0" Length Matching : M to K/K# M OIMM0 P+L+L M, OIMM P+L+L Min : lock -.0", Max : lock +.0" P ignals Topologies and Routing uidelines M Pin P Package Length Range L O-IMM0, P L ohm % Trace spacing to trace width ratio : to Minimum pacing to other ignals : 0 mils Trace Length L : Min 0.", Max." L : Max.0" Length Matching : P(P+L) to K/K# Min : lock -.0", Max : lock + 0." I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- O-IMM0 P P (PN00 + VT) ize ocument Number R ev Montara M R Layout uideline 0. 0,, 00 ate: heet of

8 ystem us ommon lock ignal Layout uide : TL+_0[..] TL+_0[..0] <,,,,> VP <> TL+_0[..] TL+_0[..0] <> #, NR#, PRI#, R0#, Y#, R#, PWR#, RY#, IT#, ITM#, LOK#, U- R[..0]#, TRY#, RT#. Transmission Line Type Total Trace Length Normal Impedance pacing (mils) TL+_0 P * _0M0 R 0 % /W 00 TL+_0 # U TL+_00 * _INN0 R00 0 % /W 00 TL+_0 # 0# trip-line(int. Layer).0 ~. inch +/-0% & (Int. Layer) V TL+_0 * _INTR R 0 % /W 00 TL+_0 # # Micro-strip(xt. Layer) & 0(xt. Layer) R TL+_0 * _NMI R0 0 % /W 00 TL+_0 # # V TL+_0 * _MI0 R 0 % /W 00 TL+_0 # # W TL+_0 _TPLK0 R 0 % /W 00 TL+_0 # # T TL+_0 _PULP0 R 0 % /W 00 TL+_00 # # TL+_0 PU_PLP0 ource ynchronous T : W R 0 % /W 00 TL+_0 0# # Y 0 TL+_0 _INIT0 R 0 % /W 00 TL+_0 # # T#[..0], INV#[..0], TN#[..0], TP#[..0] Y 0 TL+_0 TL+_0 # # U TL+_0 Transmission Line Type Total Trace Length Normal Impedance pacing (mils) TL+_0 # # TL+_00 PM00 R 0 % /W 00 TL+_0 # 0# Y TL+_0 PM0 R 0 % /W 00 trip-line.0 ~. inch +/-0% & TL+_0 # # TL+_0 PM0 R 0 % /W 00 # # TL+_0 PM0 R 0 % /W 00 # TL+_0 # ignals Name ignals Matching trobes associated trobe Matching TL+_0 <> TL+_T00 U T0# # with the group TL+_RQ00 R ITP_RT0 R 0 % /W 00 TL+_RQ0 RQ0# INV0# TL+_INV00 <> T#[..0], INV0# +/- 00 mils TP0#,TN0# +/- mils P TL+_RQ0 RQ# TN0# TL+_TN00 <> T RR0 R % /W 00 TL+_TP00 <> T#[..], INV# +/- 00 mils TP#,TN# +/- mils TL+_RQ0 RQ# TP0# P PU_T_TRIP0 R % /W 00 Mount on Rev:0. TL+_RQ0 RQ# T * TL+_PURT0 R % /W 00 RQ# T#[..], INV# +/- 00 mils TP#,TN# +/- mils TL+_0 <> TL+_RQ0[..0] # TL+_0 TL+_R00 R 0 % /W 00 T#[..], INV# +/- 00 mils TP#,TN# +/- mils TL+_0 # L TL+_0 TL+_0 # # M TL+_0 TL+_0 # # TL+_00 TL+_00 # 0# TL+_0 TL+_0 0# # TL+_0 ource ynchronous R : TL+_0 # # J TL+_0 losed to PU ddress#[..], RQ#[..0], T#[..0] TL+_0 # # M TL+_0 TL+_0 # # J TL+_0 _NMI 00p 0V % 00 Transmission Line Type Total Trace Length Normal Impedance pacing (mils) TL+_0 # # L TL+_0 TL+_0 # # N TL+_0 TL+_PURT0 00p 0V % 00 trip-line.0 ~. inch +/-0% & TL+_0 # # M TL+_0 TL+_0 # # TL+_0 _MI0 0 00p 0V % 00 TL+_0 # # N TL+_00 ignals Name ignals Matching trobes associated trobe Matching TL+_00 # 0# K TL+_0 _0M0 00p 0V % 00 TL+_0 0# # with the group # J _INN0 00p 0V % 00 INV# TL+_INV0 <> #[..], RQ#[..0] +/- 00 mils T0# +/- mils K TN# TL+_TN0 <> _INTR 00p 0V % 00 <> TL+_T0 L T# TP# TL+_TP0 <> #[.. +/- 00 mils T# +/- mils Y TL+_0 # Topology : IRR#, RR#, TRMTRIP# TL+_0 <> TL+_0 N # # T TL+_0 # VP L L L R Rtt Transmission Line TL+_0 <> TL+_NR0 L U NR# # PU R eceiver V TL+_0 # 0." - " 0" -.0" 0" -.0" +/-% +/-% Micro-strip R TL+_0 # L Rtt TL+_0 <> TL+_R00 N R R0# # L R L 0." - " 0" -.0" 0" -.0" +/-% +/-% trip-line R TL+_0 _TPLK0 00p 0V % 00 # TL+_00 0# TL+_0 _PULP0 <> TL+_R0 L U 00p 0V % 00 R# # TL+_0 <> TL+_RY0 V RY# # Topology : PROOT#.V TL+_0 PU_PLP0 <> TL+_Y0 M U 00p 0V % 00 Y# # V TL+_0 # Rs : 0 +/-% Y TL+_0 _INIT0 0 00p 0V % 00 # TL+_0 <> TL+_IT0 K IT# # R :.K +/-% TL+_0 <> TL+_ITM0 K Y ITM# # VP R PU R : 0 +/-% R PU_IRR0_O <,,,,> VP T TL+_INV0 <> Rtt R L. % /W 00 INV# W IRR# TN# TL+_TN0 <> R0. Modify L L L L Rtt Transmission Line <,> _INIT0 W INIT# TP# TL+_TP0 <> L L L 0." - " 0" -.0" 0" -.0" 0." - " +/-% Micro-strip <> TL+_LOK0 J LOK# Rs TL+_0 # 0." - " 0" -.0" 0" -.0" 0." - " +/-% trip-line TL+_0 # TL+_00 <> TL+_R0[..0] TL+_R00 0# 0 TL+_0 TL+_R0 R0# # K TL+_0 TL+_R0 R# # L TL+_0 R# # Topology : PWROO TL+_0 # TL+_0 <0,,,0,,,,,,,,,,,,,0,,,,,,> VM <> TL+_TRY0 M TRY# # VP L L Rtt Transmission Line TL+_0 # PU TL+_0 # TL+_0 <,,,,> VP 0." - " 0" -.0" 0 +/-% Micro-strip 0 # Rtt TL+_0 # L L 0." - " 0" -.0" 0 +/-% trip-line TL+_00 0# TL+_0 <> TL+_PURT0 RT# # TL+_0 R0 # TL+_0 R R # Topology : PLP# 0K % /W 00 0K % /W 00 <,,,,> VP 0 INV# TL+_INV0 <> L L Transmission Line 0 % /W 00 TN# TL+_TN0 <> PU N <> PU_PWROO PWROO TP# TL+_TP0 <> 0." - " 0." -." Micro-strip L L 0." - " 0." -." trip-line RR0 <> _0M0 RR0 0M# PM00 RR0_ <> Q RR# PM0# <> _INN0 PM0 TRN NPN MMT MT OT- IRIL INN# PM# PM0 PM# PM0 PM# Topology : LINT, LINT0, 0M#, INN#, LP#, MI#, TPLK# <> _INTR LINT0 <> _NMI 0 % /W 00 LINT L Transmission Line <> _MI0 R MI# R# ITP_RT0 PU <> _TPLK0 TPLK# 0." - " Micro-strip <> _PULP0 LP# L 0." - " trip-line <> PU_PLP0 PLP# >0mil K % /W 00 <> TL+_PRI0 J R0 PRI# TLR0 VP <,,,,> TLR <> TL+_PWR0 PWR# TLR R0 TLR K % /W 00 <> TRM 0.u V 0% 00 XR(NU) TRM Topology : INIT# driven I.V <> TRM TRM Rs : 0 +/-% PU_T_TRIP0 TRMTRIP# RV0 <,,,,> VP W R :.K +/-% R0 % /W 00 PROOT# RV RV PM_PI0 <0> R RV PU R : 0 +/-% <> PU_LK R K % /W 00(NU) LK0 RV R L <> PU_LK0 LK RV L L + L L L Transmission Line Place within " IMVP POWR TTU INITOR L L T ITP_LK0 0." - " 0" -.0" 0." -.0" Micro-strip Place " within PU T ITP_LK Rs R K % /W 00(NU) TT 0." - " 0" -.0" 0." -.0" trip-line R K % /W 00(NU) R 0 % /W 00 TK TT <,,,,> VP R0. % /W 00(NU) TI R. % /W 00 TO TM P R. % /W 00 PN TRT# OMP0 Topology : PU RT# P R0. % /W 00 R0. % /W 00(NU) OMP 0 R. % /W 00 PN PRY# OMP L R. % /W 00(NU) 0 R. % /W 00 PRQ# OMP PU L L + L L Rs Rtt M Less VP.0" -.0".0" max 0." max. +/-%. +/-% than KT PU PZ0--0 MT PIN OXONN 0." Rtt "anias Only" L L ITP Rs R0. % /W 00 R 0 % /W 00 ddress roup0 ddress roup ontrol ignal Legacy PU Thermal ost LK ITP00 Port ata roup0 ata roup ata roup ata roup anias processor 0 anias processor or later TLR = / VP Max Length : 0." TT K No tuff TT K No tuff R0. Modify I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number Rev PU ( anias ) / 0., 0, P 00 ate: heet of

9 <0,,,> VOR_PU <,,,,> VP U- R V0 V00 R V V0 0 R V0 VP0 V V0 T V VP V V0 T V VP V V0 0 T V VP + V V0 0 T V VP V V0 T V VP V V0 U V VP V V0 0 U V VP V V0 U V VP V0 V0 U V VP V V V V0 VP0 V V K V V VP V V L V V VP V V L V V VP V V 0 M V V VP V V M W V VP V V N W V VP V V N W V VP V V P 0 W V VP V0 V0 P W V VP V V J R Y V0 VP0 V V J R Y V VP V V K T Y V VP V V U T Y V VP V V V U V VP V V V V V V W V V V W P V VQ0 V V Y W 0 V VQ V0 V0 Y V V V V0 V V V V V V V V 0 V V V V V V V V V V V V.VM <> V V0 V V V V V0 V0 N 0 0 V V V V V0 V V V 0 V 0 0 V V V V V V V V 0 V V V V V V 0 Place each V V V V V V pair(0.ux, V V0 V0 V V V 0ux) per pin. V0 V V 0 V V V V V V V V V V V V 0 V V V V V V V V V V V0 V0 VR_VI0 <0> V VI0 V V VR_VI <0> V0 VI V V VR_VI <0> V VI V V VR_VI <0> V VI V V VR_VI <0> V VI V V VR_VI <0> V VI V V V V V V V V 0 V V V J V V0 V0 J V R0 V V J V0 Vsense. % /W 00(NU) V V J V V V J 0 V V K KT PU PZ0--0 MT PIN OXONN V V K V V K V V "anias Only" K V V K 0 V V L V0 V0 L V V L V V L V V M V V M V V M V V M V V M V V N V V N V0 V0 N V V N V N V P V P V P R0 V Vsense P. % /W 00(NU) V R V R V T P X0YR P-P =.mm PN T P X0YR P-P =.mm PN T P X0YR P-P =.mm PN T P X0YR P-P =.mm PN NU_T P X0YR P-P =.mm PN.u 0V 0% 00 XR.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO 0.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO 0 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0 0u.V 0% 00 XR TIYO 0 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO.u 0V 0% 00 XR 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO 0u.V 0% 00 XR TIYO 0.u V 0% 00 XR 0.0u V 0% 00 XR 0u 0V ±0% 00 YU MITUII 0.u V 0% 00 XR 0.u V 0% 00 XR 0.0u V 0% 00 XR 0 0.u V 0% 00 XR 0u 0V ±0% 00 YU MITUII 0.u V 0% 00 XR 0.0u V 0% 00 XR 0.u V 0% 00 XR 0u 0V ±0% 00 YU MITUII 0.u V 0% 00 XR 0.u V 0% 00 XR 0.0u V 0% 00 XR 0.u V 0% 00 XR 0u 0V ±0% 00 YU MITUII 0 0.u V 0% 00 XR 00u V ±0% mo =.mm MT V 0V0M00 K (K-P) U- KT PU PZ0--0 MT PIN OXONN "anias Only" One round One Via I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number Rev PU ( anias ) / 0., 0, P 00 ate: heet of

10 VOR_PU <,,,,,> IN V R00 <,> VR_POK R 0 % /W 00 VOR_N LK_N <,> VOR_N <> <> <,,,0,,,,,,,,,,,,,0,,,,,,> R0. Modify <> VOR_N <> <> <> <> <> <> VRON VRPLP PM_PI0 VR_VI0 VR_VI VR_VI VR_VI VR_VI VR_VI VOR_N NU_ 0.U 0V 0% MT00 XR VM 00K % /W 00 R R.K % /W 00 R <,,,,,,,,,0,,,>.KO % /W M MT00 VOR_N R 0 % /W 00 R0 0 % /W 00 00p 0V 0% 00 XR 00KO % /W M MT00 R R 0 % /W 00 R 0 % /W 00.K % /W 00 R 0.0u V 0% 00 XR R 0 % /W 00 R 0 % /W 00 R 0 % /W 00 R 0 % /W 00 R 0 % /W 00.K % /W 00 R VOR_N NU_ 0.U 0V 0% MT00 XR U 0V 0% MT00 XR 0u V 0 XR 0R0K-TM MIT(NU) R R NU_0 % /W 00 VM 0 % /W 00 0u V 0 XR 0R0K-TM MIT 0u V 0 XR 0R0K-TM MIT 0 0u V 0 XR 0R0K-TM MIT U V OUT V T N N RN N# VI0 VI VI VI VI VI POO + OMP OT 0u V 0 XR 0R0K-TM MIT VOR_N P LNR-I ILV-T TOP PIN INTRIL 0.0u 0V ±0% MT00 VOR_N NU_00p 0V 0% M00 XR 0.µ 0% V 00 XR VT IN U OOT VP L OT VP N 0 N N N N N VN RV TV V 0 u V 0% 0 XR 0 VOR_N IO TKY -0 0V NMKO N U_U_0 N U_U_ N U_U_ N U_U_ N U_U_ N U_U_ P N NU_0 % /W 00 R VOR_N.K 0.% /0W MT00 R u 0V 0% 00 XR.u V ±0% MT00 XR JM PNONI 0p 0V % MT00 XR 00p 0V 0% 00 XR Q M-T-N IRR0Z 0V TO- PIN IR >0mil 0.u 0V 0% 00 XR R. % /W MT00 VOR_N R K % /W 00 R0 K % /W MT00 R 00K % /W 00 >0mil Q >0mil TRN M-T-N IRLR 0V TO- PIN IR Q TRN M-T-N IRLR 0V TO- PIN IR oost Voltage.V eeper leep Voltage 0.V IO TKY M0 0V O- (M) O L 0.u 0 PM0T-RM00 ±0% TK 000p 0V 0% 00 XR VOR_PU or anias eleren PU P N IO ZNR MMZ.V O- IO VOR_PU <,,,> OP etting.iocset=.v/(.k+.k+k)=0u.isen=0u/(/)/0.=.u.isen*rsence=iocp*rds_on (Lowside) Iocp=(Isen*Rsence)/Rds_on (Lowside) R0 K % /W 00 Q R 0K % /W 00 R lose TR M-T-N N00 0V OT- ILIONIX Q VP_P <> TR M-T-N N00 0V OT- ILIONIX R VI VI VOR_N 0 % /W 00 IMVP IV Load line slope : -mv/ Vdroop : *mv/=mv Idroop : mv/.0k=.u.u/0./0. =.u Rds(on) *Io = Isen * Rsen (m/)*=.u*rsen R =.K I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number Rev Vcore 0., 0, P 00 ate: heet of 0

11 TRML NOR Thermal Power onsumption: Icc: Max 0u Icc stdby: Max 0u ddress:00 0X <,> MLK_PMU <,> MT_PMU 0mil U LNR-I MT OP PIN MT LK T 0 0 R K % /W 00 V <,,,,,0,,,,,0,,,,,,> TRM <> <> OT_OWN0 LRT# + 00p 0V 0% 00 XR R TY# - TRM <> R00 <> TRM0_ K % /W 00 0 % /W 00 (NU) R <,,,,,0,,,,,0,,,,,,> V 00 % /W 00 0.u V 0-0% 00 YV T T 0mil TT TT V N N N N N /0 modify U change to T T T T=00P OUL PL LO POIL TO T MX Thermal Power onsumption: Icc: Max 0u Icc stdby: Max 0u ddress:00 0X RT ischarge ircuit IO TKY 0V 0.0 OT-.0*.mm NMKO RT_V <,,0> <,,0,,,,,> PMUV VIN VOUT MO_LR <,,0> MO-P.u 0V 0-0% MT00 YV U I -TU LO.V MT N MO-P.u 0V 0-0% MT00 YV 0.u V 0-0% 00 YV N0 ON PIN 0-0- NTRY mil R 00 % /W 00 0mil 0mil 0mil 0.u V 0-0% 00 YV 0u 0V 0-0% MT00 YV R0. Modify R0. Modify MT-TU : Vin : Vout : N <,,0,,,,,> PMUV MO-P.u 0V 0-0% MT00 YV 0 U I -TU LO.V MT VIN VOUT N MO-P.u 0V 0-0% MT00 YV 0.u V 0-0% 00 YV N W- PIN k-r IO TKY 0V 0.0 OT-.0*.mm NMKO R0. Modify 0mil R 00 % /W 00 0mil 0mil RT_V <,,0> 0mil 0 0.u V 0-0% 00 YV 0 0u 0V 0-0% MT00 YV MO_LR <,,0> I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number R ev Thermal / VR_PWR 0. 0,, 00 ate: heet of

12 VM L 00MZ 00O % 00 M T KIN OR >0mil 0.0u V 0% 00 XR VM_LK 0.0u V 0% 00 XR 0.0u V 0% 00 XR OT lock LK lock LK lock PI lock LK lock lock Latout uideline LOK PU_LK[..0] M_LK[..0] ITP_LK[..0] LK_I LK_M LK_P LK_IPI LK_IOPI LK_WPI LK_MINIPI LK_PI LK_PMU0PI LK_PI LK_IO LK_I LK_TV LK_I LK_M LNT " ~ "." ~.0 " MX :."." ~.0 "."~.0".0"~.0"." ~." <,,,,,,,,,,> TR / P / 0 mils ( mil space between & 0) / 0 mils / 0 mils / 0 mils / 0 mils / 0 mils NOT.VM. ifferentials pairs with the same length (within 0 mil).pu & N trace mismatch within 0 mil Length mismatch within 00 mils Length same as LK lock Length mismatch within 00mils.Making PI length with minimum various. Length Require LK-.". Length mismatch +/-.0". Length mismatch +/- 00 mils 0u 0V +0-0% 0 YV L 00MZ 00O % 00 M T KIN OR u 0V +0-0% 00 YV 0.u V 0% 00 XR <0,> <,0,,> <,0,,> LK_N lock Package Length anais Processor Package Length mils Montara-M M Package Length mils PU ocket quivalent Length mils 0.0u V 0% 00 XR 0.0u V 0% 00 XR VM_LK I_MT I_MLK 0p 0V ±0.p 00 NPO R.K % /W 00 R % /W 00 N _U_ N _U_ 0p 0V ±0.p 00 NPO N _U_ LK_MO 0 PU P PI R X M.M.M.M X M.M.M.M M.M.M.M M.M.M.M M.M.M.M M 0.00M.00M.M M.M.M.M U VPI VPI V V VV VPU VR V. N N N N N N N N T LK RTT VTT_PWR/P IR Mhz_0 Mhz_ X X R0/ R/0 MZ/ _MZ/L_ V_0 V_ V_ PI_0/ PI_/ PI_ MO/PILK0 PILK PILK PILK PILK PILK PILK PULKT0 PULK0 PULKT PULK PITP0 PUTP0 Under 00mil lock Layout :. lose to lock generator. Trace as short as possible and use mil. Place crystal within 00 mils of LK enerator 0 PULKT_ITP/PI_TOP PULK_ITP/PU_TOP I I0 OP PIN I Y XTL.0MZ P X000 R R % /W 00 R % /W 00 R % /W 00 R % /W 00 R % /W 00 R % /W 00 R % /W 00 R % /W 00 R % /W 00 R0 % /W 00 R % /W 00 R0 % /W 00 R % /W 00 R % /W 00 R % /W 00 R % /W 00 R % /W 00 R % /W 00 R % /W 00 R0 % /W 00 PITP0 <> PUTP0 <> N _R_ Under 00mil Under 00mil Under 00mil R. % /W 00 R. % /W 00 R. % /W 00 R. % /W 00 LKM_ <> LKM_UI <> LKM_ <> LKM_ <> LKM_IO LKM_N <> LKM_ <> LKM_ <> LKM_IO LKM_ <> LKM_PI <> LKM_K <> LKM_W <> LKM_ <> LKM_MINI <> PU_LK <> PU_LK0 <> LKN <> LKN0 <> N hielding mil space 0 mil space LK+ mil space mil space LK- mil space 0 mil space N hielding mil space ( mil width for differential signals and N shiekding) LKM_ p 0V +/-0.P 00(NU) LKM_UI p 0V +/-0.P 00(NU) LKM_ p 0V +/-0.P 00 (NU) LKM_ p 0V +/-0.P 00 (NU) LKM_IO p 0V % 00 NPO MURT LKM_N p 0V +/-0.P 00 (NU) LKM_ p 0V +/-0.P 00 (NU) LKM_ p 0V +/-0.P 00 (NU) LKM_ p 0V +/-0.P 00 (NU) LKM_PI p 0V +/-0.P 00 (NU) LKM_K 0 p 0V +/-0.P 00 (NU) LKM_W p 0V +/-0.P 00 (NU) LKM_ p 0V +/-0.P 00 (NU) LKM_MINI p 0V +/-0.P 00 (NU) PU_LK p 0V +/-0.P 00 (NU) PU_LK0 0 p 0V +/-0.P 00 (NU) LKN p 0V +/-0.P 00 (NU) LKN0 p 0V +/-0.P 00 (NU) VM <,0,,0,,,,,,,,,,,,,0,,,,,,> VM N hielding IPLKI, IPLKO N hielding 0 mil space 0 mil space mil space mil space mil space LK_MO R 0K % /W 00 R 0K % /W 00(NU) R 0K % /W 00(NU) R 0K % /W 00(NU) R 0K % /W 00(NU) R 0K % /W 00(NU) <> IPLKO T VM R 00Mz 00O 00 0K-0T0(NU) L U 0mil R.K % /W 00(NU) LKIN V 0K % /W 00(NU) MR R0 ON# R V LKOUT R I P00-0 O PIN PULOR(NU).K % /W 00(NU) 0 R 0K % /W 00 R 0K % /W 00 R 0K % /W 00 R 0K % /W 00 R0 0K % /W 00 <,0,,0,,,,,,,,,,,,,0,,,,,,> VM 0.u V 0% 00 YV VM R % /W 00(NU) IPLKI <> IPLKI p 0V +/-0.P 00 (NU) I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number Rev lock enerator ( ypress YZ ) 0., 0, P 00 ate: heet of

13 0 INPUT _OUT _IN RLK0 0 i L: " WLKOU L:." L:L+L-L+." 0P L=LM+LM 0P L: " VI VT IMM IMM R LOK UR RLK0# VM_LK RLK RLK# RLK RLK# RLK RLK# RLK RLK# RLK RLK# _open 0 i L: " R 0 % /W 00(NU) R 0 % /W 00 <0,> LK_N UIN <,0,,> I_MT <,0,,> I_MLK R VM_LK 0 % /W 00(NU) R0 0 % /W 00 U V R0/RT0 V R/R0 V V R/RT V R/R P# R/RT R/R 0 UIN R/RT R/R L R/RT R/R N N R0/RT N R/R 0 N N L_R# OUT I W OP PIN YPR RT0 RP RP 0 % 00* /W PR 0.mm R0 RT RP RP 0 % 00* /W PR 0.mm R RT RP RP 0 % 00* /W PR 0.mm R RT RP RP 0 % 00* /W PR 0.mm R RT RP RP 0 % 00* /W PR 0.mm R RT RP0 RP 0 % 00* /W PR 0.mm R R 00K % /W 00 VM_LK R 0 % /W 00 M_LK_R0 <0> M_LK_R00 <0> M_LK_R <0> M_LK_R0 <0> M_LK_R <0> M_LK_R0 <0> M_LK_R <0> M_LK_R0 <0> M_LK_R <0> M_LK_R0 <0> M_LK_R <0> M_LK_R0 <0> LKI <> R lock uffer _open R UIN <> LKO 0 % /W 00 0p 0V ±0.p 00 NPO(NU) <,,,,,,,,,,>.VM 0 % /W 00(NU) R 0p 0V ±0.p 00 NPO(NU) 0p 0V ±0.p 00 NPO(NU) 0p 0V ±0.p 00 NPO(NU) 0p 0V ±0.p 00 NPO(NU) 0p 0V ±0.p 00 NPO(NU) 0p 0V ±0.p 00 NPO(NU) 0p 0V ±0.p 00 NPO(NU) 0 0p 0V ±0.p 00 NPO(NU) 0p 0V ±0.p 00 NPO(NU) 0p 0V ±0.p 00 NPO(NU) 0p 0V ±0.p 00 NPO(NU) 0p 0V ±0.p 00 NPO(NU) p 0V % 00 ROM 0.u V 0% 00 YV 0.0u 0V +0-0% MT00 YV L 0K-0T0 ULL WILL + 0.u V 0-0% 00 YV 0.u V 0-0% 00 YV 0.u V 0-0% 00 YV T0u 0V ±0% >0 mil VM_LK 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number R ev lock uffer ,, 00 ate: heet of

14 0 <,,,,> VP <> TL+_0[..] <> TL+_RQ0[..0] <> TL+_0[..0] N N N N N N N N0 R T U P <> TL+_T00 <> TL+_T0 <> TL+_0 <> TL+_NR0 <> TL+_PRI0 <> TL+_R00 <> TL+_Y0 <> TL+_R0 <> TL+_RY0 <> TL+_IT0 <> TL+_ITM0 <> TL+_LOK0 <> TL+_TRY0 <> TL+_RQ0[..0] <> TL+_R0[..0] <> TL+_INV00 <> TL+_INV0 <> TL+_INV0 <> TL+_INV0 <> TL+_PURT0 <> LKN <> LKN0 TL+_0 TL+_0 0 TL+_0 0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_RQ00 TL+_RQ0 0 TL+_RQ0 0 TL+_RQ0 TL+_RQ0 TL+_R00 TL+_R0 TL+_R0 J K M M T0 T NR PRI RQ0 Y R RY IT ITM LOK TRY RQ0 RQ RQ RQ RQ R0 R R I0 I I I PURT LK+ LK- VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT J K J J J J K K TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_0 TL+_00 TL+_0 TL+_0 TL+_0 <,,,,> VP Place these parts near N. as close as possible. Tu.V 0% MT POP NYO 0 MO-P 0u 0V ±0% MT00 XR MIT MO-P 0u 0V ±0% MT00 XR MIT 0 MO-P 0u 0V ±0% MT00 XR MIT MO-P 0u 0V ±0% MT00 XR MIT 0 MO-P 0u 0V ±0% MT00 XR MIT 0 MO-P 0u 0V ±0% MT00 XR MIT u 0V +0-0% 00 YV 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR TLVR_N VR0 VR TP0 TN0 TP TN TL+_TP00 <> TL+_TN00 <> TL+_TP0 <> TL+_TN0 <> TLVR_N R. % /W 00 OMPVR K J VR0 VR VR VR TLVR ROMP 0MPVR TP TN TP TN N/P0 N/P N/P N/P TL+_TP0 <> TL+_TN0 <> TL+_TP0 <> TL+_TN0 <> T T T T R0. Modify T T T N/RP N/P0 N/P PWR TL+_PWR0 <> U VT <,,,,> VP <,,,,> VP TLVR_N R0. % /W 00 R 00 % /W u V 0% 00 XR TLVR_N R. % /W 00 R 00 % /W u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR <,,,,> VP R 00 % /W 00 OMPVR R. % /W u V 0% 00 XR Place these parts near N. as close as possible. nd place each capacitor per pin. I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number R ev PN00 ost ,, 00 ate: heet of

15 0.V_IMM <,,,,,,,,,,>.VM U <> M_[..0] M_0 M_0 M_[..0] <0,> M_ M00 M00 J M_ M_ M0 M0 M_ M_ M0 M0 M_ M_ M0 M0 M_ M_ M0 M0 M_ M_ M0 M0 M_ M_ M0 M0 M_ M_ M0 M0 V K M_ M_ M0 M0 W K M_ M_0 M0 M0 V M M_0 M_ M0 M0 T M M_ M_ M M U K M_ M_ M M T K M_ M_ M M T0 M_[..0] <0,> L M_ M M M_0 M_ M 0 T T M_ M_ M T T M_ M V M_R_R0 M_ M R P M_R_R0 <> W N M R0 M_0 M M_W_R0 M R0 <> R M_ M0 W R M_W_R0 <> U M_ M V M_ M N T W M_ M N T M_ M N M_ M N Y T T0 M_ M N M_ M N W0 T T M_ M N Y T M_0 M N R T M_ M0 N R T M_ M N N T R M_ M N P T M_ M N T P M_ M N R T0 M_ M N P T T M_ M N M0 R T M_ M N N T T M_ M P These packs and resistor M_0 M N N0 T N T M_ M0 N N M,Please close to IMM M_ M N P0 T N M_ M R 00 R 0 % /W 00 M_0_R0 <0,> M_ M 0 T T 0 R 0 % /W 00 M_ M R 0 M R0 <0,> T R 0 % /W 00 M R0 <0,> M_ M P T 0 R0 0 % /W 00 M R0 <0,> M_ M P P M_ M P M_Q0 M_ M Q0 M0 M_Q M_0 M Q L R M_Q M_ M0 Q U L0 M_Q M_ M Q T M_Q M_ M Q T R0 M_Q M_ M Q T T M_Q M_ M Q N0 P M_Q M_ M Q R T M_Q[..0] <> M_ M Q N M_QM[..0] <> M_ M T M_QM0 M_ M QM0 N M_QM M_0 M QM L P M_QM M_ M0 QM V R M_QM M_ M QM P M_QM M_ M QM N P M_QM M QM P M_QM QM P0 M_QM <0> M_K0_R0 T K0 QM T <0> M_K_R0 M K <0> M_K_R0 R K QMM0 QM0 <> <0> M_K_R0 L K QMM QM <> QM0 QMM0 <> K MVR QM QMM <> K MVR_N MVR MVR QMM0 QMM0 <> W MVR QMM R MVR QM0 QMM <> J MVR0 QM VT VMM N VMM P VMM R VMM T VMM U VMM V VMM W VMM Y VMM VMM VMM VMM N VMM N VMM N VMM VMM 0 VMM VMM VMM VMM VMM K VMM K VMM P VMM P VMM MLKI MLKO R % /W 00 0 LKI <> LKO <> LKO as short as possible. LKI = LKx + ". R0 0 % /0W 00 >0MIL.V_IMM u 0V 0-0% 0 YV MO-P.u 0V 0-0% MT00 YV MO-P.u 0V 0-0% MT00 YV 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR M_R_R0 p 0V % 00 NPO MURT M R0 0 p 0V % 00 NPO MURT,,,,,,,,,>.VM R 0 % /0W 00 R 0 % /0W 00 > 0 mil MVR_N 0 0 p 0V +/-0.P 00 (NU) M_W_R0 M_0 M_ M_ M_ M_ M_ M_ M_ 0 p 0V % 00 NPO MURT p 0V % 00 NPO MURT p 0V % 00 NPO MURT p 0V % 00 NPO MURT p 0V % 00 NPO MURT p 0V % 00 NPO MURT p 0V % 00 NPO MURT p 0V % 00 NPO MURT p 0V % 00 NPO MURT MO-P 0u 0V ±0% MT00 XR MIT u 0V +0/-0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 000p 0V 0% 00 XR 000p 0V 0% 00 XR 000p 0V 0% 00 XR M_ M_ M_0 M_ M_ M_ M_0 M_ p 0V % 00 NPO MURT p 0V % 00 NPO MURT p 0V % 00 NPO MURT p 0V % 00 NPO MURT 0 p 0V % 00 NPO MURT p 0V % 00 NPO MURT p 0V % 00 NPO MURT p 0V % 00 NPO MURT I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number R ev PN00 Video ,, 00 ate: heet of

16 0 P_L0 RP N_LP0 P_L N_LP <,,,>.VM P_L N_LP P_L N_LP % 00X /W PR 0 MO-P.u 0V 0-0% MT00 YV P_L RP N_LP 0.0u V 0% 00 XR P_L N_LP <,,,>.VM P_L N_LP 0.0u V 0% 00 XR P_L N_LP % 00X /W PR 0 0.0u V 0% 00 XR P_L RP N_LP P_L N_LP P_L0 N_LP0 <> P_L[..0] P_L N_LP U % 00X /W PR N_LP0 T N_LP 00/P/P P P_L RP N_LP 0/P0/P0 P P_L N_LP N_LP 0/PLK+ T P_L N_LP N_LP 0/P0/P0 R P_L N_LP N_LP 0/P0/P0 T % 00X /W PR N_LP 0/P0/P0 N N_LP 0/P0/P0 T P_L RP N_LP R 0 % /W 00 0/P0/P0 M P_L N_LP 0/PT P P_L N_LP N_LP 0/P R P_L N_LP N_LP 0/P0/P0 M % 00X /W PR N_LP0 /P/P0 L N_LP /P00/P00 N P_L0 RP0 N_LP0 N_LP /P/P00 L P_L N_LP N_LP0 /P/P00 P P_L N_LP N_LP /P0/P00 J P_L N_LP N_LP /P/P00 J % 00X /W PR N_LP /P/P00 J R % /W 00 /P/P00 <> P_ K N_LP /P0 R0 % /W 00 0/P/P00 <> P_LK N_LP /P0LK+ K N_LP /P/P00 /P/P00 /VP0 J /VP0 /VP0 /VP0 /VP0 0/VP0 /VPT N_LP N R (NU)0 % /W 00 0/P0/P0 <> VIO_PT L N_LP /T K /P/P00 K /VP VP VP VP VP VP VP VVL VVL VX W VX Y VX V VM_X R 0 % /W MT00 R 0 % /W MT00 N/R N/R N/R V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V N/VIN N/VOUT V VPR UPT+ UPT- NT+ NT- UPM NM VLVR VLOMPP UT TTIN RT PWROK TIN P R N0 R R P M P M N P M T R N P P P N T M0 M N P N P0 L M N M P T T T0 VL_0 VL_ VL_ VL_ VL_ VL_ VL_ VL_ VLR_N R TIN0_N.VM VM R0. Modify VI_IN <> VI_OUT <> <,,,,,,,,,,> T T T T T0 T T T VL_0 <> VL_PR <> VL_UPT <> VL_UPT0 <> VL_NT <> VL_NT0 <> VL_UPM <> VL_NM <> VL_[..0] <> 0 % /W MT00 R0.K % /W 00.VM VLR_N > 0 mil UT0_N <>.VM <,,,,,,,,,,> PIRT0_N <,> PWROK_N <> K % /W 00 R K % /W 00 R 0 0.u V 0% 00 XR 0.u V 0% 00 XR 0 V V_LK V V_LK V V_LK V VM_X > 0 mil 000P V +0-0% 00 YV > 0 mil > 0 mil > 0 mil 000P V +0-0% 00 YV P V +0-0% 00 YV 0.u V 0-0% 00 YV 0.u V 0-0% 00 YV 0.u V 0-0% 00 YV MO-P.u 0V 0-0% MT00 YV 0.0u V 0% 00 XR 0.0u V 0% 00 XR u 0V +0-0% 00 YV 0.u V 0-0% 00 YV 0.0u V 0% 00 XR L L LMP0 LMP0 L0 LMP0 u 0V +0-0% 00 YV u 0V +0-0% 00 YV L L LMP0 LMP0 VM VM VM VM R0. Modify R0. Modify R % /W 00 <> P_ L R (NU)0 % /W 00 <> VIO_PLK L K R % /W 00 <> P_V K M N R % /W 00 <> P_LK_N <,,,>.VM R.K % /W 00 N R 0 % /W 00(NU) <> NV Rev: 0. Modify. <> NV by VI recommanded <> NKL N_LP T N_LP R N_LP R 0 % /W 00 P_VR P_VR N <> LKM_N <,,,>.VM R 0. % /W 00 R 0. % /W 00 <> P_UY0 L <>.V T T W RM/P0 IRY/LK TRY VL/P0V TOP/PLK- PR/PV R W/P0LK- RQ/LK NT/T RR/P I/PIP IL PXT T0/NV T/NV T/NLT T/VP0 T/VP0 T0/P0/P0 T0/P0/P0 T/P/P000 T/P0T 0/VPV /VP /VP00 /VP /VP0 /VP0 VPLK+ /VPLK- PVR0 PVR LK POMPN POMPP PUY VU TLK N N N N N N N N N N N N N N N N N N N N "NPLL "NPLL "NPLL "N "N "N NK NK NMK NK VK VMK VK VK "R " " "VYN "YN "RT "INT "XIN "ITIN/PL "PT "PLK "IPLKO "IPLKI "TV00/VP000/P00* "TV0/VP00/P0* "TV0/VP00/P0* "TV0/VP00/P0* "TV0/VP00/P0* "TV0/VP00/P0* "TV0/VP00/P0* "TV0/VP00/P0* "TV0/VP00/P0 "TV0/VP00/P0 "TV0/VP00/P0* "TV/VP0/P "TVV/VP0V/PV "TV/VP0/P "TV/VP0/P "VTLK/VP0LK/PLK "TVLKR/VP0T/PLK "PT "PLK "PO0/P "POUT/P "V "V "VPLL "VPLL "VPLL M M L R R R U U V U N V T T N N W W Y Y Y Y Y V W W Y V V V V W T P P P N ITIN TV0 TV TV TV TV TV TV TV TV TV TV0 TV TV_V TV_ TV_ TV_LK TV_POUT PT PLK V_ V_ V_PLL V_PLL V_PLL V V V V R % /W 00 R.K % /W 00 IPLKO_N TV[..0] <> TV_V <> TV_ <> TV_ <> TV_LK <> TV_POUT <> PT <> PLK <> IPLKI IPLKO PI_INT0 <,> LKM_UI <> TV0 TV TV TV R <> LU <> RN <> VYN <> YN <> R0 % /W 00 VT <> VLK <> IPLKO <> IPLKI <> R0 0 % /W 00 p 0V +/-0.P 00 (NU) R 0K % /W 00 R 0K % /W 00 R 0K % /W 00 R 0K % /W 00 VM V_LK > 0 mil V_ V_ > 0 mil V_ V_ > 0 mil V_PLL V_PLL 000P V +0-0% 00 YV > 0 mil V_PLL V_PLL 0 000P V +0-0% 00 YV 000P V +0-0% 00 YV 0 000P V +0-0% 00 YV u V 0-0% 00 YV 0 0.u V 0-0% 00 YV 000P V +0-0% 00 YV u 0V +0-0% 00 YV L LMP0 L u 0V +0-0% 00 YV 0.u V 0-0% 00 YV 0.u V 0-0% 00 YV L LMP0 LMP0 u 0V +0-0% 00 YV L L u 0V +0-0% 00 YV L LMP0 LMP0 u 0V +0-0% 00 YV VM VM LMP0 R0. Modify.VM.VM R0. Modify VT R M0 M M M N N R R R R R R R R0 R R T T N N P T P R L M M > 0 mil V_PLL 0.u V 0-0% 00 YV L LMP0.VM <,,,>.VM V_PLL V_ V_LK R 0K % /W 00(NU) R 0K % /W 00 R 0K % /W 00 R 0K % /W 00 R0 0K % /W 00 V_PLL u 0V +0-0% 00 YV 000P V +0-0% 00 YV Rev: 0. Modify. by VI recommanded R.0K % /W 00 R.0K % /W u V 0% 00 XR u 0V +0/-0% 00 YV 0.u V 0% 00 XR <> P_VR.V 0.u V 0% 00 XR TV0 TV TV TV W R K % /W 00 R K % /W 00 R K % /W 00 R0 K % /W 00 W -0T() PIN.mm OPL.VM R.K % /W 00 TIN0_N R.K % /W 00(NU) TV R.K % /W 00(NU) TV R.K % /W 00(NU) TV R.K % /W 00(NU) TV R.K % /W 00(NU) TV R.K % /W 00 X power up strapping setting: TV[:0] => Panel type selection TV => P-port multiplexed on P interface selection 0: Two -bit VI interface : One -bit panel interface TV => edicated VI port configuration 0: TM : TV ncoder TV => edicated VI port selection 0: apture : VI TV/VP0 => xternal P function enable 0: xternal : Internal TV/VP0 => PI signal test output enable 0: isable : nable <,,,,,,,,,,> <,0,,0,,,,,,,,,,,,,0,,,,,,> TV TV0 TV N_RP_ RP.K % 00X /W PR P (PN00 + VT).VM VM.VM VM I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- ize ocument Number R ev PN00 R / ,, 00 ate: heet of

17 0 0 ize ocument Number R ev ate: heet of PN00 R / 0. P (PN00 + VT) I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00-, 0, 00 U VT M00 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 J M J M M M J M J M M M N M P M P0 M0 N0 M N M R M R0 M M M M M W M W M0 M 0 M M M M 0 M M M M J M0 L0 M M M L M N M M M M M P M L M L M M M0 N M K M L M M M T M L M L M N M L M M M0 L M M M T M N K0 K K J K K K J Q0 Q Q N Q Y Q Q T Q R Q P QM0 QM QM N QM Y QM QM R QM P QM N MLKO 0 T0 T R P M00 M0 0 M0 0 M0 0 M0 M0 Y0 M0 W M0 R M0 P M0 N M0 0 J M P M M M N R L N W N Q

18 0 <,,,>.VM U R0. Modify V V V V V 0 V V V V V V V V M V M V M V M V M V M0 V M V M V M V M V M V M V M V M V U V U V T V T V R V R V P V P V N V N V V V V V V V V V Y V Y V W V W V V V V V <,,,>.VM K K L L M P P P U U Y Y Y J J J J K0 K K0 M M M M M M M M M N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N + N R N R N R N R N R N R0 N R N R N T N T N T N T N T N T0 N T N T N U N U N U N U N U N U0 N U N U N V N V N V N V N V N V0 N V N V N W N W N W N W N W N W0 N W N W N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N Y Y Y Y Y Y0 Y Y T 00u 0V ±0% MT TPLV0MR N u 0V 0-0% 0 YV u 0V 0-0% 0 YV MO-P.u 0V 0-0% MT00 YV 0 u 0V +0-0% 00 YV 0 u 0V +0-0% 00 YV 0.u V 0% 00 XR 0.u V 0% 00 XR 0 0.u V 0% 00 XR 0.u V 0% 00 XR 0.0u V 0% 00 XR 0 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 0.0u V 0% 00 XR 000p 0V 0% 00 XR 000p 0V 0% 00 XR 000p 0V 0% 00 XR 000p 0V 0% 00 XR VT I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number R ev PN00 Power ,, 00 ate: heet of

19 Note : * ll R ignals have 0 mils space from other roups' signals or non-r sigmals These packs and resistor,please close to IMM <0,> M R[..0] M_[..0] <> M R0 M_0 RP M R M_ RP 0 % 00* /W PR 0.mm M R M_ M R M_ M R M_ RP M R M_ RP 0 % 00* /W PR 0.mm M R M_ M R M_ M R M_ RP M R M_ RP 0 % 00* /W PR 0.mm M R0 M_0 M R M_ M R M_ RP M R M_ RP 0 % 00* /W PR 0.mm M R M_ M R M_ M R M_ RP M R M_ RP 0 % 00* /W PR 0.mm M R M_ M R M_ M R0 M_0 RP M R M_ RP 0 % 00* /W PR 0.mm M R M_ M R M_ M R M_ RP M R M_ RP 0 % 00* /W PR 0.mm M R M_ M R M_ M R M_ RP M R M_ RP 0 % 00* /W PR 0.mm M R0 M_0 M R M_ M R M_ RP M R M_ RP 0 % 00* /W PR 0.mm M R M_ M R M_ M R M_ RP M R M_ RP 0 % 00* /W PR 0.mm M R M_ M R M_ M R0 M_0 RP M R M_ RP 0 % 00* /W PR 0.mm M R M_ M R M_ M R M_ RP M R M_ RP 0 % 00* /W PR 0.mm M R M_ M R M_ M R M_ RP M R M_ RP 0 % 00* /W PR 0.mm M R0 M_0 M R M_ M R M_ RP M R M_ RP 0 % 00* /W PR 0.mm M R M_ M R M_ M R M_ RP M R M_ RP 0 % 00* /W PR 0.mm M R M_ M R M_ M R0 M_0 RP0 M R M_ RP 0 % 00* /W PR 0.mm M R M_ M R M_ N ignals M_[..0] M_M[..0] M_Q[..0] L L R 0.~." L L Max:0." ROUP ROUP ROUP NOT M_[..0] M_M0 M_Q0 M_[..] M_M M_Q M_[..] M_M M_Q M_[..] M_[..] M_M M_M M_Q M_Q M_[..0] M_M M_Q M_[..] M_[..] M_M M_M M_Q M_Q N ignals M_K[..0] M_[0..00] N ignals M_LK[.00] M_LK[..0] N L L L L L Rt Vtt * roup & roup & roup Mismatch must be within mils (Total Length) L 0. ~." Max:.0" L 0. " ~ " L O-IMM 0 O-IMM X L 0. " ~ " L O-IMM 0 L Max:.0" Max:.0" L O-IMM O-IMM 0 O-IMM L Rt NOT * vias NOT Vtt NOT * Minimum Pair to Pair pacing 0 mils * IMM 's clock mismatch within mils * ll lock+ & - Mismatch within 0 mils * Trace Width mils, pacing mils, vias * /L - L/ < = " * vias * The same roup must be routed in the same layer * M_Q[..0] mil trace, mil space M_[..0],M_M[..0] mil trace, 0 mil space * M_Q & M_LK mismatch within 0." N L * Minimum Isolation pacing to non-r ignals : 0 mils * M_ & M_K = M_LK +- 0." L Rt O-IMM Vtt <> M R0 <> M_R_R0 <> M_W_R0 R 0 % /W 00 R 0 % /W 00 R 0 % /W 00 M R0 <0,> M_R_R0 <0,> M_W_R0 <0,> ignals M_[..0,,0] M_[0..00] M_W0 M_0 M_R0 L L 0. ~ " Max :.0" L L Max :.0" Max :.0" NOT * L + L = M_LK[..00] +- " * L + L = M_LK[..0] +- " * Trace Width mils, pacing 0 mils, vias * Minimum Isolation pacing to non-r ignals : 0 mils N L O-IMM X L Rt Vtt NOT <0,> M_QM_R[..0] M_QM[..0] <> M_QM_R0 R 0 % /W 00 M_QM0 M_QM_R R 0 % /W 00 M_QM M_QM_R R0 0 % /W 00 M_QM M_QM_R R0 0 % /W 00 M_QM M_QM_R R 0 % /W 00 M_QM M_QM_R R 0 % /W 00 M_QM M_QM_R R 0 % /W 00 M_QM M_QM_R R 0 % /W 00 M_QM ignals M_[,,,] M_[,,,] L L 0. ~." Max :.0" * M_[,,,] = M_LK[..00] +- 0." * M_[,,,] = M_LK[..0] +- 0." * Trace Width mils, pacing 0 mils, vias * Minimum Isolation pacing to non-r ignals : 0 mils <0,> M_Q_R[..0] M_Q_R0 R 0 % /W 00 M_Q_R R 0 % /W 00 M_Q_R R00 0 % /W 00 M_Q_R R0 0 % /W 00 M_Q_R R 0 % /W 00 M_Q_R R 0 % /W 00 M_Q_R R 0 % /W 00 M_Q_R R 0 % /W 00 M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q[..0] <> I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number R ev R RI TRMINTION 0. 0,, 00 ate: heet of

20 M[:0] QM[:0] Q[:0] M[:0] R# # INL ROUP T INL TRO INL M roup 0 M[:0],QM0 Q0 M roup M roup M roup M roup M roup M roup M roup M(& ontrol) (hip elect) K locks INL ROUP WIT:P TR LNT TR LNT MTIN M roup[:0] : ata:ata "<L<" <00mil mismatch : ata:trobe : ata:other M(& ontrol) : M:M : M:Other (hip elect): : K W# #[:0] #[:] K[:0] K[:] VT locks Temination R IMM R IMM Network "<L<" 0 L<0." L<0." L<0." "<L<" 0 i L<0." L<0." L<0." "<L<" 0 i L<." L M[:],QM M[:],QM M[:],QM M[:],QM M[:0],QM M[:],QM M[:],QM : :Other : K:K : K:Other (vg~") "<L<" "<L<" "<Lcke<0" Lcke<" Q Q Q Q Q Q Q M[:0],#,R#,W# #[:0] K[:0] WLKOUT,RLK[:0]/RLK#[:0],_OUT/_OUT# : LK:LK# : LK#:Other L~" L~" L~" L<." within group. < inch mismatch between group. 0mil Length Mismatch ±mils ±mils ±mils ±mils ±mils ±mils ±mils ±mils NOT L=L WLKOUT L=L RLK/# L=L _OUT/# L=L+L- vg(l)+." <,> M_[..0] M_[..0] R <,,,>.V <,> M_Q_R[..0] <,,,> M_QM_R[..0] <,,,>.V.V IMM_VR M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_0 M_ M R0 M_R_R0 M_W_R0 M_QM_R0 M_QM_R M_QM_R M_QM_R M_QM_R M_QM_R M_QM_R M_QM_R.K % /W 00(NU) VM M_Q_R0 M_Q_R M_Q_R M_Q_R M_Q_R M_Q_R M_Q_R M_Q_R R <,,,>.V <,,,>.V 000p 0V 0% 00 XR 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV <,> lose to IMM0 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV <,,,> <,,,> <,> One 0.u capacitors per power pin. Place each capacitors close to pin. 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0 % /W 00(NU) 0.u V 0% 00 YV 0.u V 0% 00 YV <> M_LK_R <> M_LK_R0 <> M_LK_R0 <> M_LK_R <> M_LK_R <> M_LK_R0 <> M_K0_R0 <> M_K_R0 <,> M R0 <,> M_R_R0 <,> M_W_R0 <,> M_0_R0 <,> M R0 I_MLK I_MT Tu 0V 0% + R R 0mil 0.u V 0% 00 YV T T T T T T T T R0. Modify T 0u V ±0% PL0M() N + T 0K % /W 00(NU) % /W 00(NU) p 0V 0% 00 XR 0 N 0 0/P (U) 0 (U) 0 K0 K0# K# K K K# K0 K # R# W# 0# # 0 L RT(U) M0 M M M M M M M M Q0 Q Q Q Q Q Q Q Q V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V VI VP VR VR N <,> O IMM 0 000p 0V 0% 00 XR M R[..0] Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V R N NORM P u V 0% 00 YV U U U U N mil 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0.u V 0% 00 YV M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R 0 0.u V 0% 00 YV <,,,>.V lose to IMM 0 0.u V 0% 00 YV 0.u V 0% 00 YV R 0 % /W 00 R 0 % /W 00 0.u V 0% 00 YV <,> <,,,>.V <,> M_Q_R[..0] IMM_VR <,,,> <,,,> <,,,> One 0.u capacitors per power pin. Place each capacitors close to pin. 0 0.u V 0% 00 YV T T T T 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0 % /W 00(NU) 0mil <> M_LK_R0 <> M_LK_R00 <> M_LK_R0 <> M_LK_R <> M_LK_R <> M_LK_R0 <> M_K_R0 <> M_K_R0 <,> M R0 <,> M_R_R0 <,> M_W_R0 <,> M R0 <,> M R0 M_QM_R[..0] <,,,> R0. Modify.V I_MLK I_MT u 0V +0-0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV.V IMM_VR R0. Modify 0.u V 0% 00 YV R Tu 0V 0% + R 0.u V 0% 00 YV T 0u V ±0% PL0M() N + R M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_0 M_ T T0 T T T T T T M R0 M_R_R0 M_W_R0 VP T0 M_QM_R0 M_QM_R M_QM_R M_QM_R M_QM_R M_QM_R M_QM_R M_QM_R.K % /W 00(NU) M_Q_R0 M_Q_R M_Q_R M_Q_R M_Q_R M_Q_R M_Q_R M_Q_R R % /W 00(NU) K % /W 00(NU) VM 000p 0V 0% 00 XR 0 <,> M R[..0] M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R <,0,,,,,,,,,,,,,,,0,,,,,,> N 0 0/P (U) 0 (U) 0 K0 K0# K# K K K# K0 K # R# W# 0# # 0 L RT(U) M0 M M M M M M M M Q0 Q Q Q Q Q Q Q Q V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V VI VP VR VR N Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V R N RV P 0--0 O IMM P (PN00 + VT) VM I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- U U U U N VM ize ocument Number R ev R RM O-IMM 0. 0,, 00 ate: heet of T T T0 T

21 ontrol ignal Topology & roup Routing uidelines M_0_R0 M R0 M R0 M R0 M_K0_R0 M_K_R0.VM M_K_R0 ohm % M_K_R0 N L L Min=0." Max=.0" Max=.0" O-IMM P ommand ignal Topology & roup Routing uidelines M R[..0] M R[..0] M_R_R0 M_R_R0 M R0 M R0 M_W_R0 M_W_R0 M_0_R0 M_0_R0 0 ohm % ohm % M R0 M R0 N L L L L Min=.0" Max=." Max=0." Max=0." Max=.0" O-IMM0 P O-IMM P Note : onnect to the M-M M[..0] pins onnect to O-IMM with a 0 ohm +/-% resistor.vm <,0> M R[..0] M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R M R M R M R M R M R M R M R0 M R M R M R R_.VM <> RP RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm RP0 RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm <> R_.VM 0 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV Layout note:place one capacitors close to every pullup resistors terminated to +v.. 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0 0.u V 0% 00 YV M_0 M_ M_ M_ RP RP % 00X /W PR 0.mm ata ignal Topology N M_[..0] M_[..0] M_Q[..0] ohm % L Min=.0" Max=." & roup Routing uidelines L Max=0." M R[..0] M R[..0] M_Q_R[..0] O-IMM0 P L Max=." O-IMM P L Max=0." ohm % <,0> M_[..0] <,0> M_[..0].VM <,0> <> <> <> <> <> <> M_R_R0 QM0 QM QMM0 QMM QMM0 QMM M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_0 M_ M_ RP RP % 00X /W PR 0.mm RP0 RP % 00X /W PR 0.mm RP RP % 00X /W PR 0.mm R % /W 00 R % /W 00 R % /W 00 R % /W 00 R % /W 00 R % /W 00 R0 % /W 00 <> Layout note:place one capacitors close to every pullup resistors terminated to +v.. 0mil R_.VM Pure R layout and routing uideline: INL ROUP M_roup[..0] WIT: P : (ata/ata) TR LNT " < L < " <,0> M_QM_R[..0] <,0> M_W_R0 M_QM_R0 M_QM_R M_QM_R M_QM_R M_QM_R M_QM_R M_QM_R M_QM_R R % /W 00 R % /W 00 R % /W 00 R0 % /W 00 R % /W 00 R % /W 00 R0 % /W 00 R % /W 00 R % /W 00 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0 0.u V 0% 00 YV 0.u V 0% 00 YV : (ata/trobe) <,0> M R0 R % /W 00 : (ata/other) <,0> <,0> M_0_R0 M R0 R % /W 00 R0 % /W 00 M(& ontrol) : (M/M) : (M/Other) " < L < " <,0> <,0> M R0 M R0 R % /W 00 R % /W 00 (hip electl) locks : (/) : (/Other) : (K/Other) : (lock/other) " < L < " K : (K/K) L~ " L~ " : (lock/lock#) L~ " L~ " L~0" L~ " <,0> M_Q_R[..0] M_Q_R0 M_Q_R M_Q_R M_Q_R M_Q_R M_Q_R M_Q_R M_Q_R R % /W 00 R % /W 00 R % /W 00 R0 % /W 00 R0 % /W 00 R % /W 00 R % /W 00 R % /W 00 I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number R ev R PULL UP 0. 0,, 00 ate: heet of

22 0 P_LK P_L[..0] <> LVV 0p 0V ±0.p 00 NPO(NU) <,,,> VR near to chip R 0K % /W 00 0.u V 0% 00 YV 0.u V 0% 00 YV 0.u V 0% 00 YV LVN R 0p 0V ±0.p 00 NPO(NU) R 0K % /W 00 P_LK_N.VM VR 0.u V 0% 00 YV 0 P_L0 P_L P_L P_L P_L P_L P_L P_L P_L P_L P_L0 P_L P_L P_L P_L P_L P_L P_L P_L P_L P_L0 P_L P_L P_L 00 0.u V 0% 00 YV V N <> <> <> <> <> >0MIL 0.u V 0% 00 YV 0 P_ P_LK P_LK_N P_ P_V 0.u V 0-0% 00 YV 0.u V 0% 00 YV R 0.u V 0% 00 YV 0 PLLN N LVN V LVV LKINP LKINM YN VYN VR N N N N PLLN PLLN PLLN N N N N V V V U LVN LVN LVN LVN LVV LVV LVV PR RV RV N 0 N N PIO- PIO- PIO- PIO- RV 0 RV IL ILK L/IT IV PLLV 0 PLLV I VT LV TQP 00PIN VI 0 TT TT R_ P UL MN LKP LKM LKP LKM MOL P M P M P M P M P M P M P M 0P 0M 0 V P_PR RV RV R 0 % /W 00 R (NU)0 % /W 00 INVN R (NU)0 % /W 00 R (NU)0 % /W 00 P_NPV R (NU)0 % /W 00 R 0 % /W 00 R 0 % /W 00 R 0 % /W 00 R 0 % /W 00 R 0 % /W 00 P_IL P_L TT R 0 % /W 00 T P_R_ P_P P_UL P_MN T LV_TXLK_LP <> LV_TXLK_LN <> LV_TXLK_UP T0 LV_TXLK_UN T P M T T0 LV_TXOUT_UP T LV_TXOUT_UN T LV_TXOUT_UP T LV_TXOUT_UN T LV_TXOUT_U0P T LV_TXOUT_U0N T P M IV PLLV V P_MOL T T LV_TXOUT_LP <> LV_TXOUT_LN <> LV_TXOUT_LP <> LV_TXOUT_LN <> LV_TXOUT_L0P <> LV_TXOUT_L0N <> 0.u V 0% 00 YV u 0V +0-0% 00 YV R0 (NU)0 % /W 00 R (NU)0 % /W 00 VM RV R (NU)0 % /W 00 RV R (NU)0 % /W 00 R.K % /W 00 R.K % /W 00 L_PLK <> L_PT <>.VM_LV.VM L 0K-0T0 W L 0K-0T0 ULL WILL V L 0K-0T0 W LVV L 0K-0T0 ULL WILL IV L 0K-0T0 ULL WILL PLLV L 0K-0T0 ULL WILL PLLN L 0K-0T0 W N L 0K-0T0 ULL WILL LVN PLLV 0.u V 0% 00 YV 0.u V 0% 00 YV VM.VM_LV 0.u V 0-0% 00 YV.VM_LV PLLN 0.u V 0-0% 00 YV Place? close to NVT PWR 0 % /W 00 PWR 0 % /W 00 R0. Modify for MI <,0,,,0,,,,,,,,,,,,0,,,,,,> VM.VM_LV <,,,>.VM R R R0 R R R R R <,,,>.VM R R K % /W 00.K % /W 00 R P_NPV <> NV Q0 M-T-N NN. 0V OT- IRIL NV <>.K % /W 00.K % /W 00.K % /W 00.K % /W 00.K % /W 00.K % /W 00(NU).K % /W 00 (NU).K % /W 00 <,,,>.VM W 0 % /W 00 VM L M0K-0T0 P_PR P_UL P_IL P_MN P_P P_L P_R_ P_MOL.K % /W 00 (NU).K % /W 00.K % /W 00.K % /W 00 (NU).K % /W 00 (NU).K % /W 00 (NU).K % /W 00(NU).K % /W 00 (NU) R0 R R0 R R R R R <,,,>.VM <> <> LN NKL R0.K % /W 00 <> NV M-T-N NN. 0V OT- IRIL Q IO TKY U 0V 0.0 OT- PIN NMKO <,> LI0 N P IO TKY -0 O- NMKO R.K % /W 00 0.u 0V 0% 0 XR INVN <> TRPPIN P_PR P_UL P_IL P_MN P_P P_L P_R_ P_MOL PULL-UP PULL-OWN Pull high (efault) Reserve Two hannel ingle hannel (efault) I active (efault) I Inactive Interrupt active (efault) Interrupt Inactive Normal Mode (efault) Power own Mode ingle-nd LK (efault) ifferential-nd LK ailling dge Rising dge (efault) bit Mode (efault) bit Mode <,,,,,,,,,,>.VM <,0,,,0,,,,,,,,,,,,0,,,,,,> VM.VM VM I International omputer, Inc. L.,NO,.,WNW nd R. LINKOU IN, TIPI, TIWN,RO (-)00- P (PN00 + VT) ize ocument Number R ev VT & LV onnector ,, 00 ate: heet of