The first printing of this book was produced with a few minor printing errors. We apologize for any confusion this might cause you.

Transcription

1 The first printing of this book was produced with a few minor printing errors. We apologize for any confusion this might cause you. Page Correction Sentence added before Figure 2.3: "R 6 out is typically big for the current-mode case. The termination on the receiver side is not shown in the figure." Endnote reference [6] added after the sentence, "Figure 2.4(a) is a commonly used singleended current-mode driver, also called a high-common mode (HCM) driver [6]." 7 6. H. Hatamkhani and C.-K. K. Yang, "Power analysis for high-speed I/O transmitters," in Proceedings of International Symposium on VLSI Circuits, Jun. 7-9, 2004, pp Synchronous bullet corrected to "Every component gets the same clock frequency and 24 known phase." 26 Paragraph after Equation 2.4, e yz changed to e γz 35 2 nd line of Section , removed the word "term" Endnote 6 added: H. Hatamkhani and C.-K. K. Yang, "Power analysis for high-speed I/O 40 transmitters," in Proceedings of International Symposium on VLSI Circuits, Jun. 7-9, 2004, pp th bullet corrected to "Controller package layer count: or build up package for 47 DQ traces" 56 2 nd paragraph of Section 3.4.2, Ω corrected to 50 60Ω 59 st paragraph, "(shown in Figure 3.)" corrected to "(shown in Figure 3.2)" 62 st paragraph, second line, 300 corrected to 30" 63 st paragraph, 8 th line, 00 corrected to 0". 9 th line,.0 corrected to." Equations 4.5c and 4.6 corrected: 69 v v2 A B v2 = = i ABCD i 2 i (4.5c) C D 2 v v3 v3 = (,3) = (,2) (2,3). i ABCD i ABCD ABCD 3 i (4.6) 3 v A B v2 = i i C D 2 70 Table 4.'s bottom right cell corrected to st paragraph of Section 4..3 and in Equation 4.7a, the arrows should be aligned over v. 72 Equations 4.a and 4.b, the arrows should be aligned over v. Alignment of Table 4.4 corrected. Please see corrected version on the Updates tab at Removed closing brace on this page in Equation 4.42b 05 Table 5., first row in Z column, "coch" changed to "csch" jωτ ˆ 7 d jωτdm Equation 5.28 corrected to: e = Mτ e M τ. 33 Paragraph after Equation 5.46, ", 2ns" changed to ".2ns" 56 Table 6., 0e- deleted in the column heading. "e" deleted from all superscripts. Please see corrected version at 65 st line of the page, comma inserted in "RX,Deadband" and "RX,RJ" 76 Equation 7.2 corrected to: y = C0 + C0F + + C F + ε. 20 Paragraph after Equation 8.5, P n changed to P "BER(v REF ) = " added to the beginning of Equation At the top of the page, b n changed to b 0 22 Equation 8.4, "H TXT " changed to "H TXT " Equation 8.9 corrected to: 25 T ( ε ) E ( n ) = E a WH a WH = V V ( H ) W WH 2 ( ) ( ε ) RX RX T RX RX T RX RX T T RX a ε 28 st paragraph, 60 changed to 6" th line, "Figure 9.23" changed to "It"; 7 th line, "This" changed to "Figure 9.23" N N

2 247 7 th line on the page, 30 changed to 3" 250 Paragraph after Equation 9.3, "&infini;" changed to the infinity symbol, 252 st paragraph after Table 9.2 and in Figure 9.29 caption, 70 changed to 7" 260 Equation 0.3b corrected to: n TX = awh TX J ( ζ TX ) ε Ref. 265 Paragraph after Equation 0.9, H Clk changed to H Clk Figure 0.9 caption corrected to "Comparison of JIF (Jitter Impulse Response) with 277 Transient Simulation" 304 Equation 2. updated to: Lnet = L L L M pin pin pin Table 3.7, shading in last column corrected to light gray. Please see corrected version at st paragraph, "&frac2;" changed to "/2" The two equations in the first paragraph corrected to: V( t) = 25mV cos(2π 50 t 90) 7 Jt ( ) = 0.96ps cos(2π 50 t 57) 383 st paragraph of Section 5.2., Ωcm changed to Ω cm in 2 places 400 Additional sentence added to the start of 2nd paragraph: "The chapter first discusses the substrate modeling methodology, including both DC and high-frequency approaches." The word "and" deleted from the following sentence: "The relative size of the ISI 428 cancellation pulse, and to the main pulse, is determined by the equalizer coefficients, which are, in turn, determined by the channel characteristics." Equation 7.a changed to: 429 ( + g / 2),, mr ω s z = ω 2. ( R C ) p = ω R C p = ( R C ) s s D L s s 432 Line before Equation 7.2, "tc.q " changed to "t c,q " (changing period to comma) 2 2 en wee ( n) wen = 2en = 2 eun n ( ) 435 Equation 7.6 corrected to: w st paragraph of Section 7.3.2, "Stojanovi" changed to "Stojanovic" rd line, "SNR" changed to "BER" 0 ' ' e e = w e e = w e e ( ) ( ) i i i i i i Equation 7.6 corrected to: i= m i= m 45 References 22 and 24, "Stojanovi" changed to "Stojanovic" Figures 9.4, 9.5, 9.25, 4.4, 7.4, 7.6, 7.8, 7.7, 7.8, 8.25, and 8.27 were revised. See the revised versions on the Updates tab at

3 Table 4.4 Vice Versa Transform Matrices to Convert Single-Ended Variables to Mixed-Mode Variable and Single-Ended to Mixed-Mode Mixed-Mode to Single-Ended i: single-ended positive index i: differential-mode index v j: single-ended negative index m: differential-mode index n: common-mode index m n i j B - >2 >2 R M v SM m n j: common-mode index m: single-ended positive index n: single-ended negative index i j B >2 ->2 R MMS SM v =M v - i m n i j B >2 ->2 R M i SM m n i j B >2 - >2 R M i MS SM =M i - a,b i j i j m n 22 D T SM M a,b m n 22 D T M MS SM a,b = M T a,b 22

4 Table 6. Target BER vs. Q BER - BER Q BER BER Q BER BER Q BER BER Q BER BER Q BER BER Q BER

5 x y z y x Single Bit Rising Edge Rout = y for transition = z for high state = x for low state Falling Edge Figure 9-4

6 Package POD Single-End Driver Probing Point MB Trace, 0.8 Zo = Figure 9-5

7 Voltage (mv) Final Noise PDF Random Data DBI-DC Coded Final Noise PDF BER Voltage (mv) Time (ps) Time (ps) BER Figure 9-25

8 Table 3.7 Encoding and Decoding for 6-Wire Vector Signaling with Simplified Receiver Design Transmitter Receiver Symbol U V W X Y Z U-V U-W W-U X-Y Y-Z Z-X (U+V+W)-(X+Y+Z) A δ δ δ B δ δ C δ δ D δ δ E δ δ - F δ δ - G δ δ - H δ δ δ - I δ δ δ - J δ δ δ - K δ δ δ L δ - δ δ M δ δ - δ

9 R VRM LVRM R PCB LPCB R PKG LPKG R on-chip V VRM R PCBdecap L PCBdecap RPKGdecap L PKGdecap C decap Rdecap R shunt fb C PCBdecap CPKGdecap Off-Chip PDN On-Chip PDN Current Profile Figure 4-4

10 Analog Comparator 0,,,... _ RX Clock Offset DAC H DFE [n] Analog Digital Feedback Equalizer (a) t s -T t s t s +T t s + 2T Channel Single Bit Response dfe dfe 2 dfe (dfe + dfe )2 /2 (dfe 2 2 +dfe 3 )2 (b) Figure 7-4

11 x(n) Channel P u(n) u(n),e(n) Equalizer w x(n) ˆ x(n ) e(n) w n+ = w μ n w 2 we(e n ) 2 Figure 7-6

12 Voltage (V) Data-Based Tx Equalization No EQ Data Tx EQ Data Samples Edge Samples (a) Time (sec) X 0-9 Edge-Based Tx Equalization Voltage (V) No EQ Edge Tx EQ Data Samples Edge Samples (b) Time (sec) X 0-9 Figure 7-8

13 DSP ADC 0,,,... H DFE [n] Analog Digital (a) y[n] Quantization Noise Decision Slicer d[n] q[n] Offset[n] H DFE [n] (b) Figure 7-7

14 D N [K] X[k-M] X[k-2] X[k-] T M Y[k+] D 2 [K] Combinational Deterministic Decision Logic X[k] T 2 D [K] Binary Data T (a) X[K-M] X[K-2] X[K-M] X[K-2] X[K-] X[K-] comb.logic D N [k] D [k] N: X [K] D N [k] D [k] Thermometer to binary D[k] + F[k] - X[k] (b) (c) Figure 7-8

15 00 pattern Strobe PLL READ data 90 Data 00 pattern DLL READ data CA CLK 90 WRITE data VREF WRITE data Controller PHY DRAM PHY Figure 8-25

16 External Regulator VDDIO (.5V) ODT_VDDIO ODT_VSS VREF Memory System Power I/O Signaling [20%] System Clocking [40%] DRAM Core [40%] Controller DRAM Figure 8-27