Pre Silicon to Post Silicon Overview. Adam Norman Intel Corp. PCCG

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1 Pre Silicon to Post Silicon Overview Adam Norman Intel Corp. PCCG

2 What is Pre-Silicon? It is the design Phase of a platform, which is done before silicon/packages/boards have been fabricated. It can take many years of pre-silicon work to create a CPU. Typically, the design work is done with simulation. Optimization of design Tradeoffs ( power, area, cost, features, risk ) Robustness studies 2

3 What is the relationship between Pre and Post?? Questions to class before we learn more about Pre-Silicon methods What can you simulate? How accurate is the simulations? How many simulations should I run? What do you trust more? Simulation or Measurement? 3

4 Simulation Domains Pre Layout Sims Silicon and/or boards parameterized Post Layout Sims Silicon and/or Boards Extracted Active Transistors Circuits/Devices Feedback Passive Power Deliver Network (PDN) Transmission Lines Physical (PCB, Sockets, Conn.) Vias Discrete components R,L,C 4

5 Active vs Passive Simulation Active, generally has non-linear and/or time varying elements. Transient simulation is usually performed SPICE is most common simulator Passive is generally Linear Time-invariant (LTI) 3D structures usually simulated with Full-wave solvers : Can you name some 3D solvers? Output is Frequency Domain (S-parameters) 2D structures, can use simpler/faster solvers Many output formats, RLGC, tabular W-element, S-param. Combining the Active + Passive elements Transient simulation is needed Commonly used tool is HSPICE 5

6 Pre Silicon Disciplines Circuit (I/O) Design Focus on Active portion (circuits) Transmitter and Receivers Understanding PVT impact on Jitter Signal Integrity Focus on Board + Circuit Power Integrity Focus on PDN + Circuit 6

7 Signal Integrity Terminology Silicon Package Motherboard DRAM1 DRAM2 Victim Ron PKG_L1 DIMM Conn. MB_L1 DIMM_L1 DIMM_L2 Aggressor. Topology Deck 3D structures (or Vertical Structures) Transmission Lines Transmitter Circuit (Tx) Drive Strength (Ron) Receiver Circuit (Rx) IBIS Model DRAM1 Termination/ODT Loads Victim Aggressors Coupling Reference Plane DRAM2 7

8 Post Layout Extraction 8

9 How do you use the Simulations? Class Exercise 9

10 Goal specific methodologies PathFinding Comparative analysis HVM. Class Exercise [ List Variables] Heart of Signal Integrity at Intel Validation Post Layout? Transistor Models 10

11 Variation Sources Manufacturing variation (HVM) Tolerances Design Variable CLASS EXERCISE : LIST 20 parameters Time Varying (temporal) Temperature Voltage Noise 11

12 What do you measure in Simulations? Simulation has the luxury of infinite observability. How does this compare to Post-Silicon Measurements? King of metrics is the eye-diagram. Time Domain metric Many other waveform and Frequency Domain based metrics Setup/Hold timing Ringback Level Non-monotonicities Slewrate 12

13 How do you get an eye diagram? 2 Typical approaches Pattern simulation (aka empirical) Peak Distortion Analysis (aka analytic) 13

14 Eye Diagram CLASS DEMO Strobe/CLK Setup Hold Voltage Margin 14

15 Peak Distortion Finding Worst Case Eye 15

16 Sample Pulse Response EACH DOT SEPERATED EXACTLY BY 1 UI UI = BIT WIDTH precursor cursor postcursors 16

17 Sample Pulse Response ISI+ ISI- precursor cursor postcursors 17

18 LTI property: Superposition In Out Tx symbol Pulse response

19 LTI property: Superposition of symbols In Out Tx symbol Response to pattern

20 LTI property: Superposition of coupled symbols In Out Tx symbol FEXT Pulse response 20

21 LTI property: Superposition of coupled symbols In Out Tx symbol FEXT response 21

22 LTI property: Superposition of coupled symbols Out Tx symbol FEXT response 22

23 LTI property: Superposition of coupled symbols Out Insertion loss response Tx symbol

24 LTI property: Superposition of coupled symbols Out Tx symbol FEXT response Insertion loss response Tx symbol Composite response 24

25 Peak Distortion Analysis Must apply to Linear time-invariant system Superposition applies Interference of symbols on same wire Interference of symbols on different coupled channels 25

26 Worst-case 0 26

27 Worst-case VWC0 = ISI + 27

28 Worst-case 1 28

29 Worst-case VWC1 = cursor + ISI - 29

30 Is peak distortion realistic? CLASS Exercise: 10 Aggressors 10 bit deep of channel memory BER Analysis is Statistical Eye 30

31 Iteration Paths PRE-Silicon Flow Stackup/RLC Connectors/Vias Package/Skt Topology and Signaling Definition Deck Creation Tool: Text Editor Only for new busses ~3x to 4x Repeat IBIS/Linear Transistor SPECS Driver/Receiver (Silicon) Tool: IBIS Center HVM Variable Definition Tool: Spreadsheet Sampling Plan (DOE, MC, FOCUS, GA) Tools: JMP, Excel,.JSL ~3x to 4x Repeat Tied to Silicon Revs Less Frequent Loop DOE has reduced need Very Frequent Loop Run Simulations Tools: Hspice,Lynx S-Param Syn. Waveform Analysis PDA, BER Tools: SigSim, Simba Data Analysis DOE/RSM Error Analysis Tools: JMP 31 Matlab

32 Analysis Techniques Time Domain Analysis and Frequency Domain Analysis Design of Experiments (DOE)/Neural Net Modeling Build a model of the metric Worst Case analysis Monte Carlo Sweeps 32

33 DOE/NN Flow 33

This is the goal for Pre-Silicon and Post-Silicon predictions.

34 This is what we want to predict! 1,000,000 Units Notes: 1. Customer determines the fail. Not the spec. 2. With perfect prediction we would have 0 Factory Rejects and XX Customer Fails. - How do get there? This is the goal for Pre-Silicon and Post-Silicon predictions. Intel has been evolving tools/methods towards this predictive goal. Such that, we can optimize cost and performance while still meeting Reliability ( DPM or customer Fails) and Yield ( Factory Rejects) 34targets.

35 Customer Fails How do we get there? Starting from a perfect prediction. Build 1million systems - predict all variation sources Notes: 1. Infinite number of assumptions are completely known, including customer fail definition. Nothing uncontrolled 2. This could be pre-silicon or Post-Silicon - What happens in reality? This is the goal for Pre-Silicon and Post-Silicon predictions. If we could perfectly predict customer margin, then we could optimize such that we meet reliability targets with no yield loss. 35

36 Customer Fails? Customer Fails Pre-Silicon Predictions Predicting Heavy tails Perfect Prediction Correlation? Notes: Numerous factors for deviation from perfect 1. Pre-Silicon assumptions - Stimulus, # of aggressors - Driver Models, Jitter - Eye Mask 2. Missing variables and noise 3. Imperfect Simulator Goal for the evolution of Pre-Silicon Tools and methods is to Tractably close this gap 36

37 Customer Fails? Customer Fails Post-Silicon Predictions Predicting Light tails Perfect Prediction Correlation? Notes: Numerous factors for deviation from perfect 1. Post-Silicon assumptions - Stimulus - Sampling Scheme 2. Missing variables and noise 3. Uncontrolled variables 4. Measurement error Goal for the evolution of Post-Silicon Tools and methods is to Tractably close this gap 37

38 Customer Fails Correlation? Customer Fails Customer Fails Correlation Paths What matters? PreSilicon Prediction Perfect Prediction ( reality) PostSilicon Prediction Notes: 1. Good engineering is necessary to proper Assess risk. By understanding limitations And assumptions in both predictive domains the best risk decision can be made Although Pre to Post Silicon Correlation is most commonly targeted, Don t forget about the bigger goal. Don t confuse the map with the 38 terrain

39 Customer Fails Customer Fails How did we evolve to this picture? PreSilicon Prediction PreSilicon Evolution Physics:: Lossless Lossy Crosstalk SIPI Methods:: MC DOE PDA BER DPM Post Silicon Evolution PostSilicon Prediction DFx:: Voltage Margin Timing Margin BER Methods:: MC DOE GA BER DPM The evolution of both methods is valuable to study. And, of course, new methods/techniques are always being added. 39

PreSilicon Simulation Evolution Year 2000 2001 2002 2003 2006 2008 2009 Physics [Modeling] Stimulus Physics_A Physics_A Physics_B Physics_B Physics_C Physics_D Physics_E Pattern Suite +WC Pattern

40 PreSilicon Simulation Evolution Year Physics [Modeling] Stimulus Physics_A Physics_A Physics_B Physics_B Physics_C Physics_D Physics_E Pattern Suite +WC Pattern (PDA) +BER + (Tx/Rx Jitter) Sampling MC+Grid +DOE +NN Guard band GB_A GB_B (statistical eye mask) GB_C GB_D GB_E GB_F GB_G Risk/Goal Find WC Find WC Find WC Find WC Find WC +DPM DPM Takeaways: 1. Guardband must always be consistent with the assumptions. - KIT of information. 2. All facets of PreSilicon method evolve 3. Simulator capability and need dictate the physics modeling. 4, Note that methods/techniques are rarely thrown away. Efficiency and 40

41 Summary Pre-Silicon simulations are a valuable part of the design process. Excellent means for understanding and optimizing under HVM variation Are they perfect? No Should you still do validation? Yes 41

Predicting BER to Very Low Probabilities

Predicting BER to Very Low Probabilities IBIS Summit, DAC, Anaheim, CA June 15, 2010 0.25 0.2 0.15 0.1 0.05 0-0.05-0.1 Arpad Muranyi arpad_muranyi@mentor.com Vladimir Dmitriev-Zdorov -0.15-0.2-0.25-0.5-0.4-0.3-0.2-0.1