Model-Order Reduction of High-Speed Interconnects: Challenges and Opportunities

Transcription

1 Model-Order Reduction of High-Speed Interconnects: Challenges and Opportunities Michel Nakhla Carleton University Canada Model Reduction for Complex Dynamical Systems Berlin 2010

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3 EMI Delay Crosstalk Reflection Distortion

4 Interconnect Hierarchy DIE Package BOARD Backplanes and cables

5 Lumped segmentation

6 Lumped segmentation

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8 If you have is a hammer, every problem starts looking like a nail!! (Mark Twain)

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11 Lumped segmentation

12 Is this a good starting point for MOR??

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14 Agenda Interconnect Macromodeling MOR of Interconnect Macromodels

15 Lumped segmentation

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19 High-Speed Interconnect?? d Interconnect length becomes comparable to the Wavelength l v = d f Sharper pulses contain higher frequency harmonics 0.35 f max = t r

20 From Maxwell to the Telegrapher Equations H x xh t t v( x, t). dl i( x, t) H. dl QTEM C. R. Paul, Analysis of Multiconductor Transmission Lines. John Wiley and Sons, 1994 Telegrapher's Equations

21 The Telegrapher's Equations ), ( t ), ( ), ( ), ( t ), ( ), ( t t t x t t t x x x x x x v v i x i i v C G L R

22 Interconnect Delay 50 TL Vs 50 Time-of-Flight delay S. Grivet-Talocia et al., Transientanalysis of lossy transmission lines: an efficient approach based on the method ofcharacteristics, IEEE Transactions on Advanced Packaging, Feb

23 From Telegrapher s Equations to SPICE Mixed Frequency/Time Problem SPICE H-S Interconnect Nonlinear Simulator Telegrapher s Equation x W Hx F(x) b(t) t Time-Domain Equations V( d, s) A sb d (0, s) e V ( d, s) (0, s) I I Freq-Domain Equations

24 From Telegrapher's Equations to Circuit Simulation ), ( t ), ( ), ( ), ( t ), ( ), ( t t t x t t t x x x x x x v v i x i i v C G L R Macromodeling Circuit Simulator ODE s Solver ODE s

25 Macromodeling Uniform Segmentation DELAY???

26 Delay Modeling 50 TL Vs 50 With Delay Extraction 4s Lumped Segmentation 1272s Time-of-Flight delay

27 Why? Without Delay Extraction

28 With Delay Extraction

29 Delay Modeling- MoC i 1 (t) i 2 (t) + v 1 (t) - i 1 (t) NOT Passive Z 0 By Construction w 1 (t) + - Z w 2 (t) i 2 (t) + v 2 (t) - t 2v t w t 1 2 w2 t 2v1 t w1 t w 2

30 Passive Delay Extraction Baker-Campbell-Hausdorff Series (BCH) B X B A s s e e e where 1 k X k X B A X, s, f k k B B A X s s e e e 0 0 d R A G 0 0 d L B C

31 Passive Delay Extraction Lie Product The product k A m m k1 e e sb m k ; where 0 A G 0 B C R d 0 L d 0 (AsB) converges asymptotically to e as m error 1 O m

32 Passive Delay Extraction Modified Lie Product The product m k1 k ; sb A sb 2m m 2m e e e k where 0 A G 0 B C R d 0 L d 0 (AsB) converges asymptotically to e as m error 1 O m 2

33 Passive Delay Extraction sb A sb e e e k 2m m 2m lossless lossy lossless Delay sources RLC Delay sources

34 DEPACT Macromodel A sb e 1 DEPACT cell 1 2 DEPACT cell k m DEPACT cell m k th DEPACT Cell Lossless Lossy Lossless N. Nakhla, A. Dounavis, R. Achar, and M. Nakhla, DEPACT: Delay extraction based passive compact transmission line macromodelling algorithm, IEEE Transactions on Advanced Packaging, Feb

35 DEPACT Macromodel A sb e 1 2 m DEPACT cell 1 DEPACT cell k DEPACT cell m Passivity of this realization is guaranteed by CONSTRUCTION.

36 Realization of the Lossy Sections Are uniform sections good choice? Example: H s G s 2 2 m ( ) ( ) m H 2 ( s ) Gi ( s ) G j ( s ) G ( s )... G ( s ) m k l i j k... l 2m

37 Realization of the Lossy Sections- MRA Based on Pade approximation of the exponential matrix Closed-form Approximation Passivity is guaranteed by construction Realized as cascade of RLC sections A. Dounavis, R. Achar, and M. Nakhla, A general class of passive macromodels for lossy multiconductor transmission lines, IEEE Transactions on Microwave Theory and Techniques, Oct

38 Example : Lossy Coupled TL 5cm, 20cm, 40cm 50 1ns, 50 B1 C1 Open V 1ns, pF C pF B2 50 Input: step response, rise time = ns

39 Example 3: Far End Active Line (Node C1) 40cm

40 Example 3: Far End Victim Line (Node C2) 40cm

41 Example 3: Near End Active Line (Node B1) 40cm

42 Example 3: Near End Victim Line (Node B2) 40cm

43 Performance Comparison Simulations MRA (MNA size) Lumped (MNA size) MNA savings Example % Example % Example3 (5cm) % Example % (20cm) Example 3 (40cm) %

44 Example 4: Several Coupled TL Length=2.5cm Length=2.5cm Length=2.5cm Length=0.4cm Length=0.4cm V1 V4 Input: Trapzoidal pulse, pulse width = 0.8ns rise time = 0.1 ns fall time = 0.1 ns period = 2ns

45 Example 4: CPU Comparison Algorithm Total number of lumped sections CPU time (SPARC Ultra 5-10) (seconds) Conventional Lumped MRA

46 Example : Nonlinear Terminations 5V 30 5V V V1 V3 1.5pF 0.1pF 30 V2 Length=10cm V4 1.5pF R, L, C and G functions of frequency Trapezoidal pulse with rise/fall 0.1ns pulse width 5ns and a period of 10ns

47 Example 5 R and L of interconnects are functions of frequency

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52 Algorithm Total number of lumped sections CPU time (SPARC Ultra 5-10) (seconds) Conventional Lumped MRA 20 49

53 Example 6: Nonlinear Terminations 5V Lossless line Length = 15cm 5V 1pF 1pF Output 1pF pF 1pF 1pF 1pF 1pF 1pF 1pF

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58 Algorithm Total number of lumped sections CPU time (SPARC Ultra 5-10) (seconds) Conventional Lumped MRA

59 Volts Macromodeling- Example IBM Line-4* DEPACT Lumped Segmentation Ruehli, Cangellaris and Huang, Three Test Problems for the Comparison of Lossy Transmission Line Algorithms, Proc. EPEP-2002

60 Macromodeling- CPU Comparison (IBM Line-4*) Frequency-dependent Parameters Method CPU time (sec) SPEED-UP Lumped Segmentation MRA DEPACT

61 DEPACT Macromodel - Example 2 1v tr=0.1ns DEPACT order m=6

62 Volts DEPACT Macromodel - Example 2 DEPACT Lumped Segmentation Time (ns) Active line far-end voltage of subnetwork #2

63 Volts DEPACT Macromodel - Example 2 DEPACT Lumped Segmentation Time (ns) Victim line far-end voltage of subnetwork #2

64 DEPACT Macromodel - Example 2 Lumped Segmentation CPU speed-up DEPACT Speed-Up 23.4 sec 0.75 sec 31

65 Macromodeling RLC coupled sections + distributed delay sources

66 Agenda Interconnect Macromodeling MOR of Interconnect Macromodels

67 MOR for RLC+Delay MOR ODE ODE MOR ODDE ODE e s a s k k Expanded system Passivity k

68 MOR for RLC+Delay ODE ODDE ODDE MOR MOR MOR?? ODE ODE ODDE

69 ODDE ODE Q 1 Q 2 W. Tseng, C. Chen, E. Gad, M. Nakhla, and R. Achar, Passive order reduction for RLC circuits with delay elements, IEEE Trans. Adv. Pkg.,Nov

70 MOR for RLC+Delay ODDE ODDE Passive by Construction Preserve TL causality

71 MOR for RLC+Delay 1024 Resistors 477 Capacitors 596 Inductors 120 lossless TLs Order of the original network: 2390 Order of the Reduced model: 60 CPU SPEEDUP: 17

72 Frequency Response

73 Multi-port MOR N lines No. of ports = 2 x N MOR.

74 Multi-port MOR N lines... N= Number of coupled lines P= number of ports= 2 x N No. of block moments k = 20: N = 4 q = 160 N = 64 q = 2560

75 Interconnects General RLC Circuits??

76 Interconnect PUL Parameters ), ( t ), ( ), ( ), ( t ), ( ), ( t t t x t t t x x x x x x v v i x i i v C G L R G and C are diagonally dominant Matrices L and R : diagonal is the largest element (absolute value)

77 Agenda Interconnect Macromodeling MOR of Interconnect Macromodels MOR for RLC+Delay Partitioning 1. Physical 2. Electrical

78 Agenda Interconnect Macromodeling MOR of Interconnect Macromodels MOR for RLC+Delay Partitioning 1. Physical 2. Electrical

79 Previous Methods Driver Subcircuit Receiver Subcircuit Interconnect Subcircuit References: 1) F.Y.Chang, The generalized method of characteristics for waveform relaxation analysis for lossy coupled transmission lines, IEEE Trans.MTT,vol.37,pp , Dec ) R.Wang and O.Wing, Transient analysis of dispersive VLSI interconnects terminated in nonlinear load, IEEE Trans. CAD, vol.11, no.10,pp , Oct. 1992

80 Transverse Partitioning (Conceptual View)

81 Transverse Partitioning (Conceptual View)

82 Transverse Partitioning (Conceptual View) + - SOURCE SOURCE + - SOURCE SOURCE + - SOURCE SOURCE

83 WR-TP Coupled lines circuit splits into single lines subcircuits Exploits the rapid decrease in coupling effects as the distance between the lines increases Method can be implemented using Parallel Processing N. Nakhla, A. E. Ruehli, M. Nakhla, and R. Achar, Simulation of coupled interconnects using waveform relaxation and transverse partitioning, IEEE Transactions on Advanced Packaging,, Feb

84 WR-TP: Mathematical View Telegrapher s equations can be written as: For the j th line Applying relaxation techniques v i (k+1) j j x (k+1) x (k+1) (k+1) i (k) j R jji j L jj e j x, t t (k+1) (k+1) vj (k) Gˆ ˆ jj v j C jj q j x, t t

85 Single-ended Representation Line 1 Line Line j Line N Line j + - N coupled lines N single line subcircuits Line N + -

86 Distributed Representation Line 1 Line j Line N N coupled lines

87 Distributed Representation Line Line 1 Line j Line j Line N Line N N coupled lines N single line subcircuits

88 WR-TP: Numerical Examples Nine Coupled Line circuit d=1cm R = 50 V C = 1pF N=9 1) A. Ruehli, A.C. Cangellaris and H-M Huang, Three test problems for the comparison of lossy transmission line algorithms, Proceedings EPEP, pp , Oct

89 WR-TP: Example HSPICE WF-TP After 3 iterations Initial Guess Time (sec) x 10-8 Voltage at far end of active line x 10-3 HSPICE WF-TP Initial Guess After 3 iterations Time (sec) x 10-8 Voltage at far end of victim line I. Elfadel, Convergence of Transverse Waveform Relaxation for the Electrical Analysis of Very Wide Transmission Line Buses, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, August 2009

90 Example 2 N 4 CPU Time (Seconds) HSPICE WR-TP Computer: INTEL P4 2GHz CPU N (number of lines)

91 Example hours! in HSPICE CPU Time (Seconds) WF-TP 10 5 Linear Computer: INTEL P4 2GHz CPU N (number of lines)

92 Example 3 Highly Resistive Low Inductive V R = 50 C = 1pF N=24 # lines W Element HSPICE WF-TP Computer: INTEL P4 2GHz CPU sec sec sec sec sec sec

93 Example 3 24 Coupled lines IFFT WF-TP (3 iterations) Time (sec) x 10-8 Voltage at near end of victim line

94 Example 3 24 Coupled lines IFFT WF-TP (3 iterations) W element (HSPICE) Time (sec) x 10-8 Voltage at near end of victim line

95 ... Direct MOR vs. WR-TP+MOR Reduced Models Tightly coupled 2N-ports Reduced model 2-Port Reduced Subcircuit #1 2-Port Reduced Subcircuit #2 2-Port Reduced Subcircuit #N Direct MOR WR-TP+MOR N. Nakhla, M. Nakhla, and R. Achar, Model order reduction of large multiport interconnect structures using waveform relaxation techniques, IEEE International Conference on Computer Aided Design, 2007

96 Model Reduction of subcircuits j th line: Port 1 SOURCE + - Port 2. SOURCE 2-N port circuit N 2-port subcircuits

97 Direct MOR vs. WR-TP+MOR Sparsity Patterns k= no. of preserved block moments Sparsity pattern of MNA Eqs. using Direct MOR Large and dense!!! Dimension: 2kN x 2kN

98 Direct MOR vs. WR-TP+MOR Sparsity Patterns k= no. of preserved block moments Sparsity pattern of reduced MNA Eqs. using PRIMA Large and dense!!! Dimension: 2kN x 2kN Sparsity pattern of reduced MNA Eqs. using WR-TP Sparse Block Diagonal Dimension of each block: 2k x 2k

99 WR-TP + MOR: FD parameters Z( s) R( s) sl ( s) Y( s) G( s) sc( s) Direct MOR 1. Approximation of Z(s), Y(s) by positive real matrices 2. To ensure passivity of the reduced model : Requires passive synthesis of multi-port Z(s), Y(s) [1] WR-TP+MOR 1. Approximation of Z(s), Y(s) by positive real scalar rational function 2. To ensure passivity of the reduced model : Requires passive synthesis of single-port immitance

100 Voltage (volts) Computational Results Example: 8 coupled lines Original Network WR-TP+MOR (1 iteration) Time (sec) x 10-8 Victim line near end (line 4)

101 Voltage (volts) Computational Results Example: 8 coupled lines Original Network WR-TP+MOR (2 iterations) Time (sec) x 10-8 Victim line near end (line 4)

102 Voltage (volts) Computational Results Example: 8 coupled lines Original Network WR-TP+MOR (3 iterations) Time (sec) x 10-8 Victim line near end (line 4)

103 Computational Results Example: 8 coupled lines Model d= 3 cm, t r =0.5ns Size Original network 1810 Direct MOR 320 WR-TP+MOR 40

104 Computational Results d= 15 cm, t r =0.2ns Example: 36 coupled lines (72 ports) Model Size CPU Time (Sec) Speed-up Reduced WR-TP +MOR x

105 Parallel Implementation 8 - core CPU (Intel Xeon E GHz) Speedup # CPUs D. Paul, N. Nakhla, R. Achar, and M. Nakhla, Parallel simulation of massively coupled interconnect networks, IEEE Transactions on Advanced Packaging, Feb. 2010

106 SUMMARY Maxwell s equations to Telegrapher s equations Properties of Interconnects Interconnects Macromodels Uniform Lumped Segmentation Non-uniform Lumped Segmentation Non-uniform Lumped Segmentation MOR RLC +Delay Portioning Physical Electrical