Recent developments for MOR in the electronics industry

Size: px
Start display at page:

Download "Recent developments for MOR in the electronics industry"

Transcription

1 Recent developments for MOR in the electronics industry Wil Schilders Reduced Order Models in Computational Science and Engineering Aachen, January 30-31, 2014

2 Full proposal oc for a new COST action EU-MORNET: European Model Reduction Network Proponent Wil Schilders

3 Applications of Model Reduction Multibody systems Medical and dental modeling Control and power Tsunami risk analysis Automotive Social networ ks PAGE 3

4 What is Model Reduction? Systems and control, Lyapunov, Truncated Balanced Realization Scientific computing, numerical MOR, Krylov methods, linear algebra, tensors Pade-via-Lanczos and PRIMA Passivity preserving Structure preserving Linear and nonlinear problems Parameterized methods Tensor analysis Large-scale Lyapunov systems Balanced realizations Observability and controllability Gramians Port-Hamiltonian systems Hankel singular values Projection methods MOR at operator level Mathematical modeling, behavioral modeling, models via data Karhunen-Loeve expansions Neural networks Vector fitting Behavioral models PAGE 4

5 Why these topics together? Scientific computing, numerical MOR, Krylov methods, linear algebra, tensors Systems and control, Lyapunov, Truncated Balanced Realization Remarkably, they share the same common phenomenology! Mathematical modeling, behavioral modeling, models via data PAGE 5

6 More information Kick-off meeting May/June 2014 Management Committee currently being formed After kick-off, addditional partners can join the network Basis for new European projects EID: European Industrial Doctorate (1 univ, 1 ind) ITN/ETN W. H. A. Schilders, J. M. L. Maubach and S. Lungten PAGE 6

7 MOR in the electronics industry Methods like PVL, PRIMA were developed by people associated with electronics companies The electronics industry has been extremely stimulating for progress in model order reduction, as designers need very fast simulations of extremely large structures PAGE 7

8 Motivation for the work Accurate Simulations require a high level of detail Huge models whose simulations are computationally very expensive! Models inner states may be too detailed Solution: find a smaller yet equivalent model Model Order Reduction But EM effects are becoming more relevant! Scaling reduction Integration Increase Higher Frequency UvA, PAGE 8

9 The impossible made possible.. A complete package layout used for full wave signal integrity analysis 8 metallization layers and 40,000 devices The FD solver used 27 million mesh nodes and 5.3 million tetrahedrons The transient solver model of the full package had 640 million mesh cells and 3.7 billion of unknowns 9

10 Avoiding brute force The behaviour of this MOS transistor can be simulated by solving a system of 3 partial differential equations discrete system for at least unknowns Insight? Even worse: an electronic circuit consists of MOS devices Solution: compact device model (made by physicists/engineers based on many device simulations, ~50 unk) Can we construct such compact models in an automated way? 10

11 Another example Integrated circuits need 3-D structure for wiring 10 years ago 1-2 layers of metal, no influence on circuit performance Present situation: 8-10 layers of metal Delay of signals, parasitic effects due to high frequencies 3-D solution of Maxwell equations leads to millions of extra unknowns Gradual Can we construct a compact model for the interconnect in an automated way? circuit 11

12 Model Order Reduction is about capturing dominant features 12

13 Example: MOR for transmission line (RC) Original Reduced Netlist size (Mb) # ports # internal nodes # resistors # capacitors

14 Many challenges in the electronics industry Extremely large resistor networks are used to describe substrate propagation, power transistors and more Designers want to know the sensitivity of their designs with respect to many (!) parameters The positioning of analog components on a chip is vital for the performance Challenges in linear & nonlinear MOR PAGE 14

15 Outline Low-order models at work in the electronics industry: MOR for purely algebraic systems MOR for nonlinear systems MOR for DAEs Conclusions 15 15

16 Outline Low-order models at work in the electronics industry: MOR for purely algebraic systems MOR for nonlinear systems MOR for DAEs Conclusions 16 16

17 Challenge: Large resistor networks Obtained from extraction programs to model substrate and interconnect Networks are typically extremely large, up to millions of resistors and thousands of inputs/outputs Network typically contains: Resistors Internal nodes ( state variables ) External nodes (connection to outside world, often to diodes) Model Order Reduction needed to drastically reduce number of internal nodes and resistors 17

18 Reduction of resistor networks 18

19 Deleting all internal nodes: not an option 19

20 Simple network 274 external nodes (pads, in red) 5384 internal nodes 8007 resistors/branches Can we reduce this network by deleting internal nodes and resistors, still guaranteeing accurate approximations to the path resistances between external nodes? NOTE: there are strongly connected sets of nodes (independent subsets), so the problem is to reduce each of these strongly connected components individually 20

21 Two-Connected Components can delete all internal nodes here 21

22 Other examples January 2010 PAGE 22

23 Solution: Block Bordered Diagonal form Algorithm was developed to put each of the strongly connected components into BBD form (see figure) Internal nodes can be deleted in the diagonal blocks, keeping only the external nodes and crucial internal nodes The reduced BBD matrix allows extremely fast calculation of path resistances (work of Duff et al) 23

24 Reduction results See also thesis Roxana Ionutiu (2011) 24

25 Outline Low-order models at work in the electronics industry: MOR for purely algebraic systems MOR for nonlinear systems MOR for DAEs Conclusions 25 25

26 Challenge: Fast and accurate simulation of oscillators ( nonlinear MOR) RC Cal SD- ADC Test Pins Xtal CLK DAC MIXER PA + Matching Digital Core Modem and control Tripler LNA + Matching IF Amp VCO + PLL PLL Filter 26

27 Classification of circuits Engineer Mathematician Analysis by Jaijeet Roychowdhury 27

28 Nonlinear modeling of perturbed oscillators 1. PSS of oscillator: d/dt [q(x PSS )]+ j(x PSS )=0, T=T OSC 2. u 1 (t)= d/dt(x PSS )(t) ( right Floquet eigenfunction) 3. v 1 (t) solves a linearized adjoint system ( left Floquet eigenfunction) 4. Perturbed oscillator: d/dt [q(x)]+ j(x)= b(t) has solution x(t)=x PSS (t+ (t))+x n (t), [ (t) phase noise] 5. (t) satisfies a non-linear scalar differential equation d/dt ( )(t) = v 1 (t+ (t)).b(t), (0)=0 28

29 Example- three stage ring oscillator 153kHz ring oscillator Unlocked : i inj = 6 * 10-5 *sin(1.04ω 0 * t) Locked osc: i inj =6 * 10-5 * sin(1.03ω 0 * t) 29

30 MOR: Fast and accurate modeling of VCO pulling VCO pulling due to PA and other blocks/oscillators needs to be analyzed before production Full system simulation is CPU intensive or infeasible Behavioural model order reduction gives fast and accurate insight in pulling/locking and coupling Full mathematical theory of locking/unlocking mechanisms and conditions lacking! 30

31 Outline Low-order models at work in the electronics industry: MOR for purely algebraic systems MOR for nonlinear systems MOR for DAEs Conclusions 31 31

32 General idea of Index-aware Model Order Reduction (IMOR) PAGE 32

33 Differential algebraic systems Why did we develop IMOR? PAGE 33

34 Model of a generator PAGE 34

35 Model of a generator PAGE 35

36 PRIMA reduced order generator model January 2010 PAGE 36

37 Index-aware MOR needed PRIMA may run into problems for higher index systems Besides, we feel that it is always good to mimic the structure and properties of the original problem Mimetic methods are gaining popularity, but have been developed for a long time: Exponentially fitted schemes for singularly perturbed and stiff differential equations Modified ICCG method for iterative solution of linear systems MOR for port-hamiltonian systems As the basis for our IMOR method, we use a method developed in the 1990 s 11 October 2011 PAGE 37

38 März decoupling procedure January 2010 PAGE 38

39 März decoupling procedure January 2010 PAGE 39

40 Modification of decoupling procedure January 2010 PAGE 40

41 Modified index-1 system January 2010 PAGE 41

42 IMOR-1 method descriptor form January 2010 PAGE 42

43 IMOR-1 method reduced order form January 2010 PAGE 43

44 Modified index-2 system January 2010 PAGE 44

45 Modified index-2 system January 2010 PAGE 45

46 IMOR-2 method descriptor form January 2010 PAGE 46

47 IMOR-2 method reduced order form January 2010 PAGE 47

48 Why a new method IIMOR? The IMOR method leads to algebraic systems that are explicit in the algebraic variables This is due to the way the decoupling method is described/constructed Not attractive in practice: if we start with a large resistor network (purely algebraic), IMOR would need the inverse of the system matrix Question: can we develop a projection method that leads to implicit algebraic systems? so that we can use the methods we developed for the reduction of purely algebraic systems January 2010 PAGE 48

49 The Implicit IMOR method PAGE 49

50 Delaying the inversion in the decoupling January 2010 PAGE 50

51 Implicit index-1 decoupled system January 2010 PAGE 51

52 Descriptor form January 2010 PAGE 52

53 Construction of bases for projector January 2010 PAGE 53

54 Numerical results for IIMOR method PAGE 54

55 January 2010 PAGE 55

56 January 2010 PAGE 56

57 January 2010 PAGE 57

58 January 2010 PAGE 58

59 January 2010 PAGE 59

60 January 2010 PAGE 60

61 January 2010 PAGE 61

62 January 2010 PAGE 62

63 January 2010 PAGE 63

64 January 2010 PAGE 64

65 January 2010 PAGE 65

66 January 2010 PAGE 66

67 January 2010 PAGE 67

68 Conclusions PAGE 68

69 Needed (future work): Use the methods we developed for purely algebraic systems also in this IIMOR context (cf paper by Schilders, Marcotte, Shontz in COMPEL, 2012) January 2010 PAGE 69

70 References January 2010 PAGE 70

Model Order Reduction

Model Order Reduction Model Order Reduction Wil Schilders NXP Semiconductors & TU Eindhoven November 26, 2009 Utrecht University Mathematics Staff Colloquium Outline Introduction and motivation Preliminaries Model order reduction

More information

Virtual Prototyping for Power Electronics

Virtual Prototyping for Power Electronics Virtual Prototyping for Power Electronics Cross-Theme Project (Design Tools and Modelling) EPSRC Centre for Power Electronics Dr Xibo Yuan 5 th July 2016 Contents Background Challenges and approaches Accuracy

More information

Contents Part I Introduction The COMSON Project Part II Partial Differential Algebraic Equations PDAE Modeling and Discretization

Contents Part I Introduction The COMSON Project Part II Partial Differential Algebraic Equations PDAE Modeling and Discretization Contents Part I Introduction 1 The COMSON Project... 3 Michael Günther and Uwe Feldmann 1.1 Trends in Microelectronics... 3 1.2 Scope of the COMSON Project... 4 1.3 Methodology... 5 1.3.1 The Demonstrator

More information

EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania

EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania 1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS 2 -> ESD PROTECTION CIRCUITS (INPUT PADS) -> ON-CHIP CLOCK GENERATION & DISTRIBUTION -> OUTPUT PADS -> ON-CHIP NOISE DUE TO PARASITIC INDUCTANCE -> SUPER BUFFER

More information

Introduction to Model Order Reduction

Introduction to Model Order Reduction Introduction to Model Order Reduction Wil Schilders 1,2 1 NXP Semiconductors, Eindhoven, The Netherlands wil.schilders@nxp.com 2 Eindhoven University of Technology, Faculty of Mathematics and Computer

More information

Model Order Reduction for Parameter-Varying Systems

Model Order Reduction for Parameter-Varying Systems Model Order Reduction for Parameter-Varying Systems Xingang Cao Promotors: Wil Schilders Siep Weiland Supervisor: Joseph Maubach Eindhoven University of Technology CASA Day November 1, 216 Xingang Cao

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 17, 2018 I/O Circuits, Inductive Noise, CLK Generation Lecture Outline! Packaging! Variation and Testing! I/O Circuits! Inductive

More information

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr. DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is

More information

Model-Order Reduction of High-Speed Interconnects: Challenges and Opportunities

Model-Order Reduction of High-Speed Interconnects: Challenges and Opportunities Model-Order Reduction of High-Speed Interconnects: Challenges and Opportunities Michel Nakhla Carleton University Canada Model Reduction for Complex Dynamical Systems Berlin 2010 EMI Delay Crosstalk Reflection

More information

SyreNe System Reduction for Nanoscale IC Design

SyreNe System Reduction for Nanoscale IC Design System Reduction for Nanoscale Max Planck Institute for Dynamics of Complex Technical Systeme Computational Methods in Systems and Control Theory Group Magdeburg Technische Universität Chemnitz Fakultät

More information

Model Order Reduction for Electronic Circuits: Mathematical and Physical Approaches

Model Order Reduction for Electronic Circuits: Mathematical and Physical Approaches Proceedings of the 2nd Fields MITACS Industrial Problem-Solving Workshop, 2008 Model Order Reduction for Electronic Circuits: Mathematical and Physical Approaches Problem Presenter: Wil Schilders, NXP

More information

Computing Phase Noise Eigenfunctions Directly from Steady-State Jacobian Matrices

Computing Phase Noise Eigenfunctions Directly from Steady-State Jacobian Matrices Computing Phase Noise Eigenfunctions Directly from Steady-State Jacobian Matrices Alper Demir David Long Jaijeet Roychowdhury Bell Laboratories Murray Hill New Jersey USA Abstract The main effort in oscillator

More information

ECE 451 Macromodeling

ECE 451 Macromodeling ECE 451 Macromodeling Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 451 Jose Schutt Aine 1 Blackbox Macromodeling Nonlinear Network 1 Nonlinear Network

More information

MODEL-order reduction is emerging as an effective

MODEL-order reduction is emerging as an effective IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005 975 Model-Order Reduction by Dominant Subspace Projection: Error Bound, Subspace Computation, and Circuit Applications

More information

EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology

EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology EECS240 Spring 2013 Lecture 2: CMOS Technology and Passive Devices Lingkai Kong EECS Today s Lecture EE240 CMOS Technology Passive devices Motivation Resistors Capacitors (Inductors) Next time: MOS transistor

More information

Parallel VLSI CAD Algorithms. Lecture 1 Introduction Zhuo Feng

Parallel VLSI CAD Algorithms. Lecture 1 Introduction Zhuo Feng Parallel VLSI CAD Algorithms Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 513 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee5900spring2012.html

More information

Preamplifier in 0.5µm CMOS

Preamplifier in 0.5µm CMOS A 2.125 Gbaud 1.6kΩ Transimpedance Preamplifier in 0.5µm CMOS Sunderarajan S. Mohan Thomas H. Lee Center for Integrated Systems Stanford University OUTLINE Motivation Shunt-peaked Amplifier Inductor Modeling

More information

Topic 4. The CMOS Inverter

Topic 4. The CMOS Inverter Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Topic 4-1 Noise in Digital Integrated

More information

Identification of Electrical Circuits for Realization of Sparsity Preserving Reduced Order Models

Identification of Electrical Circuits for Realization of Sparsity Preserving Reduced Order Models Identification of Electrical Circuits for Realization of Sparsity Preserving Reduced Order Models Christof Kaufmann 25th March 2010 Abstract Nowadays very-large scale integrated circuits contain a large

More information

7-9 October 2009, Leuven, Belgium Electro-Thermal Simulation of Multi-channel Power Devices on PCB with SPICE

7-9 October 2009, Leuven, Belgium Electro-Thermal Simulation of Multi-channel Power Devices on PCB with SPICE Electro-Thermal Simulation of Multi-channel Power Devices on PCB with SPICE Torsten Hauck*, Wim Teulings*, Evgenii Rudnyi ** * Freescale Semiconductor Inc. ** CADFEM GmbH Abstract In this paper we will

More information

EE5900 Spring Lecture 5 IC interconnect model order reduction Zhuo Feng

EE5900 Spring Lecture 5 IC interconnect model order reduction Zhuo Feng EE59 Spring Parallel VLSI CAD Algorithms Lecture 5 IC interconnect model order reduction Zhuo Feng 5. Z. Feng MU EE59 In theory we can apply moment matching for any order of approximation But in practice

More information

A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devices

A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devices IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2003 155 A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear

More information

IMPEDANCE and NETWORKS. Transformers. Networks. A method of analysing complex networks. Y-parameters and S-parameters

IMPEDANCE and NETWORKS. Transformers. Networks. A method of analysing complex networks. Y-parameters and S-parameters IMPEDANCE and NETWORKS Transformers Networks A method of analysing complex networks Y-parameters and S-parameters 1 ENGN4545/ENGN6545: Radiofrequency Engineering L#7 Transformers Combining the effects

More information

Basic. Theory. ircuit. Charles A. Desoer. Ernest S. Kuh. and. McGraw-Hill Book Company

Basic. Theory. ircuit. Charles A. Desoer. Ernest S. Kuh. and. McGraw-Hill Book Company Basic C m ш ircuit Theory Charles A. Desoer and Ernest S. Kuh Department of Electrical Engineering and Computer Sciences University of California, Berkeley McGraw-Hill Book Company New York St. Louis San

More information

Model order reduction for multi-terminals systems : with applications to circuit simulation Ionutiu, R.

Model order reduction for multi-terminals systems : with applications to circuit simulation Ionutiu, R. Model order reduction for multi-terminals systems : with applications to circuit simulation Ionutiu, R. DOI: 10.6100/IR716352 Published: 01/01/2011 Document Version Publisher s PDF, also known as Version

More information

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002 CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed

More information

CMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process

CMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process EECS240 Spring 202 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS Technology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 Today s Lecture

More information

CMOS Cross Section. EECS240 Spring Today s Lecture. Dimensions. CMOS Process. Devices. Lecture 2: CMOS Technology and Passive Devices

CMOS Cross Section. EECS240 Spring Today s Lecture. Dimensions. CMOS Process. Devices. Lecture 2: CMOS Technology and Passive Devices EECS240 Spring 2008 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS echnology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 oday s Lecture

More information

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually

More information

Model reduction of nonlinear circuit equations

Model reduction of nonlinear circuit equations Model reduction of nonlinear circuit equations Tatjana Stykel Technische Universität Berlin Joint work with T. Reis and A. Steinbrecher BIRS Workshop, Banff, Canada, October 25-29, 2010 T. Stykel. Model

More information

A comparison of model reduction techniques from structural dynamics, numerical mathematics and systems and control

A comparison of model reduction techniques from structural dynamics, numerical mathematics and systems and control A comparison of model reduction techniques from structural dynamics, numerical mathematics and systems and control B. Besselink a, A. Lutowska b, U. Tabak c, N. van de Wouw a, H. Nijmeijer a, M.E. Hochstenbach

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

More information

Topics to be Covered. capacitance inductance transmission lines

Topics to be Covered. capacitance inductance transmission lines Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of

More information

Comparison of Model Reduction Methods with Applications to Circuit Simulation

Comparison of Model Reduction Methods with Applications to Circuit Simulation Comparison of Model Reduction Methods with Applications to Circuit Simulation Roxana Ionutiu, Sanda Lefteriu, and Athanasios C. Antoulas Department of Electrical and Computer Engineering, Rice University,

More information

Passivity Assessment and Model Order Reduction for Linear Time-Invariant Descriptor Systems in VLSI Circuit Simulation.

Passivity Assessment and Model Order Reduction for Linear Time-Invariant Descriptor Systems in VLSI Circuit Simulation. Abstract of thesis entitled Passivity Assessment and Model Order Reduction for Linear Time-Invariant Descriptor Systems in VLSI Circuit Simulation Submitted by Zheng ZHANG for the degree of Master of Philosophy

More information

Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form

Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form Boyuan Yan, Sheldon X.-D. Tan,PuLiu and Bruce McGaughy Department of Electrical Engineering, University of

More information

An Algorithmic Framework of Large-Scale Circuit Simulation Using Exponential Integrators

An Algorithmic Framework of Large-Scale Circuit Simulation Using Exponential Integrators An Algorithmic Framework of Large-Scale Circuit Simulation Using Exponential Integrators Hao Zhuang 1, Wenjian Yu 2, Ilgweon Kang 1, Xinan Wang 1, and Chung-Kuan Cheng 1 1. University of California, San

More information

Implementing Nonlinear Oscillator Macromodels using Verilog-AMS for Accurate Prediction of Injection Locking Behaviors of Oscillators

Implementing Nonlinear Oscillator Macromodels using Verilog-AMS for Accurate Prediction of Injection Locking Behaviors of Oscillators Implementing Nonlinear Oscillator Macromodels using Verilog-AMS for Accurate Prediction of Injection Locking Behaviors of Oscillators Ben Gu, Kiran K. Gullapalli, Steven Hamm, Brian Mulvaney, MICA Circuit

More information

A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devices

A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devices A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devices Michał Rewieński, Jacob White Department of Electrical Engineering and

More information

Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printed Circuit Boards

Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printed Circuit Boards Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printed Circuit Boards Frank Y. Yuan Viewlogic Systems Group, Inc. 385 Del Norte Road

More information

Charge Pump. Loop Filter. VCO Divider

Charge Pump. Loop Filter. VCO Divider FEATURES PIN CONFIGURATION Low phase noise XO Input from crystal or clock at 10-27MHz. Integrated crystal load capacitor: no external load capacitor required. Output clocks up to 160MHz. Low phase noise

More information

Two-Layer Network Equivalent for Electromagnetic Transients

Two-Layer Network Equivalent for Electromagnetic Transients 1328 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 18, NO. 4, OCTOBER 2003 Two-Layer Network Equivalent for Electromagnetic Transients Mohamed Abdel-Rahman, Member, IEEE, Adam Semlyen, Life Fellow, IEEE, and

More information

COMPARISON OF TWO METHODS TO SOLVE PRESSURES IN SMALL VOLUMES IN REAL-TIME SIMULATION OF A MOBILE DIRECTIONAL CONTROL VALVE

COMPARISON OF TWO METHODS TO SOLVE PRESSURES IN SMALL VOLUMES IN REAL-TIME SIMULATION OF A MOBILE DIRECTIONAL CONTROL VALVE COMPARISON OF TWO METHODS TO SOLVE PRESSURES IN SMALL VOLUMES IN REAL-TIME SIMULATION OF A MOBILE DIRECTIONAL CONTROL VALVE Rafael ÅMAN*, Heikki HANDROOS*, Pasi KORKEALAAKSO** and Asko ROUVINEN** * Laboratory

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded

More information

An Optimum Fitting Algorithm for Generation of Reduced-Order Models

An Optimum Fitting Algorithm for Generation of Reduced-Order Models An Optimum Fitting Algorithm for Generation of Reduced-Order Models M.M. Gourary 1, S.G. Rusakov 1, S.L. Ulyanov 1, M.M. Zharov 1, B.J. Mulvaney 2 1 IPPM, Russian Academy of Sciences, Moscow 1523, e-mail:

More information

MOSIS REPORT. Spring MOSIS Report 1. MOSIS Report 2. MOSIS Report 3

MOSIS REPORT. Spring MOSIS Report 1. MOSIS Report 2. MOSIS Report 3 MOSIS REPORT Spring 2010 MOSIS Report 1 MOSIS Report 2 MOSIS Report 3 MOSIS Report 1 Design of 4-bit counter using J-K flip flop I. Objective The purpose of this project is to design one 4-bit counter

More information

Grasping The Deep Sub-Micron Challenge in POWERFUL Integrated Circuits

Grasping The Deep Sub-Micron Challenge in POWERFUL Integrated Circuits E = B; H = J + D D = ρ ; B = 0 D = ρ ; B = 0 Yehia Massoud ECE Department Rice University Grasping The Deep Sub-Micron Challenge in POWERFUL Integrated Circuits ECE Affiliates 10/8/2003 Background: Integrated

More information

Model Order Reduction using SPICE Simulation Traces. Technical Report

Model Order Reduction using SPICE Simulation Traces. Technical Report Model Order Reduction using SPICE Simulation Traces Paul Winkler, Henda Aridhi, and Sofiène Tahar Department of Electrical and Computer Engineering, Concordia University, Montreal, Canada pauwink@web.de,

More information

ECE 407 Computer Aided Design for Electronic Systems. Simulation. Instructor: Maria K. Michael. Overview

ECE 407 Computer Aided Design for Electronic Systems. Simulation. Instructor: Maria K. Michael. Overview 407 Computer Aided Design for Electronic Systems Simulation Instructor: Maria K. Michael Overview What is simulation? Design verification Modeling Levels Modeling circuits for simulation True-value simulation

More information

Lecture 6: DC & Transient Response

Lecture 6: DC & Transient Response Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins

More information

Operator-based Model-Order Reduction of Linear Periodically Time-Varying Systems

Operator-based Model-Order Reduction of Linear Periodically Time-Varying Systems 5 Operator-based Model-Order Reduction of Linear Periodically Time-Varying Systems Yayun Wan, Jaijeet Roychowdhury ECE Department University of Minnesota Minneapolis, MN, USA yayun,jr@eceumnedu ABSTRACT

More information

Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay

More information

Chapter 2 Fault Modeling

Chapter 2 Fault Modeling Chapter 2 Fault Modeling Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering National Central University Jungli, Taiwan Outline Why Model Faults? Fault Models (Faults)

More information

System Reduction for Nanoscale IC Design (SyreNe)

System Reduction for Nanoscale IC Design (SyreNe) System Reduction for Nanoscale IC Design (SyreNe) Peter Benner February 26, 2009 1 Introduction Since 1993, the German Federal Ministry of Education and Research (BMBF Bundesministerium füa Bildung und

More information

Computational Electromagnetics Definitions, applications and research

Computational Electromagnetics Definitions, applications and research Computational Electromagnetics Definitions, applications and research Luis E. Tobón Pontificia Universidad Javeriana Seminario de investigación Departamento de Electrónica y Ciencias de la Computación

More information

VLSI Design Verification and Test Simulation CMPE 646. Specification. Design(netlist) True-value Simulator

VLSI Design Verification and Test Simulation CMPE 646. Specification. Design(netlist) True-value Simulator Design Verification Simulation used for ) design verification: verify the correctness of the design and 2) test verification. Design verification: Response analysis Specification Design(netlist) Critical

More information

Lecture 12 CMOS Delay & Transient Response

Lecture 12 CMOS Delay & Transient Response EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology

More information

Lab 3 Revisited. Zener diodes IAP 2008 Lecture 4 1

Lab 3 Revisited. Zener diodes IAP 2008 Lecture 4 1 Lab 3 Revisited Zener diodes R C 6.091 IAP 2008 Lecture 4 1 Lab 3 Revisited +15 Voltage regulators 555 timers 270 1N758 0.1uf 5K pot V+ V- 2N2222 0.1uf V o. V CC V Vin s = 5 V Vc V c Vs 1 e t = RC Threshold

More information

ECE-470 Digital Design II Memory Test. Memory Cells Per Chip. Failure Mechanisms. Motivation. Test Time in Seconds (Memory Size: n Bits) Fault Types

ECE-470 Digital Design II Memory Test. Memory Cells Per Chip. Failure Mechanisms. Motivation. Test Time in Seconds (Memory Size: n Bits) Fault Types ECE-470 Digital Design II Memory Test Motivation Semiconductor memories are about 35% of the entire semiconductor market Memories are the most numerous IPs used in SOC designs Number of bits per chip continues

More information

DC and AC modeling of minority carriers currents in ICs substrate

DC and AC modeling of minority carriers currents in ICs substrate DC and AC modeling of minority carriers currents in ICs substrate Camillo Stefanucci, Pietro Buccella, Maher Kayal and Jean-Michel Sallese Swiss Federal Institute of Technology Lausanne, Switzerland MOS-AK

More information

Behavioral Modeling for Analog System-Level Simulation by Wavelet Collocation Method

Behavioral Modeling for Analog System-Level Simulation by Wavelet Collocation Method IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 6, JUNE 2003 299 Behavioral Modeling for Analog System-Level Simulation by Wavelet Collocation Method Xin

More information

EE100Su08 Lecture #9 (July 16 th 2008)

EE100Su08 Lecture #9 (July 16 th 2008) EE100Su08 Lecture #9 (July 16 th 2008) Outline HW #1s and Midterm #1 returned today Midterm #1 notes HW #1 and Midterm #1 regrade deadline: Wednesday, July 23 rd 2008, 5:00 pm PST. Procedure: HW #1: Bart

More information

INSTRUMENTAL ENGINEERING

INSTRUMENTAL ENGINEERING INSTRUMENTAL ENGINEERING Subject Code: IN Course Structure Sections/Units Section A Unit 1 Unit 2 Unit 3 Unit 4 Unit 5 Unit 6 Section B Section C Section D Section E Section F Section G Section H Section

More information

Electromagnetics in COMSOL Multiphysics is extended by add-on Modules

Electromagnetics in COMSOL Multiphysics is extended by add-on Modules AC/DC Module Electromagnetics in COMSOL Multiphysics is extended by add-on Modules 1) Start Here 2) Add Modules based upon your needs 3) Additional Modules extend the physics you can address 4) Interface

More information

Stability and Passivity of the Super Node Algorithm for EM Modeling of IC s

Stability and Passivity of the Super Node Algorithm for EM Modeling of IC s Stability and Passivity of the Super Node Algorithm for EM Modeling of IC s M.V. Ugryumova and W.H.A. Schilders Abstract The super node algorithm performs model order reduction based on physical principles.

More information

This section reviews the basic theory of accuracy enhancement for one-port networks.

This section reviews the basic theory of accuracy enhancement for one-port networks. Vector measurements require both magnitude and phase data. Some typical examples are the complex reflection coefficient, the magnitude and phase of the transfer function, and the group delay. The seminar

More information

Testability. Shaahin Hessabi. Sharif University of Technology. Adapted from the presentation prepared by book authors.

Testability. Shaahin Hessabi. Sharif University of Technology. Adapted from the presentation prepared by book authors. Testability Lecture 6: Logic Simulation Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Adapted from the presentation prepared by book authors Slide 1 of 27 Outline What

More information

Interconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003

Interconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003 Interconnect (2) Buffering Techniques.Transmission Lines Lecture 12 18-322 Fall 2003 A few announcements Partners Lab Due Times Midterm 1 is nearly here Date: 10/14/02, time: 3:00-4:20PM, place: in class

More information

Generation of Four Phase Oscillators Using Op Amps or Current Conveyors

Generation of Four Phase Oscillators Using Op Amps or Current Conveyors J. of Active and Passive Electronic Devices, Vol. 0, pp. 207 22 Reprints available directly from the publisher Photocopying permitted by license only 205 Old City Publishing, Inc. Published by license

More information

Model order reduction of electrical circuits with nonlinear elements

Model order reduction of electrical circuits with nonlinear elements Model order reduction of electrical circuits with nonlinear elements Andreas Steinbrecher and Tatjana Stykel 1 Introduction The efficient and robust numerical simulation of electrical circuits plays a

More information

Numerical Algorithms for ODEs/DAEs (Transient Analysis)

Numerical Algorithms for ODEs/DAEs (Transient Analysis) Numerical Algorithms for ODEs/DAEs (Transient Analysis) Slide 1 Solving Differential Equation Systems d q ( x(t)) + f (x(t)) + b(t) = 0 dt DAEs: many types of solutions useful DC steady state: state no

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures

More information

Problems in VLSI design

Problems in VLSI design Problems in VLSI design wire and transistor sizing signal delay in RC circuits transistor and wire sizing Elmore delay minimization via GP dominant time constant minimization via SDP placement problems

More information

Equivalent Circuit Model Extraction for Interconnects in 3D ICs

Equivalent Circuit Model Extraction for Interconnects in 3D ICs Equivalent Circuit Model Extraction for Interconnects in 3D ICs A. Ege Engin Assistant Professor, Department of ECE, San Diego State University Email: aengin@mail.sdsu.edu ASP-DAC, Jan. 23, 213 Outline

More information

SERIALLY PROGRAMMABLE CLOCK SOURCE. Features

SERIALLY PROGRAMMABLE CLOCK SOURCE. Features DATASHEET ICS307-03 Description The ICS307-03 is a dynamic, serially programmable clock source which is flexible and takes up minimal board space. Output frequencies are programmed via a 3-wire SPI port.

More information

Thermal-reliable 3D Clock-tree Synthesis Considering Nonlinear Electrical-thermal-coupled TSV Model

Thermal-reliable 3D Clock-tree Synthesis Considering Nonlinear Electrical-thermal-coupled TSV Model Thermal-reliable 3D Clock-tree Synthesis Considering Nonlinear Electrical-thermal-coupled TSV Model Yang Shang 1, Chun Zhang 1, Hao Yu 1, Chuan Seng Tan 1, Xin Zhao 2, Sung Kyu Lim 2 1 School of Electrical

More information

E2.2 Analogue Electronics

E2.2 Analogue Electronics E2.2 Analogue Electronics Instructor : Christos Papavassiliou Office, email : EE 915, c.papavas@imperial.ac.uk Lectures : Monday 2pm, room 408 (weeks 2-11) Thursday 3pm, room 509 (weeks 4-11) Problem,

More information

EEE598D: Analog Filter & Signal Processing Circuits

EEE598D: Analog Filter & Signal Processing Circuits EEE598D: Analog Filter & Signal Processing Circuits Instructor: Dr. Hongjiang Song Department of Electrical Engineering Arizona State University Thursday January 24, 2002 Today: Active RC & MOS-C Circuits

More information

Error Analysis of a Synchronizer Analysis Algorithm

Error Analysis of a Synchronizer Analysis Algorithm Error Analysis of a Synchronizer Analysis Algorithm Mark Greenstreet 1 Chen Greif 1 Suwen Yang 2 1 University of British Columbia 2 Oracle Frontiers of Analog Circuits Outline Metastability: synchronizers

More information

Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics

Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics Lecture 23 Dealing with Interconnect Impact of Interconnect Parasitics Reduce Reliability Affect Performance Classes of Parasitics Capacitive Resistive Inductive 1 INTERCONNECT Dealing with Capacitance

More information

EE5780 Advanced VLSI CAD

EE5780 Advanced VLSI CAD EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay

More information

Order Reduction of the Dynamic Model of a Linear Weakly Periodic System Part II: Frequency-Dependent Lines

Order Reduction of the Dynamic Model of a Linear Weakly Periodic System Part II: Frequency-Dependent Lines 866 IEEE TRANSACTIONS ON POWER SYSTEMS, VOL. 19, NO. 2, MAY 2004 Order Reduction of the Dynamic Model of a Linear Weakly Periodic System Part II: Frequency-Dependent Lines Abner Ramirez, Adam Semlyen,

More information

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DS0026 Dual High-Speed MOS Driver General Description DS0026 is a low cost

More information

Transient Sensitivity Analysis CASA Day 13th Nov 2007 Zoran Ilievski. Zoran Ilievski Transient Sensitivity Analysis

Transient Sensitivity Analysis CASA Day 13th Nov 2007 Zoran Ilievski. Zoran Ilievski Transient Sensitivity Analysis CASA Day 13th Nov 2007 Talk Structure Talk Structure Introduction Talk Structure Introduction Recap Sensitivity Talk Structure Introduction Recap Sensitivity Examples and Results Talk Structure Introduction

More information

Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits

Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 10, OCTOBER 2003 1297 Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits Peng Li, Student

More information

Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements.

Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. 1 2 Introduction Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. Defines the precise instants when the circuit is allowed to change

More information

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE610: CMOS Analog Circuits L5: Fabrication and Layout -2 (12.8.2013) B. Mazhari Dept. of EE, IIT Kanpur 44 Passive Components: Resistor Besides MOS transistors, sometimes one requires to implement passive

More information

Semiconductor Memories

Semiconductor Memories Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " D-Latch " Timing Constraints! Dynamic Logic " Domino

More information

Architecture-level Thermal Behavioral Models For Quad-Core Microprocessors

Architecture-level Thermal Behavioral Models For Quad-Core Microprocessors Architecture-level Thermal Behavioral Models For Quad-Core Microprocessors Duo Li Dept. of Electrical Engineering University of California Riverside, CA 951 dli@ee.ucr.edu Sheldon X.-D. Tan Dept. of Electrical

More information

3 Gramians and Balanced Realizations

3 Gramians and Balanced Realizations 3 Gramians and Balanced Realizations In this lecture, we use an optimization approach to find suitable realizations for truncation and singular perturbation of G. It turns out that the recommended realizations

More information

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,

More information

MM74C922 MM74C Key Encoder 20-Key Encoder

MM74C922 MM74C Key Encoder 20-Key Encoder MM74C922 MM74C923 16-Key Encoder 20-Key Encoder General Description The MM74C922 and MM74C923 CMOS key encoders provide all the necessary logic to fully encode an array of SPST switches. The keyboard scan

More information

EE382M-14 CMOS Analog Integrated Circuit Design

EE382M-14 CMOS Analog Integrated Circuit Design EE382M-14 CMOS Analog Integrated Circuit Design Lecture 3, MOS Capacitances, Passive Components, and Layout of Analog Integrated Circuits MOS Capacitances Type of MOS transistor capacitors Depletion capacitance

More information

Efficient Variability Analysis of Electromagnetic Systems via Polynomial Chaos and Model Order Reduction

Efficient Variability Analysis of Electromagnetic Systems via Polynomial Chaos and Model Order Reduction IEEE TCPMT, VOL. XXX, NO. XXX, 213 1 Efficient Variability Analysis of Electromagnetic Systems via Polynomial Chaos and Model Order Reduction Domenico Spina, Francesco Ferranti, Member, IEEE, Giulio Antonini,

More information

Transistor's self-und mutual heating and its impact on circuit performance

Transistor's self-und mutual heating and its impact on circuit performance Transistor's self-und mutual heating and its impact on circuit performance M. Weiß, S. Fregonese, C. Maneux, T. Zimmer 26 th BipAk, 15 November 2013, Frankfurt Oder, Germany Outline 1. Motivation. Research

More information

Power Grid Analysis Based on a Macro Circuit Model

Power Grid Analysis Based on a Macro Circuit Model I 6-th Convention of lectrical and lectronics ngineers in Israel Power Grid Analysis Based on a Macro Circuit Model Shahar Kvatinsky *, by G. Friedman **, Avinoam Kolodny *, and Levi Schächter * * Department

More information

Reduced Order Modeling Enables System Level Simulation of a MEMS Piezoelectric Energy Harvester with a Self-Supplied SSHI-Scheme

Reduced Order Modeling Enables System Level Simulation of a MEMS Piezoelectric Energy Harvester with a Self-Supplied SSHI-Scheme Reduced Order Modeling Enables System Level Simulation of a MEMS Piezoelectric Energy Harvester with a Self-Supplied SSHI-Scheme F. Sayed 1, D. Hohlfeld², T. Bechtold 1 1 Institute for Microsystems Engineering,

More information

Digital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories

Digital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification

More information

Characteristics of Passive IC Devices

Characteristics of Passive IC Devices 008/Oct 8 esistors Characteristics of Passive IC Devices Poly esistance Diffusion esistance Well esistance Parasitic esistance Capacitors Poly Capacitors MOS Capacitors MIM Capacitors Parasitic Capacitors

More information