AWE Macromodels of VLSI Interconnect for Circuit Simulation *

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1 AWE Macromodels of VLSI Interconnect for Circuit Simulation * Seok-Yoon Kim, Nanda Gopal, and Lawrence T. Pillage Computer Engineering Research Center The University of Texas at Austin 2201, Donley Drive, Suite 395 Austin, Texas Abstract Asymptotic Waveform Evaluation (AWE) has been successfully applied to the evaluation of linear(ized) models of digital system interconnect. What remains is to interface AWE models with the nonlinear rnodels of drivers and terminations that must be taken into account in order to obtain accurate timing information of the overall circuit/system. This paper describes an approach for obtaining time-domain macromodels of linear RLC interconnect that can be easily integrated into any circuit simulator. Based on generalized n-port descriptors, the technique can also be utilized to efficiently synthesize accurate driving-point models that reflect the loading characteristics of complex interconnect systems. 1 Introduction The increases in VLSI circuit complexity and operating speeds demand the use of accurate simulation and verification techniques beginning at the lowest levels of the design verification hierarchy. This demand is particularly evident all the way from the extraction to the system-level verification of high-speed physical interconnect. And, it is believed that even for integrated circuits, interconnect behavior forms the major limitation on the performance of future high-speed, submicron technologies. Irrespective of the design style or methodology, the combined effects of the interconnect and the nonlinear drivers and loads must be simulated during some stage of the verification process. More accurate modeling of interconnects results in large, linear circuit models that can dramatically slow down a circuit simulation [4]. Hence, one approach would be to evaluate linear and non-linear circuit models separately, and combine the results at a later stage. Simulation of the non-linear device models requires the use of conventional simulation techniques such as those employed in SPICE [lo]. The linear models, which also form the major portion of a typical integrated circuit, can however, be evaluated by more efficient techniques. One such technique, developed for the efficient evaluation of large, lumped, linear(ized) RLC circuit mod- *This work was supported in part by the National Science Foundation under MIP # , the Semiconductor Research Corporation under contract #91-DP-142, and International Business Machines Corporation. els, is the method of Asymptotic Waveform Evaluation (AWE) [9]. AWE approximates the driving-point and transfer immitances of these circuit models in terms of their dominant poles and residues, which are in turn, obtained by a moment-matching technique recognized to be a form of the Pad4 approximation. AWE has been applied to a host of CAD problems including interconnect simulation [E], transmission line simulation [13], polezero analysis [5], RC extraction [7], timing analysis [9], and piecewise linear circuit simulation [3]. The underlying theory of AWE is welldocumented in the above references and will not be dealt with in any detail here. This paper focuses on combining the results of the linear AWE and the non-linear circuit simulation, for the specific purpose of efficiently incorporating accurate interconnect information into the overall circuit description. In [13], the exact distributed equations of the interconnect are incor orated as submatrices in the nodal admittance (MNA! matrix of the overall circuit. Any non-linear device equations are linearized through the use of a set of independent, piecewiselinear waveforms [13]. The response moments needed for the AWE analysis of the circuit are generated from the derivatives of the MNA matrix. Additional performance enhancement is achieved by precharacterizing the derivatives of the interconnect submatrices in terms of the eigenvalues and eigenvectors. Obtaining macromodels of a general multi-port in terms of its admittance (y-parameter) matrix is described in [ll]. This macromodel is directly stenciled into the MNA matrix of the overall circuit. The approach in [ll] differs from the approach above in that the AWE technique is only used to obtain rational approximations for the y-parameters of the circuit. In order to compute the port currents that are required for a linear-time complexity convolution, the port voltages are again assumed to be piecewise linear. The response of the overall circuit is then computed using conventional circuit simulation techniques. The main attraction of [Ill lies in its generality. In this paper, simple interconnect macromodel stencils, in SPICElike format, are developed based on a multi-port description. These macromodels can be accessed as device model calls in conventional circuit simulators. No assumptions have been made concerning the voltage waveshapes at the ports, that is, any /92 SO3.W Q 1992 IEEE 64

2 numerical integration method can be used in deriving macromodels. A measure of the local truncation error (LTE) of these macromodels is also developed based on trapezoidal integration method. The multiport descriptions of the interconnect models are efficiently obtained as a preprocess using AWE. In addition, the common-denominator concept, described in [l], is extensively used to simplify the macromodel stencils. The validity of the proposed macromodel is verified by applying it to an example of a large interconnect system obtained from industry. Finally, an explicit description of an interface with a circuit simulator such as SPICE [lo] is discussed. 2 Multi-Port Characterization An interconnect configuration can be considered to be a multi-port network, as shown in fig.1. Such a v1 IL I interconnect configuration 47 Figure 1: Modeling an interconnect system as an N- port network. network is usually characterized in terms of one of the following sets of interchangeable descriptors, namely, 9- (admittance), P- impedance), h- (hybrid), or transmission parametersi21. To facilitate the interface with conventional circuit simulators such as SPICE [lo], which employs Modified Nodal Analysis (MNA), in this work the y- parameters are used to characterize the multi-port interconnect networks, using the following notation: also be viewed as a representation of a lumped-element system, is such that it largely retains the asymptotic behavior of the original N-port network. The generation of the y-parameters for a specified multi-port network is achieved by exciting the network with an impulse voltage at one of the ports while shorting all other ports [2]. Measuring the currents at each of the ports then yields one column of the Y- matrix. This procedure is repeated at each of the network ports to obtain the complete description. Some reduction in computational effort can be achieved by noting that for reciprocal networks such as RLC interconnect circuits, x,(s) = Y.i(s). An essential part in the fohowing development of the macromodels is the assumption of a common denominator, or a common set of dominant poles at all the nodes of the circuit [l]. This is facilitated by the use of moment-shifting, as described in [l], to obtain accurate low-frequency pole approximations using AWE. Further, as recommended in [l], the commondenominator poles are computed at any one of the network ports, i.e., a driving point. Besides helping to avoid the computational expense of calculating pole approximations at every port, the commondenominator approach also greatly simplifies the development of the interconnect macromodels. In this work, the y-parameters were generated using the Rapid Interconnect Circuit Evaluator (RICE), an application-specific implementation of AWE which exploits the tree-like topologies of lumped RLC interconnect circuits to further increase computational efficiency [ Macromodel Synthesis To avoid the explicit convolution problem, which is computationally expensive in terms of storage and run time, a canonical realization of the expression in eq.(2) is used to obtain an equivalent macromodel that can be directly stenciled into the system MNA matrix of the overall circuit. For purposes of clarity, this synthesis procedure is explained using 2nd-order AWE approximations for the y-parameters of a 1-port network, i.e., a driving-point synthesis. Extensions to multi-port networks are discussed in the following section. The port voltage and current of a 1-port are related by the expression: Using AWE, each entry of the Y-matrix in eq.(l) is approximated by a reduced-order model of the form: Assuming zero initial conditions, eq.(3) can be realized in time-domain using a controller canonical form, as shown in fig.2 [6]. Corresponding to the above system, the following set of internal state variables are defined: kl(t) = Vin(t) - QlZl - UoZ2, where 15 i, j 5 N, fi and H are the dominant pole and corresponding residue approximations respectively, q &(t) = q(t). (4) is the order of approximation, and d represents any di- lnon-zero initial conditions affect only the constant bo term rect coupling between ports [Ill. The development of in eq.(3), and are easily incorporatedif the derivatives of either this reduced-order, rational-function model, which can the port current or voltage at t = o are supplied. 65

3 where G,, and le, are as specified in eq.(lo)-(11). The structure and regularity of the expressions in eq.(lo)- (11) enable a simple and efficient implementation. In the case of a driving-point synthesis, the macromodel thus obtained, eq.(lo)-(11), is a Norton equivalent circuit at the driven network port. The circuit described by eq.( lo)-( 11) is equivalent to replacing energy storage elements by their companion models and then collapsing the circuit at the driving-point, to obtain the same equivalent configuration (Refer fig.3). Figure 2: Controller-canonical realization of a 1-port network description. Then, the port current in terms of these state variables is given by: original circuit 43 iin(t) = b2i1 + blzl(t) + bozz(t). (5) To obtain expressions for the state variables 2' in terms of the port parameters, the values of 5 are evaluated at t = t k as follows: TR cm*m circuit ~i(tk) tk = ~i(tk-1) + ii(~) d ~ i, = 1,2. (6) ik-i Various numerical integration methods can be used for integrating eq.(6, including Backward Euler BE), Forward Euler (FE] or TRapezoidal (TR) met h ods, or multi-step methods such as Gear's second-order or Runge-Kutta's method [8]. The precise selection of the integration scheme used depends on that employed in the base simulator. Assuming the TR method of integration, and substituting eq.(4) into eq.(6) yields the updating rule for the internal state variables: aohk-lfz(tk-l)], hk-1 ZZ(tk) = 22(tk-l) + - [21(tk--1) + zl(tk)] (7) 2 where hk-1 = (tk - tk-l), k 2 1, is the internal timestep of the base simulator, and Norton Equivalent (Driving-point) (= 1-port macromodel) Figure 3: Computing the equivalent Norton circuit at the driving-point of a simple interconnect circuit. 4 Multi-Port Analysis The extension of the analysis in the previous section to the case of a multi-port network is hard only in terms of notation. However, the principles and procedures being identical, the extension to an N-port network is well structured and fairly straightforward, as explained below. In the case of an N-port network, the canonical form of the macromodel at each port assumes the form in fig.4. As shown, a description similar to that derived for the l-port network in the previous section and shown in fig.2, exists for each of the N network ports. Each port canonical-model has an associated set of state variables as well. flk-l= [1+(%)~1+(%)'a0]. (8) Plugging eq.(4) and eq.(7) into eq.(5) yields the equation describing the macromodel in the circuit simulator: iin(tk+l) = Gep(tk)Vin(tk+l) 4- Ieq(tk), (9) Figure 4: An abstract controller-canonical realization of the pth port description in an N-port network. 66

4 1 Geq(tk) = b2 -- Qk [ (; 1 ) (ha1 - bl) + (%)2 (b2ao - bo), The main difference between the one-port and multi-port macromodels is the presence of a transconductance factor in the latter, representing the interaction between ports. With reference to eq.(9), the time-domain equations characterizing the pth port in an N-port macromodel in a circuit simulator are: where gpj represents the influence of the j-th port on the pth port of the network. This is represented by a voltage-controlled current source in the multi-port macromodel, as shown in the 2-port macromodel in fig.5. In terms of the internal state variables and the....2mfinetw&... the simulation routines. The equivalent model parameters are calculated using the expressions in eq.(13)- (15), that can be implemented efficiently. 5 Local Truncation Error Estimation Conventional circuit simulators such as SPICE employ measures of the local truncation error (LTE) in controlling time step used in the simulation. Since estimating the LTE requires the 3rd-derivatives of the node variables, information about the active-device nodes at four time-points the current and three previous time points) is stored (I 81. A similar technique can be employed to estimate the LTE for the port currents in the AWE macromodels. Assuming the previously calculated values are exact, as done in SPICE, the LTE for Iij(tk), denoted as 6ij(tk), is given by where tk-1 < ( < tk. The 3rd-derivative in eq.(l?) & approximated by fitting a 3rd-order polynomial to the values of at tk,tk-l, tk-2 and tk-3. This yields the following equation [8]: 1... Figure 5: 2-port macromodel of interconnect for circuit simulation. specified y-parameter approximations, the equations for each of these elements are as shown in eq.(13)-(15), where a.. - b. pa3 - paqaj - bpij. The updating rule for the internal state variables are given by eq.(16), where hk-1 = ( tk-tk-i), 1 5 p 5 N, and To summarize, the large and stiff interconnect circuits encountered in typical VLSI circuits are replaced by the simple macromodels that can be directly stenciled into the MNA matrix formulated by conventional circuit simulators. No modifications are required in where DD3 stands for 3rd divided-difference equation and is represented by: To evaluate eq.( 18) more efficiently, the values of the divided-difference vectors of can be stored in place of IC;.. Once ij(tk) is evaluated, the LTE's for port currents can be easily estimated using eq.(12) and eq.(15). For the sake of notational convenience, eq.(12) is rewritten as: N N q Ip(eq)(tk) = c (!?pj -bpjq)vj (tk)+e cpij (tk)2ij (tk), j=1 i=l j=1 (20) 67

5 where cpij (tk) represents the corresponding coefficient term in eq.(12). Then, the LTE for ip(tk), denoted as Ep(tk), is approximately given by: N o 6 Results With an accurate macromodel for the transmission line, the effects of nonlinear drivers and terminations can be considered. Figure 6 shows an example configuration of a nonlinear load driven by an ECL gate through a lcm length of low-loss transmission wire. Using a macromodel constructed from 6th-order approximations of the transmission line, the clipping action of the diodes is clearly seen. Note that the result obtained using the macromodel is indistinguishable from that obtained using the complete circuit model of the transmission line. The easy handling of multiple drivers in a circuit, is invaluable when considering coupled interconnect systems, such as the MOS example in fig.7. In this case, 8th-order AWE approximations of the y-parameters of the coupled interconnect system were considered. The results again show excellent accuracy in the response waveforms (when compared to a conventional simulation using lumped models). Finally, the effect of coupling is again illustrated using an example from ECL technology, as shown in fig.9. Using macromodels for the coupled transmission-line system accurately shows the effect of switching noise on the passive line. For this example, Gth-order AWE approximations of the y-parameters m U m 3 7i Lumped ckt - Macromodel - 0 5e-10 le-09 Figure 6: Lossy transmission line with ECL driver and nonlinear diode termination. 68

6 Figure 7: Lossy, coupled transmission lines with multiple MOS drivers and nonlinear MOS terminations. were used in generating the macromodel. Note that al U fa rl I I I I I I 0 2e-084e-086e-088e-081e-Oa.2e m U ';1-1.2 > * t c--~_c I I I I I I t \ Port 3-Lumped ckt - Port 4-Lumped ckt Port 3-Macromodel Port 4-Macromodel ' I I I 0 2e-10 4e-10 6e-10 8e-10 le-09 Figure 9: Lossy coupled transmission lines with multiple ECL drivers and nonlinear terminations. al m 3 U > e-084e-08 6e-088e-081e-0i1.2e-07 Figure 8: Response waveforms of the circuit in fig.7. all of the macromodel responses are indistinguishable from the complete circuit responses as long as the reduced-order AWE model is sufficiently accurate. 7 Interfacing to a Circuit Simulator Figure 10 summarizes the overall approach proposed in this paper. As seen, the multi-port parameter descriptors need be computed only once for a section of interconnect, immediately following the circuit extraction stage of design verification. Our model card for a multi-port element in a netlist input to a circuit simulator is as follows: P<name> <#ports> <node 1> <node 2>... <model name> <order of y-approx.>. T Extraction Transistors Circuit Simulator i Linear Interconnect AWE (RICE) w - arameters Figure 10: Program organization of enhanced simulator incorporating interconnect macromodels. 69

7 The form of the model is:.model <model name> DENOM=(ao U*) YII=(<num. coeff.>) Y12=(<num. coeff.>).... The example shown in fig.11 illustrates the ease of notation and compact nature of this specification. P1 Q *Lossy interconnect macromodel *Ramp voltage driver Vi 1 0 PULSE(0 I 0 le-9) *Transmission-line macromodel Pl TLI 4 *Load capacitor Ci 2 0 le-i2 0.0 *Model specification of multiport macromodel.model TL1 DENOM=(I.O 6.06e e20 1.6e25) +Yil=(O.l 6.05e6 8.22e ei9 4e23) +Yi2=( e23) +Y21=( e23) +Y22=( ~168.22e e19 4e23). END Figure 11: Example specification of a lossy interconnect using the approach proposed in this paper. The macromodel element routines are then called at each time-step, using a routine which requires only the model information and the step size At. From this model, generalized MNA stencils are used to fill in the port parameters in the MNA matrix. 8 Conclusion A simple macromodel based on the y-parameter description of a complex interconnect network has been derived. This enables the reduction of large, stiff interconnect configurations into compact representations that pose minimal problems to conventional circuit simulation techniques. The macromodel can be incorporated directly into a conventional circuit simulation with no modification of the original simulation software. The techniques proposed herein are suitable for development as a software library that can be used to enhance existing simulators to handle large VLSI interconnect configurations very efficiently. In addition, the ability to handle elements at the port level makes the proposed approach extremely attractive for any linear(ized) macromodels or for applications such as mixed-mode simulation. References [l] I>. F. Anastasakis, N. Gopal, S. Y. Kim, and L. T. Pillage. On the stability of approximations in Asymptotic Waveform Evaluation. In Proc. 2Sth ACM/IEEE Des. Auto. Conf., Jun [2] Desoer and E. Kuh. Basic Curcuit Theory. McGraw-Hill, [3] C. T. Dikmen et al. Piecewise linear Asymptotic Waveform Evaluation for transient simulation of electronic circuits. In Proc. IEEE Int '1. Symp. Ckt. Sys., Jun [4] N. Gopal, E. Tuncer, D. P. Neikirk, and L. T. Pillage. Evaluation of high-performance interconnect using lumved models. IEEE Trans. Ckt. Sus. (submittgd). X. Huang. Pade approximation of linear(ized) circuit responses. PhD thesis, Carnegie Mellon Univ., Nov T. Kailath. Linear Systems. Prentice-Hall, Inc., S. Kumashiro, R. Rohrer, and A. Strojwas. A new efficient method for the transient simulation of 3D interconnect structures. In IEDM Tech. Dig., L. W. Nagel. Spice2, a computer program to simulate semiconductor circuits. Technical Report TR-ERL-M520, UC-Berkeley, May L. T. Pillage and R. A. Rohrer. Asymptotic Waveform Evaluation for timing analysis. IEEE Trans. Computer-Aided Des., 9, PSPICE USERS' MANUAL. Version Microsim Corp., Jan V. Raghavan and R. A. Rohrer. AWESpice: A general tool for the efficient and accurate simulation of interconnect problems. in hoc. 29th ACM/IEEE Des. Auto. Conf., Jun C. L. Ratzlaff, N. Gopal, and L. T. Pillage. RICE: Rapid Interconnect Circuit Evaluator. In Proc. 28th ACM/IEEE Des. Auto. Conf., Jun T. K. Tang, M. S. Nakhla, and R. Griffith. Analysis of lossy multiconductor transmission lines using the Asymptotic Waveform Evaluation technique. IEEE Trans. Microwave Th. tech., 39(12), Dec

EE5900 Spring Lecture 5 IC interconnect model order reduction Zhuo Feng

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