Achieve Your Best Design with SI

Transcription

1 Achieve Your Best Design with SI and PI concerns SIPro and PIPro Application Engineer / Keysight Technologies Nash TU Taipei

2 Contents Signal Integrity Design Cycle SIPro PIPro Power-aware SI Simulation 2

3 Signal Integrity Design Cycle Modeling is to define mathematical presentations of channels, transmitters and receivers using proper tools such as EM solvers or test instruments, and etc. Modeling Simulation For SI simulation, S Parameter, Transient and ChannelSim are commonly used simulators in ADS. Simulation result would include eye pattern, eye height, eye width, jitter, and etc. Value of a simulation is to estimate performance of a real system. To know how good a simulation, we will rely on correct measurement. The correlation between simulation and measurement provides know-how to improve modeling and simulation. Correlation Analyses Analyses include system optimization, Monte Carlo, yield analysis, sensitivity and Design of Experiment (DOE), etc. 3

4 Keysight EDA in Signal Integrity Design Modeling Simulation Correlation Analyses 4

5 ADS SI Modeling Flow Modeling Simulation Pre-layout Simulation Correlation Analyses PCB Layout EM Solver S Parameter PCB Layout Post-layout Simulation 5

6 ADS: SIPro and PIPro A C O H E S I V E W O R K F L O W F O R S I A N D P I A N A LY S E S Layout Import into ADS (Direct *.brd Import, Allegro ADFI or ODB++ flow) SIPro / PIPro Analysis Transient Convolution Channel Sim DDR Bus Sim Layout Set up and run analyses Manage nets, VRMs, sinks, components ADS Schematic 3D layout view and results visualization 4 New EM Simulators PI-DC IR Drop PI-AC PDN Impedance Power Plane Resonances Power-Aware Signal Integrity 6

7 Increased Productivity for Post-layout Analysis S E A M L E S S F L O W F R O M E M - A N A LY S E S B A C K I N T O S C H E M AT I C F O R B O T H S I A N D P I Channel simulation Transient simulation SSN Analysis I/O ports Signal Integrity Design Cycle Automated Test Bench Generation PDN Impedance Data with VCC Bounce S-parameter Extraction 7

8 Contents Signal Integrity Design Cycle SIPro PIPro Power-aware SI Simulation 8

9 SIPro S I M U L AT I O N T E C H N O L O G Y O V E R V I E W A composite technology of fast FEM + Planar EM Power-Aware Signal Integrity Speed and Accuracy A purely EM-based simulation, capturing more EM effects than 2D-hybrid solutions SI-specific, net-driven use-model and flow Easily plot Transmission, Return loss, Xtalk and TDR/TDT Automatic-schematic generation EM model flows back to schematic ready for further simulation with Transient, Channel Sim, DDR Bus Sim and more Power-Aware Signal Integrity 9

10 Frequency 3D-Planar EM Full-Wave 3D EM SIPro S I M U L AT I O N T E C H N O L O G Y C O M PA R I S O N F O R H I G H - S P E E D D I G I TA L P C B S Speed/Capacity 40GHz 20GHz 10GHz 5GHz Hybrid 2D Tline + FEM New Technology Area Accuracy 10

11 SIPro: Accuracy S I M U L AT I O N C O M PA R I S O N F R O M W I L D R I V E R T E C H N O L O G Y T E S T C A S E Stripline Beatty Standard Test Structure Wild River Technology CMP-28 SI Kit Full-wave 3DEM (FEM) SIPro (New Technology) 11

12 SIPro: Speed and Accuracy X I L I N X K C U F P G A P L AT F O R M B O A R D Example : SFP (Small Form Factor Pluggable) TX channel Very good agreement! SIPro finished in 18 min, a fraction of simulation time compared to FEM SIPro: 1GB memory, 6 secs per frequency point FEM: 8GB memory, 12 mins per frequency point 12

13 SIPro: Accuracy D D R 4 D Q C H A N N E L, M E A S U R E D V S S I P R O Measurement: Courtesy of GigaTest Labs 28-layer Xilinx UC1650B DDR4 memory characterization board DDR4_C2_DQ4 single ended line (cookie cut) DDR4_C2_DQ4, Single Ended 2431 mil path length 20GHz or 2λ with Er=4) Red = SIPro Black = Measured 13

14 SIPro: SI-specific Use-model and Flow L AY O U T T O R E S U LT S I N L E S S T H A N 2 0 C L I C K S No layout simplification required! Net-driven Guided port creation Quickly plot all crosstalk elements from the same component Easily plot TDR/TDT Mixed-mode S- parameters 14

15 Contents Signal Integrity Design Cycle SIPro PIPro Power-aware SI Simulation 15

16 PIPro S I M U L AT I O N T E C H N O L O G Y O V E R V I E W PIPro has an efficient net-driven PI analysis setup with 3 new simulator engines Speed and Accuracy PI-specific net-driven use-model and flow Change decap values/models without needing to re-simulate Automatic-schematic generation EM model flows back to schematic ready for further simulation with behavioral and circuitlevel simulations of VRMs, sinks and more PI-DC IR Drop Power Plane Resonances PI-AC PDN Impedance 16

17 Z11 [Ohm] Z11 [Ohm] PIPro: Accuracy C U S T O M E R VA L I D AT E D T E S T - C A S E, S I M U L AT I O N V S. M E A S U R E D D ATA 10 2 Bare-Board measurement PIPro PiPro 10 1 PDN populated with Decaps measurement PIPro PiPro Customer used ideal cap values with no ESR specified, hence sharp resonances Frequency [GHz] Frequency [GHz] Test case: ATE test card PDN traverses many layers Ideal VRM model. Customer did not have IC data. 17

18 Designed for Usability Filter by Net Filter by Component Right-click to add-to-analysis Drag & Drop Hierarchical search for complex selections Context sensitive menus e.g. Select instances connected to ONLY the selected nets Easily copy setups from one analysis to another Filters 3D Layout View Color coded Nets 18

19 PIPro DC IR Drop Sink : U V Vdrop= 53 mv Sink : U V Vdrop= 52 mv Voltage and current reported per Via, Sink, VRM and more! VRM: U4 1.2 V Power Dissipation and Current Density visualization Sink : U V Vdrop= 52 mv Sink : U V Vdrop= 52 mv Xilinx KCU105 VCC1V2 PDN 19

20 PIPro AC PDN Impedance Analysis Voltage, current and Power Loss Density Plots Component Model assignment: Lumped SnP Murata Samsung TDK Create custom parts from Schematic models Easy setup: Filter, drag and Drop Components + Full scripting support for setup, simulation and post-processing 20

21 PIPro AC PDN Impedance Analysis D E C A P S E L E C T I O N I N P I P R O Voltage, current and Power Loss Density Plots Analyze effect of decap model changes without re-simulation. Original PDN Impedance New Model Selected 21

22 PIPro PDN Impedance Decap Optimization Nominal Optimized - Reduce BOM cost by removing decaps - Finds optimal design based on user s desire for fewest decaps, vendors, models and lowest total price 22

23 Decap Optimization in PIPro-AC Fundamental setup items: AC analysis Decaps defined in Component Models Launched from AC analysis: Decap Optimization 23

24 Decap Optimization in PIPro-AC I N C L U D I N G O P T I M I Z AT I O N - S P E C I F I C I N F O R M AT I O N Decaps that should be excluded from the optimization procedure Target Impedance required as spec 24

25 DeCap Optimization in PIPro-AC D E S I G N C H O I C E : F L E X I B I L I T Y T O I D E N T I F Y E F F E C T O F C O N S T R A I N T S Full calculation only launched for new setup and/or new target Instantaneous refresh of solutions when updating constraints Allows to easily update the suggested solutions Optimization does not require a re-simulation of the PIPro AC EM sim! Optimization divided in two distinct steps: 1. Main optimization step Minimum set of solutions needed to be evaluated 2. Refinement step Continues to evaluate the full set of solutions Shows current best result to ensure existence of solution when stopped 25

26 DeCap Optimization L I S T S O R T I N G 10 best results are presented Detailed overview of each results exits Impedance graph wrt original solution Detailed decap configuration with assigned model Loop inductance table New AC analysis can be created for each result 26

27 DeCap Optimization in PIPro-AC Importance of DeCap Optimization Goal: Reducing cost, enforce flatter PDNs, and free-up board space Ensure impedance constraints are met using a less conservative decoupling scheme Choose optimal model given the user-defined constraints New tool allowing more flexibility, and designed not to require a re-simulation of the EM model for each optimization 27

28 PIPro Power Plane Resonance Analysis S E L F R E S O N A N C E S Analyze self-resonances of the PCB and inspect trouble areas that have the highest field strength 28

29 Contents Signal Integrity Design Cycle SIPro PIPro Power-aware SI Simulation 29

30 Power Aware SI Simulation D AT A S I G N A L ( D Q 0 ) W I T H A N D W I T H O U T P O W E R P L A N E ( W I T H D E C A P S ) VRM U60 30

31 Power Aware SI Simulation D AT A S I G N A L ( D Q 0 ) W I T H A N D W I T H O U T P O W E R P L A N E ( W I T H D E C A P S ) Power Aware SI Simulation amplitude time Only SI Simulation Blue Line : Data Signal DQ0 without Power Plane - with Decaps ( SI simulation) Red Line : Data Signal DQ0 in presence of Power Plane with Decaps ( Power Aware SI Simulation) 31

32 0 Power Aware SI Simulation D AT A S I G N A L ( D Q 0 ) W I T H A N D W I T H O U T P O W E R P L A N E ( W I T H D E C A P S ) Only SI Simulation (no Power nets effect) in simulation Power Aware SI Simulation taking Power nets in simulation Eye Diagram without taking effect of Power Net Eye Diagram with Power Net ( Power Aware SI) 32

33 Summary SIPro is an resource efficient EM tool to extract S-parameter from High Speed Digital PCBs. Proven to correlate well with measurement results and other 3DEM solvers. Tightly connected to ADS SI simulation flow. PIPro Provides seamless flow from DC, AC to resonance simulation. Can help utilize your resource with De-cap optimization. 33

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