Modeling the sensitivity of CMOS circuits to radiation induced single event transients

Transcription

1 Available online at Microelectronics Reliability 48 (2008) Modeling the sensitivity of CMOS circuits to radiation induced single event transients Gilson I. Wirth a,b, *, Michele G. Vieira a, Egas H. Neto a, Fernanda Lima Kastensmidt b a State University do Rio Grande do Sul, UERGS, Guaiba, RS, Brazil b Universidade Federal do Rio Grande do Sul, UFRGS, Porto Alegre, RS, Brazil Received 6 December 2006 Available online 6 March 2007 Abstract An accurate and computer efficient analytical model for the evaluation of integrated circuit sensitivity to radiation induced single event transients is presented. The key idea of the work is to exploit a model that allows the rapid determination of the sensitivity of any MOS circuit to single event transients (SETs), without the need to run circuit level simulations. To accomplish this task, both single event transient generation and its propagation through circuit logic stages are characterized and modeled. The model predicts whether or not a particle hit generates a transient pulse which may propagate to the next logic gate or memory element. The electrical masking (attenuation) of the transient pulse as it propagates through each stage of logic until it reaches a memory element is also modeled. Model derivation is in strong relation with circuit electrical behavior, being consistent with technology scaling. The model is suitable for integration into CAD-Tools, intending to make automated evaluation of circuit sensitivity to SEU possible. Ó 2007 Elsevier Ltd. All rights reserved. 1. Introduction Semiconductor technology scaling leads to complex circuits made of ever shrinking devices, and as a consequence, integrated circuits have become more susceptible to energetic particle strikes. If an energetic particle strikes a sensitive region in a semiconductor device, the resulting electron hole pair generation can cause a transient pulse that may alter the logical state of the struck circuit node. In digital circuits, this temporary voltage or current disturbance at a circuit node is called a single event transient (SET). A SET may change the results of a computation, if it propagates to a latch or other memory element. With decreasing device dimensions in modern technologies, SETs become a concern not only in space environment, but also at ground level [1 5]. Therefore efficient * Corresponding author. Address: UFRGS Universidade Federal do Rio Grande do Sul, Departamento de Engenharia Eletrica, Av. Osvaldo Aranha, 103, Porto Alegre, RS, Brazil. Tel.: ; fax: address: wirth@inf.ufrgs.br (G.I. Wirth). SET sensitivity analysis methods will be needed to be included in the design flow of integrated circuits. At the design phase, it is common practice to evaluate the sensitivity of a circuit to a SET through electric-level simulation (using Spice-like simulators). However, considering the design flow of modern systems-on-chip composed by millions of transistors, electric-level simulation may be too time consuming. Computer efficient techniques are needed to improve the analysis of the sensitivity of multi million transistor designs to SET. The transient pulse generated by the charge deposition mechanism might not be captured by a memory circuit because it could be logically, electrically or latching-window masked [10]. Logical masking occurs when a particle strikes a circuit node that is blocked out from affecting the output due to a subsequent gate whose output is determined solely by its other inputs. Electrical masking occurs when the transient pulse generated by the particle hit is attenuated as it propagates through the logical gates and filtered out before it reaches a memory element. Strong pulses may propagate through more logical gates than weaker ones. Latching-window masking occurs when the /$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi: /j.microrel

2 30 G.I. Wirth et al. / Microelectronics Reliability 48 (2008) transient pulse reaches a latch outside the latching window, i.e., not at the clock transition when the latch captures its input values. Narrow pulses have a smaller latching probability than wider ones. Different radiation sources show different charge deposition waveforms. The waveform shape can be the decisive factor for a single event upset (SEU) occurrence or not in CMOS circuits. As a consequence the soft error susceptibility of internal nodes in a logic circuit may vary by orders of magnitude. This makes possible to significantly reduce the soft error rate with a reduced cost overhead. Once the nodes with the greatest soft error susceptibility are identified, soft error hardening techniques may be applied to decrease the susceptibility of these nodes. In this work SET generation and propagation in MOS circuits is studied and modeled, helping to implement a simple methodology for identifying the logic circuit nodes most susceptible to transient faults. A number of different methodologies for the evaluation of the sensitivity of digital circuits to SETs have been proposed [1 5]. The sensitivity analysis may be performed at different levels of abstraction. At higher abstraction levels, the impact of an energetic particle may be simulated by momentarily changing the logic value at the struck node. Lower level models may be implemented by device simulation of the charge collection from energetic particle tracks. The availability of analysis tools at different abstraction levels is important to allow the circuit designer to choose the proper balance between speed and accuracy. To allow analysis at different abstraction levels, models that properly link the effects from lower abstraction levels up through the higher levels are mandatory. The model proposed here links the transistor level effects to the logic level without requiring circuit simulation. Considering the tight time to market window imposed to the semiconductor industry, full transient simulation, either at device or circuit level, can be too time consuming for the comprehensive evaluation of the sensitivity of complex circuits to all the different radiation sources. The availability of a simple analytical model, without requiring circuit simulation, could help simplify the evaluation of circuit sensitivity to SEU. This work is aimed at providing such a simple model. The model describes the behavior of the energetic particle strike phenomenon at the logic level and avoids running costly circuit level simulations. This allows rapidly determining the range of particle charge depositions for which the circuit is SEU robust. The analysis of radiation effects on MOS circuits has been an area of intense research in the past years. Earlier works, such as [7 10], have already proposed logic level or mixed signal analysis of radiation induced SETs. Many approaches have been proposed for speeding up the sensitivity analysis process, neglecting pulse degradation (electrical masking) [8 10]. Electrical masking can prevent a SET from propagating through the logical chain and reaching a memory element. For proper analysis of circuit sensitivity to SET, both transient pulse generation and propagation have to be modeled. Other approaches are designed to specifically deal with sequential circuits [9]. 2. Single event transient generation If an energetic particle strikes a sensitive region in a semiconductor device, the resulting electron hole pair generation can cause a transient current that may alter the logical state of the circuit. The charge deposition mechanism produces a transient pulse that lasts until the deposited charge is conducted away via open current paths to V DD or ground, returning the logic node to its original state. If pulse amplitude is high enough and pulse duration is long enough, the pulse may propagate through subsequent circuit stages and change the results of a computation. Hence, pulse amplitude and duration are key parameters for evaluation of circuit sensitivity to SEU. The sensitive sites are the surroundings of the reversebiased drain junctions of a transistor biased in the off state, as for instance the drain junction of the p-transistor in Fig. 1. As current flows through the pn-junction of the struck transistor, the transistor in the on-state (n-transistor in Fig. 1) conducts a current that attempts to balance the current induced by the particle strike. If the current induced by the particle strike is high enough the on-transistor can not balance the current and a voltage change at the node will occur. This voltage change lasts until the charge is conducted away by the current feed through the ontransistor. Through this work a SET that may propagate to the next stage is assumed to be generated by the particle hit if the voltage at the struck node changes by more than V DD /2, i.e., if the voltage change at node crosses the logical threshold. The transient pulse duration or width T D is defined as the time during which the voltage change (perturbation) at the node is greater than V DD /2. In circuit analysis the charge collection mechanism is represented by introducing a transient current source with 1 0 V dd Fig. 1. At Spice level simulation the charge deposition mechanism is modeled by a transient current source.

3 G.I. Wirth et al. / Microelectronics Reliability 48 (2008) the appropriate characteristics at the circuit node where the particle hit occurs, as shown in Fig. 1, which depicts the situation for a particle hit at the drain junction of the p-transistor in the off state. For particle hits at drain junctions of n-transistors in the off state, the transient current is in the opposite direction. Device level simulations carried out by various groups demonstrated the validity of this approach for circuit level analysis of SET [2 4]. At the circuit level, the charge deposition mechanism can be modeled by a double exponential current pulse at the particle strike site [6] I P ðtþ ¼I 0 ðe t=s a e t=s b Þ where I 0 is approximately the maximum charge collection current, s a is the collection time constant of the junction and s b is the time constant for initially establishing the ion track. The maximum charge collection current I 0 depends on the energetic particle linear energy transfer (LET) value and process parameters. Once the values of I 0, s a, and s b are determined for a given technology and particles of interest, any circuit designed in that technology may be evaluated at the circuit level modeling the charge deposition mechanism by Eq. (1). The values of I 0, s a, and s b for a given technology may be obtained by device simulation as well as from closed form expressions [6,7,11]. In the following circuit simulations and modeling, s b is assumed to be much smaller than s a, while s a is used as a variable parameter, which is in line with experimental findings [6,7]. Typically, s a increases almost linearly with increasing LET [11]. In the following, a simple analytical model, that yields results equivalent to circuit simulation if a current pulse as given by (1) is injected at the struck node, is derived. The model will provide information that is valuable for logic level analysis of SETs, namely, single event transient pulse duration (width) and amplitude, without the need to run circuit level (Spice-level) simulations. For transient fault analysis the circuit is sub-divided into stages, in an approach similar to the one used in timing analysis, at the design logic level [12]. A stage is a structure ð1þ composed by a PMOS block and a NMOS block connected to the output node, as depicted in Fig. 2. The block is a set of series-parallel connected transistors. For modeling purposes, a network model as depicted in Fig. 3 is used, where C is the effective capacitive loading lumped onto the output node, and R the effective resistance of the pull-up path (if the PMOS block is on ) or pull-down path (if the NMOS block is on ). I P (t) is the current induced by the particle strike, as given by (1). Once the effective resistance R for each transistor type (n or p) in a given technology has been determined, the effective resistance R of the transistors with different geometries can be determined by multiplying by the W/L ratio of the actual transistor. The use of a linear resistor to model the pull-up or pull-down path is a method well-known from switchlevel simulators [12]. The differential equation describing the voltage V(t) at the struck node is dv ðtþ C þ V ðtþ dt R ¼ I PðtÞ ð2þ The solution of this differential equation leads to the voltage V(t) at the struck node. For s b much smaller than s a, the solution is V ðtþ ¼ I Os a R s a RC e t erc t The time t peak at which the node voltage reaches its maximum value can then be evaluated as being ln RC RC t peak ¼ ð4þ s a RC Inserting t peak back into (3) leads to the peak transient voltage V peak reached at the struck node V peak ¼ I Os a R s RC a RC s a RC ð5þ s a RC RC RC ð3þ The minimum injected charge Q C (Q C = I 0 s a ) needed to cause a transient pulse of amplitude V peak is then V peak ðs a RCÞ Q C ¼ RC ð6þ RC R RC RC RC Fig. 2. A circuit stage is a structure composed by a NMOS block and a PMOS block. Fig. 3. Equivalent circuit for calculating circuit response to an energetic particle hit.

4 32 G.I. Wirth et al. / Microelectronics Reliability 48 (2008) By exploring the asymptotic behavior of (6), the model can be further simplified. From mathematical analysis, it is found that if s a is much smaller than RC, then Q C! V peak Æ C. Ifs a is much greater than RC, then Q C! (V peak /R) s a. From this asymptotic behavior a simpler equation can be proposed to model circuit behavior Q C ¼ Q N þðv peak =RÞs a ð7þ where Q N = V peak Æ C. Now that a simple and computer efficient formulation for the minimum injected charge needed to cause a transient pulse of amplitude V peak has been obtained, the transient pulse duration (width) T D may be evaluated. Starting from (3) a simple equation for the transient pulse duration T D may be derived. The voltage V(t) at the struck node shows a double exponential behavior. After the peak transient voltage V peak is reached at time t peak, the node voltage starts to decrease exponentially. Exploring the asymptotic behavior of (3) in a similar way as done in the derivation of (7), the following equation may be proposed T D ¼ t peak RC ln V DD =2 s a ln V peak V DD =2 V peak where the sum of t peak to the second term at the right hand side corresponds to the analytical solution of the equation V(t)=V DD /2 if the RC time constant is much greater than s a. The sum of t peak to the last term at the right hand side corresponds to the analytical solution if s a is much greater than RC. Mathematical analysis of (5) allows the determination of a simple and accurate fitting for V peak V peak ¼ I Os a R ð9þ s a þ RC Eq. (9) is computationally more efficient than (5) and is used in Section 4, where model equation results are compared to Spice level simulations. The mathematical analysis of the asymptotic behavior that leads to the derivation of (7) starting from (6), and ð8þ of (9) starting from (5), is related to the electrical response of the struck node. If the response of the circuit at the struck node is much slower than s a, then the transient current pulse is effectively integrated by the nodal capacitance C, and the amount of charge that flows through the equivalent resistance R is negligible. If, however, the RC time constant at the node is much shorter than s a, then the circuit responds to the delivered charge faster than the pulse delivers it, and pulse duration is relevant to the circuit response. This concept is critical to the accurate modeling of SETs at the circuit level [16 19]. 3. Single event transient propagation The duration of a SET may degrade as it propagates through a chain of logic gates. Circuit simulations show that SET degradation occurs when an input transition occurs before the gate has completely switched from its previous transition. When this occurs, the output switches in the opposite direction before it reaches the peak amplitude, V DD in the case of a zero to one transition, or ground in the case of a one to zero transition. Also, circuit delays caused by the switching time of the transitions cause the rise and fall time of the pulse to increase [10,13]. These two effects reduce the duration of an output transition, decreasing the soft error rates caused by energetic particle hits in combinatorial circuits. Fig. 4 exemplifies this behavior for a simple chain of NAND gates. The analysis of transient pulse propagation shows that pulse degradation is directly influenced by the propagation delay (tp) of the logic gate. As larger tp, greater will be the degradation of the output pulse. Circuit simulation shows that this holds for gates of different geometry and complexity, in different technology nodes. The model presented in this section is based on results obtained from Spice level circuit simulation in four different technology nodes: the commercially available AMS 0.35 lm technology node [14], as well as the models made publicly available by the device modeling group at the University of California at Berkeley for the 0.18 lm, 0.13 lm Fig. 4. Degradation of a transient pulse as it propagates through a chain of NAND gates, where V in is a transient voltage pulse caused by an energetic particle hit at the input of the chain. Pulse duration is defined as the time the signal remains above V DD /2.

5 G.I. Wirth et al. / Microelectronics Reliability 48 (2008) and 0.10 lm technology nodes [15]. The main conclusion drawn from the analysis of transient pulse propagation is that the propagation delay of a gate (tp) can be used as a benchmark in the study of the degradation of transient pulses. The proposed model gathers the dependence on all parameters that influence pulse degradation into a single one, namely the propagation delay tp, aiming for the provision of a simple and computationally efficient model. Among the parameters that influence pulse degradation are channel length and width, capacitance at the node (fan-out), supply voltage V DD and gate complexity. For modeling purposes, simulations for chains of different logic gates, with different geometries, fan-out and in the different technology nodes, were carried out. Pulse degradation was modeled by curve fitting, after characterization of transient pulse degradation as it propagates through a chain of equal logic gates. A similar approach has already been proposed for the modeling of delay degradation in static CMOS gates [13]. The response of the gate to an input transient is divided into four regions, according to the relation between the input transient duration s and the gate delay tp. The first region represents the situation in which the transient pulse is filtered out. Electrical simulations show that a minimum pulse width is needed at the input of a gate, in order to induce an output transition, i.e., change the output voltage by V DD /2. For input transients with duration smaller then this minimum width, the output voltage does change less than V DD /2, i.e., the transient pulse is not propagated to the next stage. Thus, the model for this region is if ðs n < k tpþ; s nþ1 ¼ 0 ð10þ where s n and s n+1 are the transient pulse durations at the nth and (n + 1)th stages, respectively. k is fitting parameter equal to the minimum ratio s n /tp needed for a SET to be propagated to the next stage. The me k is used for all logic gates of the technology node, regardless of their fan-out or number of inputs. Hence, k has to be determined only once for a given technology node, in a pre-characterization step. The second and third regions model the situation in which the pulse is propagated but degraded in amplitude and duration. It is found that the pulse degrades faster in the last stages before being filtered out. Hence, it is appropriate to model pulse attenuation into two regions, with different equations modeling the degradation in each one of these two regions. The model for the second region, obtained by curve fitting, is if ðk tp < s n < ðk þ 1ÞtpÞ; s nþ1 ¼ðkþ1Þtpð1 e ð2:5 ðsn=tpþþ Þ ð11þ The model for the third region, where pulse duration is not degraded as fast as in the second region, is if ððk þ 1Þtp < s n < ðk þ 3ÞtpÞ s nþ1 ¼ðs 2 n ð12þ tp2 Þ=s n The fourth region represents the situation in which the transient pulse is not degraded. This occurs when the input pulse has duration (s n ) greater than (k + 3) times tp. In this case the degradation of the input pulse is negligible. Hence, for modeling purposes no pulse degradation is assumed to occur in this region if ðs n > ðk þ 3ÞtpÞ; s nþ1 ¼ s n ð13þ 4. Model validation In this section models for both pulse generation and propagation are validated by comparing the results obtained using model equations to Spice level simulations in the four different technology nodes studied (AMS 0.35 lm, Berkeley 0.18 lm, 0.13 lm and 0.10 lm). Supply voltages V DD are 3.3 V, 2.2 V, 1.5 V and 1.2 V, for the 0.35 lm, 0.18 lm, 0.13 lm and 0.10 lm technology nodes, respectively. Inverters, 2- and 4-input nand gates, and 2- and 4-input nor gates with different fan-out are simulated. For validating the model for a SET generated by a particle hit, Spice transient analysis is performed injecting a double exponential current pulse as given by (1) at the struck node. The resulting pulse duration and amplitude is then compared to results obtained with model equations. The double exponential model as given by (1) is proven to be adequate to study the SET mechanism at the circuit simulation level [2 6]. At this point, only particle hits at the drains of the transistors connected to the output node of the logical gate are considered, i.e., particle hits that cause direct charge injection at the output node of a stage. Particle hits at internal nodes of a gate will necesrily cause a smaller SET at the output node. The main goal of the work is to provide a simple analytical model to evaluate the sensitivity of each gate in a complex circuit. It is the most critical node that determines the sensitivity of the gate. Nevertheless, it is important to note that the model may be used to analyze the sensitivity of internal nodes as well, since circuit analysis techniques may be used to reduce the circuit to an equivalent to the one in Fig. 3. First, the minimum charge needed to cause a SET, as a function of the particle hit parameters I 0 and s a, is evaluated. A SET is assumed to occur if the voltage at the struck node changes by more than V DD /2, i.e., V peak is set equal to V DD /2 in (6) (8). Several simulations are performed in order to evaluate the minimum I 0 corresponding to each s a in the range of the collection time constants of the junction. Note that for the determination of the minimum required charge Q C corresponding to a given pulse duration a large number of Spice simulations needs to be performed. Here, some typical results obtained when comparing model and circuit simulation are presented. For all simulations performed in the four technologies studied, agreement

6 34 G.I. Wirth et al. / Microelectronics Reliability 48 (2008) E-14 1E-10 Spice Simulation Detailed Model Simple Model Q C (C) 1E-15 T D (s) 1E-11 Spice Simulation Analytical Model 1E-16 1E-13 1E-12 1E-11 1E-10 τ α (s) Fig. 5. Minimum charge Q C versus collection time constant s a for the injected transient current just capable of inducing a SET at the output of a 2-input nand gate with fan-out 1 in the 0.10 lm technology. Squares are results from Spice circuit simulation. Circles are analytical model results after detailed Eq. (6). Triangles are analytical model results after simple Eq. (7). 1E-12 1E-13 1E-12 1E-11 1E-10 τ α (s) Fig. 6. Transient pulse duration (width) T D versus collection time constant s a for the injected transient current capable of inducing a SET of amplitude V DD at the output of an inverter with fan-out 2 in the 0.13 lm technology. Squares are results from Spice circuit simulation. Circles are results after analytical model Eq. (8). between circuit simulation and analytical model equations was within 20% or better. Fig. 5 compares simulation results to model equations for a 2-input nand gate with fan-out equal to 1 in the 0.10 lm technology node. All transistors are minimum size. Both inputs are at logical 0. The particle strike is assumed to occur at the drain of the n-transistor connected to the output node. The struck transistor is in the off-state. The effective resistance R of the pull-up path is 8.1 kx. The effective capacitive loading C lumped onto the output node is 0.45 ff. Good agreement between model and Spice simulation is found. For fast transients (s a much smaller than RC) at a given logical gate and fan-out, Q C depends weakly on the state of the gate inputs. In this case Q C corresponds approximately to the charge amount needed to initially charge the node capacitance. However, for slower transients (s a much greater than RC), Q C depends strongly on the state of gate inputs. This is because the change in current that flows through open paths to V DD or ground. For instance, for a particle strike with s a = 80 ps at the me 2-input NAND gate shown in Fig. 5, if one of the gate inputs is at logical 1 instead of both of them at logical 0, Q C decreases from 5.9 fc to 3.2 fc. This happens because two conducting p-transistors in parallel show half the resistance of a single one conducting. Next, the duration of a SET induced by a particle hit that deposits a charge greater than Q C is evaluated. The transient pulse duration or width T D is defined as the time during which the voltage change (perturbation) at the node is greater than V DD /2. Fig. 6 shows the comparison between model prediction as given by (8) and circuit simulation results for an inverter in the 130 nm technology node. Inverter input is at logical 1 and fan-out is 2. The particle strike is assumed to occur at the drain of the p-transistor in the off-state. The effective resistance R of the pull-down path is 8.2 kx. The effective capacitive loading C lumped onto the output node is 0.70 ff. All transistors are minimum size. Again, good agreement between model and Spice simulation is found. The effective capacitance C is the sum of all parasitic capacitances lumped at the node, including interconnect, drain junction and the capacitive loading due to the logic gates driven by the struck node. The effective resistance R is computed on a pre-characterization step. For n-transistors, it was computed as the mean value of the channel dc resistance for gate voltage equal to V DD and a drain source voltage exponentially decaying from V DD to zero, with the source terminal connected to ground. For p-transistors, it was computed as the mean value of the channel dc resistance for the gate terminal connected to ground and a source drain voltage exponentially decaying from V DD to zero, with the source terminal connected to V DD.Ithasto be done only once for the fabrication process of interest. Once the effective resistance R for each transistor type (n or p) in the process technology of interest has been determined, the effective resistance R of transistors with different geometries is determined by multiplication by the W/L ratio of the actual transistors. The effective resistance of the pullup and pull-down paths of the different gates is then computed as a series-parallel resistance association. Concerning the validity of model equations, it is known that modeling the charge deposition mechanism by a double exponential current pulse as given by (1) can lead to unrealistic values for the peak transient voltage at the struck node. If unphysical values are chosen for the parameter pair I 0 and s a, it can lead to voltages well above V DD or well bellow ground. In this case (5) and (9) will also lead to unrealistic values for the peak transient voltage. However, if physically consistent values for I 0 and s a are set,

7 G.I. Wirth et al. / Microelectronics Reliability 48 (2008) Fig. 7. SET propagation in a three-bit adder. The particle hit is assumed to occur at the inverter labeled inv3. Table 1 SET with T D = 120 ps at a three-bit adder inv3 nand1 nand6 inv9 nor4 nand7 Spice Model Table 2 SET with T D = 90 ps at a three-bit adder inv3 nand1 nand6 inv9 nor4 nand7 Spice Model c2 c2 the analytical model equations will lead to results conform to the ones obtained by circuit simulation. Next, the model for transient pulse propagation was validated by comparing the results obtained using (10) (13) to Spice level circuit simulation in the four different technology nodes. The results obtained for an energetic particle hit at an internal node of a 3-bit adder test circuit in the 0.10 lm technology are presented. For this technology, the parameter k in (10) (13) is equal to 2. The particle hit is assumed to occur at the drain of the transistor in the off state in the inverter labeled inv3 (see Fig. 7). Tables 1 and 2 compare Spice simulation results to model prediction, as given by (10) (13). The first line in each table shows SET duration (in ps) at the output of each gate, as obtained by Spice simulation. The second line shows model results, also in picoseconds. Table 1 shows the results for a SET with duration T D = 120 ps caused by a particle hit at inv3. Pulse duration is attenuated as it propagates towards the output labeled c2. The model correctly predicts that the pulse reaches the output. Table 2 shows the result for a SET with T D = 90 ps at the me inverter. The model correctly predicts that the pulse is filtered out (electrically masked) and does not reach output c2. For the evaluation of model computational efficiency, the machine execution times for the simulations ran to obtain the data shown in Tables 1 and 2 may be compared. Model computations and circuit simulations ran in a Sun- Blade1000 workstation with a 900 MHz UltraSparcIII+ processor, 4GB of main memory and 3GB of swap. Considering the evaluation of energetic particle hits at an internal node of the simple 3-bit adder, the Hspice simulations spent more than 10 seconds (user time), while the analytical evaluation spent less than 10 ms (user time). This corresponds to a speedup of more than 1000 times (three orders of magnitude). All our experimental results obtained from case studies did show a reduction in analysis time of at least three orders of magnitude. Please remember that the determination of the minimum charge to generate a SET using solely circuit simulation, without the help of a modeling tool, is a trial and error process. In the evaluation of the speed up only the run time of the simulation that leads to the minimum charge is considered. Hence, in practical situations the speed up may be much greater. The analytical modeling approach is also consistent with technology scaling. As devices dimensions are scaling down, both nodal capacitance C and supply voltage V DD decrease. As a consequence the minimum charge needed for SET generation also decreases. This can be clearly seen from Eq. (7). Decreasing both C and V DD, the minimum charge needed to induce a SET is seen to decrease. Please note that if V DD decreases the transient amplitude V peak needed to cause a SET also decreases. This behavior predicted by the analytical model is in line with experimental data. With decreasing device dimensions, lower energy particles may induce single event transients [16]. Furthermore, as device dimensions are scaling down, SETs may propagate easily through the logic chain and be latched at a memory element, causing a computation error. Scaling down device dimensions usually leads to faster gates, i.e. with lower propagation delay (tp). Hence, SETs are easily propagated through the logic chain, with less electrical masking, as can be seen from Eqs. 10,11,13. This behavior was verified by simulation of different technology nodes, and is also in line with device simulation and experimental data [16 19]. 5. Conclusion An accurate and computationally efficient analytical model for the evaluation of integrated circuit sensitivity to single event upset (SEU) is presented. The model allows the rapid determination of the sensitivity of any MOS circuit, without the need to run circuit level (Spice-like)

8 36 G.I. Wirth et al. / Microelectronics Reliability 48 (2008) simulations. Both single event transient generation and its propagation through circuit logic stages are characterized and modeled. Model derivation is in strong relation with circuit electrical behavior and is consistent with technology scaling. The model allows the evaluation of the critical charge Q C needed to induce a SET at a given node, as well as the duration of a SET induced by a particle hit that deposits a charge greater than Q C. This makes the model suitable for implementation into CAD-Tools for automated evaluation of MOS circuit sensitivity to single event upsets and failure rate. From the comparison between model and circuit simulation results, it can be concluded that the simple analytical model provides results equivalent to those obtained when the SET mechanism is evaluated using standard circuit simulation techniques. The model is consistent with technology scaling. References [1] Calvin T, Vargas F, Nicolaidis M, Velazco R. A low-cost highly reliable SEU-tolerant SRAM: prototype and test results. IEEE Trans Nucl Sci 1995;42: [2] Palau J, Calvet M, Dodd P, Sexton F, Roche P. Contribution of device simulation to SER understanding. In: 41st IEEE Int Reliab Phys Symp Dallas Texas, p [3] Palau J, Hubert G, Coulie K, Sagnes B, Calvet M. Device simulation study of the SEU sensitivity of SRAMs to ion tracks generated by nuclear reactions. IEEE Trans Nucl Sci 2001;48: [4] Castellani-Coulié K, Palau J, Hubert G, Calvet M, Dodd P, Sexton F. Various SEU conditions in SRAM studied by 3-D device simulation. IEEE Trans Nucl Sci 2001;48: [5] Ziegler JF. Terrestrial cosmic rays. IBM J R& D 1996;40(1): [6] Messenger GC. Collection of charge on junction nodes from ion tracks. IEEE Trans Nucl Sci 1982;NS-29: [7] Srinivan GR. Modeling the cosmic-ray-induced soft-error rate in ICs: an overview. IBM J R&D 1996;40(1): [8] Sonza Reorda M, Violante M. Efficient analysis of single transients. J Systems Architect 2004; [9] Cha H, Rudnick EM, Patel JH, Iyer RK, Choi GS. A gate-level simulation environment for alpha-particle-induced transient faults. IEEE Trans Comput 1996;45: [10] Shivakumar P, Kistler M, Keckler SW, Burger D, Alvisi L. Modeling the effect of technology trends on the soft error rate of combinational logic. In: Int conf on dependable systems and networks 2002 proceedings. IEEE Comput Soc; p [11] Eaton P, Mavis D, Avery K, Sibley M, Gadlage M, Turfingler T. SET Pulsewidth measurements using a variable temporal latch technique. IEEE Trans Nucl Sci 2004;51: [12] Weste N, Eshraghian K. Principles of CMOS vlsi design: a systems perspective. Addison-Wesley; [13] Bellido-Diaz MJ, Juan-Chico J, Acosta AJ, Valencia M, Huertas JL. Logical modeling of delay degradation effect in static CMOS gates. IEE Proc-Circuits Devices Syst 2000;147(2): [14] [15] [16] Fleetwood D, Winokur Peter S, Dodd Paul E. An overview of radiation effects on electronics in the space telecommunications environment. Microelectron Reliab 2000;40: [17] Baumann R. The impact of technology scaling on soft-error rate performance and limits to the efficacy of error correction electron devices meeting IEDM 02 Digest of papers 2002: [18] Adell P, Schrimpf R, Cirba C, Holman W, Zhu X, Barnaby H, Mion O. Single event transient effects in a voltage reference. Microelectron Reliab 2005;45: [19] Dodd P, Massengill W. Basic mechanisms and modeling of singleevent upset in digital microelectronics. IEEE Trans Nucl Sci 2003; 50: