Modeling high-speed SiGe-HBTs with HICUM/L2 v2.31

Size: px
Start display at page:

Download "Modeling high-speed SiGe-HBTs with HICUM/L2 v2.31"

Transcription

1 Modeling high-speed SiGe-HBTs with HICUM/L2 v2.31 A. Pawlak, M. Schroter, A. Mukherjee, J. Krause Chair for Electron Devices and Integrated Circuits (CEDIC) Technische Universität Dresden, Germany 12th HICUM Workshop, Newport Beach, CA (USA), 212 MS 1

2 Outline Introduction HICUM equivalent circuit Transfer current Mobile charges Vertical NQS-effects Lateral NQS-effect Noise modeling Self-heating Experimental results MS 2

3 Introduction Introduction Experimental results... from DOTFIVE project (3 different process generations of 3 different technology partners) from characterizing other process types (production, high-voltage) => observation of a variety of physical effects some effects were difficult to describe with physics-based model parameters with existing v2.24 => motivation for extension to v2.31 heavy use of BTE, HD, DD device simulation for model development => final verification always on experimental results => this presentation: overview and details on v2.31 extensions MS 3

4 HICUM equivalent circuit HICUM equivalent circuit, Q BCx B Q js,, Q BCx R Bx i jsc i jbcx QdS B * S i TS C rbi R* bi C su C i jbci B Q jci R su Q jei S intrinsic transistor R Cx Q i r AVL i T Qf C thermal network ΔT j T C BEpar1 i jbep C BEpar2 Q jep i BEtp i jbei E R E i BEti P R th C th V nc noise correlation E V nb vertical NQS effects Q f,nqs I nc = 2qI T 1S. V nc I nb = 2qI jbei 1S. V nb Q f,qs τ f α Qf R=τ f 2 T b1 =1+jωτ f B f (2α qf -α IT ) noiseless intrinsic T b2 =jωτ f α IT T b1 V nb T b2 V nc transistor 1S. V nc i T,qs τ f V C1 V C2 τ f α IT V C1 τ f i T,nqs =V C2 α IT 3 R=τ f MS 4

5 Transfer current Transfer current... in HICUM is based on the GICCR From 1D drift-diffusion-transport equation: V BEi V BCi exp V T exp V T I T = c l W h j h v h g pdx Weight functions h j and h v are 1 in the 1D case, c is a bias independent constant. Weight function h g reads h g ( x) = 2 μ nr n ir, with "r" as reference region 2 μ n ( x)n i ( x) Reference region in HICUM is the neutral base: h k = 2 μ n ( x B )n i ( xb ) px ( ) dx 2 k μ n ( x)n i ( x) px ( ) dx k k represents the various regions in the transistor MS 5

6 Transfer current Transfer current related charge Actual charge in the transistor is divided into zero-bias, depletion and mobile charge component: Q p = qa E px ( ) dx = Q p + ΔQ j + ΔQ m Transfer current expression from GICCR: with weighted hole charge c 1 I T = exp exp = i Tf i Tr Q pt V BEi and weighted mobile charge (h f newly introduced in v2.3) V T V BCi =, Q rt = τ r i Tr => Transfer current is directly related to charges defined from small- and large-signal behavior V T Q pt = Q p + h jei Q jei + h jci Q jci + Q ft + Q rt ΔQ j Q ft h f τ f i Tf + h fe ΔQ Ef + ΔQ Bf + h fc ΔQ Cf MS 6

7 Transfer current h g GICCR allows taking into account material composition Si BJT Doping (cm 3 ) Low-current weight factors h g SiGe HBT h Si SiGe jei h jci 1 2 h jei h jci h jei.2 1. h jci Doping (cm 3 ) x (µm) x (µm) h g h f,h fb 1 21 h 1 h 2 fc fe h fc x (µm) Doping (cm 3 ) High-current weight factors Si SiGe h fe h fc h f.98 5 h fb (base as reference region) h g h fe h f,h fb x (µm) Doping (cm 3 ) MS 7

8 Transfer current Normalized transconductance g m /(I C /V T ) can be used to identify device non-ideality and to compare technologies experimental observation: drop in normalized transconductance already at low to medium injection for some technologies. experimental data 1D device simulation 1 1 g m V T /I C f T /f max =7/1 GHz f T /f max =25/3 GHz f T /f max =3/5 GHz.75 HICUM/L2 v2.2 HICUM/L2 v J C (ma/µm 2 ) g m V T /I C no Ge Box Ge Weak Ge gradient Strong Ge gradient J C (ma/µm 2 ) cannot be described with simple (bias independent) reverse Early voltage models From 1D device simulation: effect is directly related to Ge grading in BE-SCR => explicitly included in v2.3:, exp( u) 1 h jei = h jei u = a u hjei ( 1 ( V BEi V DEi ) z Ei) MS 8

9 Transfer current Transconductance at medium injection Stronger reduction of g m /(I C /V T ) could not be described with meaningful Q p values Need to keep physics-based value for Q p for accurate modeling of internal base (sheet) resistance => extract Q p from tetrodes rather than from transfer current. For graded Ge, weighted mobile charge is much larger than actual mobile charge (mostly concentrated in neutral base) => need to introduce h f : g m *V T /I C Q ft = h f τ f i Tf + h fe ΔQ Ef + ΔQ Bf + h fc ΔQ Cf.6 1D Device.5 h =3.9 f.4.7 h f =1.8 V (V) BE.9 1 => strongly improves g m modeling at medium bias Q min, Q min,t (fc) grad, Q min grad, Q min,t box, Q min box, Q min,t J (ma/µm 2 ) C MS 9

10 Temperature dependence of new weight factors... due to bandgap differences h jei also incl. movement of SCR boundaries.1 Transfer current 1 ΔV gbe V T h jei ( T) h jei ( T ) T ζ vgbe = exp 1 T, h jei a hjei T a hjei ( T) = a hjei ( T ) Medium-current weight factor High-current weight factor ΔV gbe V T ζ hjei T h f ( T) h f ( T ) T = exp 1 h fec (, ) ( T) = h fec, ( ) T V gb T V gec (, ) ( ) exp T V T T h f, h fe T ( C) Experimental results T ( C) 2 h f h fe MS 1

11 Transfer current Results Physics-based extensions in v2.3 and v2.31 Material composition related effects modeled explicitly by physics-based equations Takes into account temperature effects due to different bandgap values => Accurate transfer current modeling by GICCR with physics-based charges, weight factors, and parameters device simulation GICCR ideal (classical sol.) I T (ma) relative error (%) V B E (V) => New version has been successfully applied to several recent technologies MS 11

12 Mobile charges Mobile charges forward active bias mobile charge in HICUM corresponding transit time follows: Q f ccritical current I CK Q f = τ f + ΔQ Ef + ΔQ fh τ f = τ f + Δτ Ef + Δτ fh = i Tf τ f di T ' added parameter for better fitting to field dependence of mobility. τ f (ps) I /I C CK.8 Δτ fh Δτ Ef τ v ceff r Ci x+ x 2 + a I CK ickpt = v ceff V lim δ CK 1 δ CK 2 default δ CK =2 parameter allows better fitter for, e.g., pnp I CK (A) δ = 2. (default) CK δ = 1 (e.g. holes) CK V (V) CE MS 12

13 BC barrier effect BC barrier effect In HICUM v2.3, the collector heterojunction barrier effect is modeled. Barrier effect becomes more pronounced in advanced SiGe HBT generations Formation of barrier in conduction band strongly related to Kirk-effect in well-designed HBT => more rapid increase of transit time beyond I CK V C (V) ΔV cbar 15 1 I C.1 x.3 jc x (µm) 5 Ge (%) 1/(2πf T ) norm f T /f max =25/3 GHz f T /f max =3/5 GHz.5 1 J /J C CK Influence of heterojunction position on barrier effect Close to BC-junction -> related to Kirk-effect Far in the collector -> at too high (i.e. irrelevant) currents 1/(2πf T ) (ps) HBT, Δx Ge,C HBT, Δx Ge,C =3 nm HBT, Δx Ge,C =16 nm J (ma/µm 2 ) C MS 13

14 BC barrier effect Modeling the BC barrier effect Onset of barrier effect is still given by I CK (for a "well-designed" DHBT) barrier voltage (from bias dependent conduction band barrier): 2 ΔV cb V cbar i Tf I CK = exp with i bar = i bar + i2 bar + a cbar I cbar ΔV Cb (mv) simulation model J (ma/µm 2 ) C τ f (ps) τ f (ps) 2 15 V cbar I C /I CK τ f (ps) 15 1 a cbar New parameters: V cbar, I cbar, a cbar 5 I cbar I /I C CK I /I C CK MS 14

15 BC barrier effect New mobile charge formulation at high injection Include barrier related base and collector charge terms explicitly: Q f h, = ΔQ Ef + ΔQ Bf, b + ΔQ Bf c +, ΔQ Cf, c Q fh, c Barrier related base charge term calculated by a bias dependent barrier voltage. ΔQ Bf b ΔV C, = τ Bfvs i Tf exp V T 2 15 simul τ Bf,b τ fh,c with already existing τ Bfvs = ( 1 f τhc )τ hcs Δτ fh (ps) 1 τ Bf,b +τ fh,c Kirk-effect related transit times are "delayed" by the formation of the barrier: 5 ΔQ fh c, τ hcs i Tf w 2 ΔV C V Cbar = exp V T J C (ma/µm 2 ) => very accurate and flexible, and still backwards compatible MS 15

16 Vertical NQS-effects Vertical NQS-effects HICUM includes mobile charge and transfer current related NQS effects => modeled using polynomial approximation and separate networks charge delay and input admittance transfer current delay and transconductancea Q f,nqs V C1 Q f,qs i T,qs τ V C2 f τ α R=τ f τ f f α Qf IT V C1 τ f i T,nqs =V C2 α IT 3 R=τ f Mag(Y 11 /Y 11 (f )) simulation mag simulation phase no NQS 2 inverted polynomial Phase(Y 11 ) ( ) Mag(Y 21 /Y 21 (f )) 1.9 simulation mag simulation phase no NQS inverted polynomial Phase(Y 21 ) ( ) f/f T f/f T => Good agreement in small-signal and large-signal simulation MS 16

17 Lateral NQS-effect Lateral NQS-effect... caused by high-frequency emitter current crowding theoretical solution only for small-signal case (and negligible DC current crowding) => simple capacitance parallel to R Bi : C RBi = f CRBi ( C jei + C jci + C dei + C dci ) Verilog-A only allows adjunct network with charge definition: Q RBi = C RBi V RBi or Q RBi = f CRBi ( Q jei + Q jci + Q dei + Q dci )? latter leads to strong overestimation of the charge, current and admittance present solution ONLY valid for small-signal operation and not too high frequencies Do NOT use for large-signal operation!! => still under investigation Feedback from circuit design? Q RBi (fc) C RBi B* R Bi B V RBi Q RBi =C RBi V RBi Q RBi =f CRBi (Σ Q) J C (ma/µm 2 ) MS 17

18 Lateral NQS-effect Problems with implementation of lateral NQS-effect... caused by undesired derivatives small-signal form of Q RBi = C RBi V RBi in Verilog-A leads to dq RBi dt dc ( RBi V RBi ) dv RBi = = C dt RBi dt + dc RBi dv RBi V RBi dt dv RBi theoretical solution => undesired derivative from Verlog-A implementation constraints Also: undesired derivatives result in large overhead of compiled code since dc RBi /dv RBi internally requires the calculation of the derivatives of all nonlinear capacitances (incl. for C dei and C dci ) alternatives are presently under investigation not present in smallsignal theory MS 18

19 Noise modeling Noise modeling New noise correlation model in v2.31 is valid at all frequencies physically connected to NQS effects => can use same delay time and assoc. parameters V nb noise correlation I nb = 2qI jbei I nc = 2qI T 1S. V nb 2 T b1 =1+jωτ f B f (2α qf -α IT ) noiseless intrinsic T b2 =jωτ f α IT T b1 V nb T b2 V nc transistor V nc 1S. V nc 1S. V nc NF min (db) HICUM meas no corr HD BTE RC delay f (GHz) Additional flicker noise contribution for emitter resistance R E 2 K I A fre E fre = f I re 4kT R E MS 19

20 Self-heating Self-heating intra-device thermal coupling (self-heating) described by single-pole network dissipated power: P = f(i T, V CEi, I BE, I BC, R B, R E, R CX, I AVL ) Based on observations of experimental data and solution of heat transport equation: P R th ΔT j C th T T R th ( T) = R th ( T ) ζ Rth T R th (K/mW) w E =13nm w E =1.5µm model R th (K/mW) Parameter extraction.5 Numerical simulation T ( C) 1.85 measured model T ( C) Temperature node also allows modeling of inter-device thermal coupling MS 2

21 Summary on V2.31 extensions Summary on V2.31 extensions list of new model parameters and flags Parameter Def. Description δ CK 2 Fitting factor for I CK a hjei Parameter describing the slope of h jei (V BE ) r hjei 1 Smoothing parameter for h jei (V BE ) at high voltage. ΔV gbe Bandgap difference between base and BE-junction, used for h jei and h f. ζ hjei 1 Temperature coefficient for a hjei. ζ VgBE 1 Temperature coefficient for h jei. h f 1 Weight factor for the low current minority charge. V cbar Barrier voltage, = turns the model off. a cbar.1 Smoothing parameter for barrier voltage. i cbar Normalization parameter, = turns the model off. ζ rth Temperature coefficient for R th FLCONO High-frequency noise correlation flag Kf re R E flicker noise coefficient Af re 2 R E flicker noise exponent factor TYPE 1 Flag for npn (1) and pnp (-1) transistors MS 21

22 Experimental results Experimental results Technologies shown here ST B9MW with f T /f max = 2/3 GHz, A E = 1x.13x4.87 μm 2 IHP SGB25V with f T /f max = 75/95 GHz, A E = 1x.64x12.68 μm 2 IHP 5GHz with f T /f max = 3/5 GHz, A E = 8x.12x.96 μm 2 => Comparison over large bias, temperature, and geometry range MS 22

23 Experimental results I C, I B (A) I C, I B (A) ST B9MW technology Forward gummel characteristics for [-4, 27, 75, 125] C V BE (V) V BE (V).9 Forward current gain Forward current gain I C, I B (A) I C, I B (A) V BE (V) V (V) BE => very good agreement over wide bias and T range Forward current gain Forward current gain MS 23

24 Experimental results 3 ST technology (cont d) transit frequency for [-4, 27, 75, 125] C. 3 f T [GHz] 2 1 f T [GHz] I [ma/µm 2 ] C I C [ma/µm 2 ] 3 3 f T [GHz] 2 1 f T [GHz] I [ma/µm 2 ] C I C [ma/µm 2 ] => very good agreement over wide bias and T range MS 24

25 Experimental results 4 ST technology (cont d) Maximum oscillation frequency for [-4, 27, 75, 125] C. 3 f max [GHz] 2 f max [GHz] I /A [ma/µm 2 ] C E I C /A E [ma/µm 2 ] 3 3 f max [GHz] 2 1 f max [GHz] I /A [ma/µm 2 ] C E I /A [ma/µm 2 ] C E => good agreement over wide bias and T range MS 25

26 Experimental results 1 ST technology (cont d) Normalized transconductance for [-4, 27, 75, 125] C. 1 g m *V T /I C.5 g m *V T /I C.5 g m *V T /I C V [V] BE g m *V T /I C V [V] BE V BE [V] V BE [V] => very good agreement over wide bias and T range MS 26

27 Experimental results IHP SGB25V technology Temperature dependence of forward Gummel characteristics 1 meas model T J C, J B [ma/µm 2 ] V [V] BE => very good agreement over wide bias and T range MS 27

28 Experimental results IHP SGB25V technology (cont d) geometry scaling of transit frequency f T (GHz) meas model meas J (ma/µm 2 ) C J C (ma/µm 2 ) model 6 A A E = 1x.64x12.68 μm 2 E =1x.64x27.8 μm 2 f T (GHz) 4 f T (GHz) meas model 2 A E =1x.98x12.68 μm J C (ma/µm 2 ) => good agreement over geometry and wide bias range MS 28

29 Experimental results IHP 5GHz technology Temperature dependence of forward Gummel characteristics and transit frequency J C, J B [ma/µm 2 ] meas model f T [GHz] T = 15 C T = 27 C T = 5 C T = 75 C T = 1 C model V [V] BE J C [ma/µm 2 ] => very good agreement over wide bias and geometry range MS 29

30 Experimental results U (db) V BE =.75 V V BE =.8 V V BE =.9 V model power gain MSG (db) 1 1 f (GHz) IHP 5GHz technology (cont d) V BE =.75 V V BE =.8 V V BE =.9 V model 1 1 f (GHz) stability factor not stable below peak f T => reasonable agreement over frequency and wide bias range k meas model k V BE =.75 V V BE =.8 V V BE =.9 V model 1 1 f (GHz) J C (ma/µm 2 ) MS 3

31 Experimental results IHP 5GHz technology (cont d) Large-signal results for A E =.12 x 1μm 2 (4 in parallel) harmonic f = 8GHz 2 J C = 2.5mA/µm 2 V CE =1.3V P out (dbm) nd 3 rd P (dbm) in => very good agreement for dynamic characteristics MS 31

32 Summary and conclusions Summary and conclusions observation of various physical effects both in advanced technologies (during DOTFIVE project) and other technologies measured in our lab HICUM/L2 v2.31 extensions BC barrier effect & improved description of material composition in transfer current and g m BC barrier effect in mobile charge temperature dependence of new parameters and of thermal resistance HF noise correlation model valid up to very high frequencies miscellaneous: flicker noise addition in RE, optimized NQS effect VA implement., pnp flag access to variety of (production) technologies for modle verification is very important => otherwise difficult to make a model widely applicable throughout industry need better measurement capability for small- and large-signal model verification Goal for InP HBTs: extend HICUM/L2 add specific physical effects (as determined to be relevant) enable geometry scaling => circuit optimization and statistical modeling generate scalable HICUM/L and distributed HICUM/L4 automatically from L2 => offer unified and flexible HBT modeling strategy MS 32

33 Summary and conclusions Acknowledgments IHP, Frakfurt/Oder, Germany ST Microelectronics, Grenoble, France EU CATRENE project RF2THzSiSoC MS 33

HICUM / L2. A geometry scalable physics-based compact bipolar. transistor model

HICUM / L2. A geometry scalable physics-based compact bipolar. transistor model HICUM HICUM / L2 A geometry scalable physics-based compact bipolar transistor model M. Schroter, A. Pawlak, A. Mukherjee Documentation of model version 2.32 August, 2013 M. Schroter 16/5/14 1 HICUM List

More information

HICUM release status and development update L2 and L0

HICUM release status and development update L2 and L0 HICUM release status and development update L2 and L0 M. Schröter, A. Pawlak 17th HICUM Workshop Munich, Germany May 29th, 2017 Contents HICUM/L2 in a nutshell Release of HICUM/L2 version 2.4.0 Strong

More information

Accurate transit time determination and. transfer current parameter extraction

Accurate transit time determination and. transfer current parameter extraction Accurate transit time determination and transfer current parameter extraction T. Rosenbaum, A. Pawlak, J. Krause, M. Schröter Chair for Electron Devices and Integrated Circuits (CEDIC) University of Technology

More information

HICUM Parameter Extraction Methodology for a Single Transistor Geometry

HICUM Parameter Extraction Methodology for a Single Transistor Geometry HICUM Parameter Extraction Methodology for a Single Transistor Geometry D. Berger, D. Céli, M. Schröter 2, M. Malorny 2, T. Zimmer 3, B. Ardouin 3 STMicroelectronics,, France 2 Chair for Electron Devices

More information

Nonlinear distortion in mm-wave SiGe HBTs: modeling and measurements

Nonlinear distortion in mm-wave SiGe HBTs: modeling and measurements Nonlinear distortion in mm-wave SiGe HBTs: modeling and measurements P. Sakalas $,#, A. Pawlak $, M. Schroter $ $ CEDIC, Technische Universität Dresden, Mommsenstrasse 13, Germany # FRLab. Semiconductor

More information

Working Group Bipolar (Tr..)

Working Group Bipolar (Tr..) Department of Electrical Engineering and Information Technology Institute of Circuits and Systems Chair for Electron Devices and Integrated Circuits Working Group Bipolar (Tr..) I T parameter extraction

More information

Status of HICUM/L2 Model

Status of HICUM/L2 Model Status of HICUM/L2 Model A. Pawlak 1), M. Schröter 1),2), A. Mukherjee 1) 1) CEDIC, University of Technology Dresden, Germany 2) Dept. of Electrical and Computer Engin., University of Calif. at San Diego,

More information

Regional Approach Methods for SiGe HBT compact modeling

Regional Approach Methods for SiGe HBT compact modeling Regional Approach Methods for SiGe HBT compact modeling M. Schroter 1),2) and H. Tran 2) 1) ECE Dept., University of California San Diego, La Jolla, CA, USA 2) Chair for Electron Devices and Integr. Circuits,

More information

2 nd International HICUM user s meeting

2 nd International HICUM user s meeting 2 nd International HICUM user s meeting Monterey, September 22 D. Berger, D. Céli, T. Burdeau STMicroelectronics,, France esults HICUM status in ST Implementation of HICUM model equation in an in-house

More information

A new transit time extraction algorithm based on matrix deembedding techniques

A new transit time extraction algorithm based on matrix deembedding techniques 27 A new transit time extraction algorithm based on matrix deembedding techniques C. Raya, N. Kauffmann, D. Celi, T. Zimmer State of art Method Result Introduction T F importance: - T F physical information

More information

HICUM/L2 version 2.2: Summary of extensions and changes

HICUM/L2 version 2.2: Summary of extensions and changes HICUM/L2 version 2.2: Summary of extensions and changes M. Schroter Chair for Electron Devices & Integrated Circuits Dept. of Electrical and Computer Engineering (CEDIC) University of Technology Dresden,

More information

HICUM/L2 version 2.21: Release Notes

HICUM/L2 version 2.21: Release Notes HICUM/L2 version 2.21: Release Notes Chair for Electron Devices & Integrated Circuits (CEDIC) University of Technology Dresden, Germany M. Schroter and A. Chakravorty mschroter@ieee.org http://www.iee.et.tu-dresden.de/iee/eb/

More information

About Modeling the Reverse Early Effect in HICUM Level 0

About Modeling the Reverse Early Effect in HICUM Level 0 About Modeling the Reverse Early Effect in HICUM Level 0 6 th European HICUM Workshop, June 12-13, 2006, Heilbronn Didier CELI, STMicroelectronics 1/21 D. Céli Purpose According to the bipolar models,

More information

Charge-storage related parameter calculation for Si and SiGe bipolar transistors from device simulation

Charge-storage related parameter calculation for Si and SiGe bipolar transistors from device simulation Charge-storage related parameter calculation for Si and SiGe bipolar transistors from device simulation M. Schroter ),) and H. Tran ) ) ECE Dept., University of California San Diego, La Jolla, CA, USA

More information

Non-standard geometry scaling effects

Non-standard geometry scaling effects Non-standard geometry scaling effects S. Lehmann 1), M. Schröter 1),2), J. Krause 1), A. Pawlak 1) 1) Chair for Electron Devices and Integr. Circuits, Univ. of Technol. Dresden, Germany 2) ECE Dept., University

More information

Lecture 38 - Bipolar Junction Transistor (cont.) May 9, 2007

Lecture 38 - Bipolar Junction Transistor (cont.) May 9, 2007 6.72J/3.43J - Integrated Microelectronic Devices - Spring 27 Lecture 38-1 Lecture 38 - Bipolar Junction Transistor (cont.) May 9, 27 Contents: 1. Non-ideal effects in BJT in FAR Reading material: del Alamo,

More information

Methodology for Bipolar Model Parameter Extraction. Tzung-Yin Lee and Michael Schröter February 5, TYL/MS 2/5/99, Page 1/34

Methodology for Bipolar Model Parameter Extraction. Tzung-Yin Lee and Michael Schröter February 5, TYL/MS 2/5/99, Page 1/34 Methodology for Bipolar Model Parameter Extraction Tzung-Yin Lee and Michael Schröter February 5, 1999 TYL/MS 2/5/99, Page 1/34 Outline General Remarks Brief overview of TRADICA Parameter extraction flowchart

More information

A Novel Method for Transit Time Parameter Extraction. Taking into Account the Coupling Between DC and AC Characteristics

A Novel Method for Transit Time Parameter Extraction. Taking into Account the Coupling Between DC and AC Characteristics A Novel Method for Transit Time Parameter Extraction Taking into Account the Coupling Between DC and AC Characteristics Dominique BEGE and Didier CELI STMicroelectronics, 850, rue jean Monnet F-38926 Cedex

More information

13. Bipolar transistors

13. Bipolar transistors Technische Universität Graz Institute of Solid State Physics 13. Bipolar transistors Jan. 16, 2019 Technische Universität Graz Institute of Solid State Physics bipolar transistors npn transistor collector

More information

Didier CELI, 22 nd Bipolar Arbeitskreis, Würzburg, October 2009

Didier CELI, 22 nd Bipolar Arbeitskreis, Würzburg, October 2009 HICUM/L0 v1.2: Application to Millimeter Wave Devices Didier CELI, 22 nd Bipolar Arbeitskreis, Würzburg, October 2009 Outline Purpose ariation of reverse Early effect with the evolution of technologies

More information

Institute of Solid State Physics. Technische Universität Graz. Exam. Feb 2, 10:00-11:00 P2

Institute of Solid State Physics. Technische Universität Graz. Exam. Feb 2, 10:00-11:00 P2 Technische Universität Graz nstitute of Solid State Physics Exam Feb 2, 10:00-11:00 P2 Exam Four questions, two from the online list. Calculator is ok. No notes. Explain some concept: (tunnel contact,

More information

ELEC 3908, Physical Electronics, Lecture 19. BJT Base Resistance and Small Signal Modelling

ELEC 3908, Physical Electronics, Lecture 19. BJT Base Resistance and Small Signal Modelling ELEC 3908, Physical Electronics, Lecture 19 BJT Base Resistance and Small Signal Modelling Lecture Outline Lecture 17 derived static (dc) injection model to predict dc currents from terminal voltages This

More information

ECE-305: Spring 2018 Final Exam Review

ECE-305: Spring 2018 Final Exam Review C-305: Spring 2018 Final xam Review Pierret, Semiconductor Device Fundamentals (SDF) Chapters 10 and 11 (pp. 371-385, 389-403) Professor Peter Bermel lectrical and Computer ngineering Purdue University,

More information

Transistor's self-und mutual heating and its impact on circuit performance

Transistor's self-und mutual heating and its impact on circuit performance Transistor's self-und mutual heating and its impact on circuit performance M. Weiß, S. Fregonese, C. Maneux, T. Zimmer 26 th BipAk, 15 November 2013, Frankfurt Oder, Germany Outline 1. Motivation. Research

More information

Device Physics: The Bipolar Transistor

Device Physics: The Bipolar Transistor Monolithic Amplifier Circuits: Device Physics: The Bipolar Transistor Chapter 4 Jón Tómas Guðmundsson tumi@hi.is 2. Week Fall 2010 1 Introduction In analog design the transistors are not simply switches

More information

Breakdown mechanisms in advanced SiGe HBTs: scaling and TCAD calibration

Breakdown mechanisms in advanced SiGe HBTs: scaling and TCAD calibration Breakdown mechanisms in advanced SiGe HBTs: scaling and TCAD calibration T. Rosenbaum 1,2,3, D. Céli 1, M. Schröter 2, C. Maneux 3 Bipolar ArbeitsKreis Unterpremstätten, Austria, November 6, 2015 1 STMicroelectronics,

More information

Memories Bipolar Transistors

Memories Bipolar Transistors Technische Universität Graz nstitute of Solid State Physics Memories Bipolar Transistors Technische Universität Graz nstitute of Solid State Physics Exams February 5 March 7 April 18 June 27 Exam Four

More information

Semiconductor Device Simulation

Semiconductor Device Simulation motivation and target applications compact model development under conditions relevant for circuit design development of test structures and measurement methods (fast) predicting device performance and

More information

Spring Semester 2012 Final Exam

Spring Semester 2012 Final Exam Spring Semester 2012 Final Exam Note: Show your work, underline results, and always show units. Official exam time: 2.0 hours; an extension of at least 1.0 hour will be granted to anyone. Materials parameters

More information

ELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and Self-Heating

ELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and Self-Heating ELEC 3908, Physical Electronics, Lecture 18 The Early Effect, Breakdown and Self-Heating Lecture Outline Previous 2 lectures analyzed fundamental static (dc) carrier transport in the bipolar transistor

More information

TCAD setup for an advanced SiGe HBT technology applied to the HS, MV and HV transistor versions

TCAD setup for an advanced SiGe HBT technology applied to the HS, MV and HV transistor versions TCAD setup for an advanced SiGe HBT technology applied to the HS, MV and HV transistor versions T. Rosenbaum 1,2,3, D. Céli 1, M. Schröter 2, C. Maneux 3 Bipolar ArbeitsKreis München, Germany, November

More information

Forward-Active Terminal Currents

Forward-Active Terminal Currents Forward-Active Terminal Currents Collector current: (electron diffusion current density) x (emitter area) diff J n AE qd n n po A E V E V th ------------------------------ e W (why minus sign? is by def.

More information

CLASS 3&4. BJT currents, parameters and circuit configurations

CLASS 3&4. BJT currents, parameters and circuit configurations CLASS 3&4 BJT currents, parameters and circuit configurations I E =I Ep +I En I C =I Cp +I Cn I B =I BB +I En -I Cn I BB =I Ep -I Cp I E = I B + I C I En = current produced by the electrons injected from

More information

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2

More information

ECE-342 Test 2 Solutions, Nov 4, :00-8:00pm, Closed Book (one page of notes allowed)

ECE-342 Test 2 Solutions, Nov 4, :00-8:00pm, Closed Book (one page of notes allowed) ECE-342 Test 2 Solutions, Nov 4, 2008 6:00-8:00pm, Closed Book (one page of notes allowed) Please use the following physical constants in your calculations: Boltzmann s Constant: Electron Charge: Free

More information

Thermal Capacitance cth its Determination and Influence on Transistor and Circuit Performance

Thermal Capacitance cth its Determination and Influence on Transistor and Circuit Performance Thermal Capacitance cth its Determination and Influence on Transistor and Circuit Performance Gerhard G. Fischer IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany IHP Im Technologiepark 25 15236

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 1 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.12 Electronic Devices and Circuits Exam No. 1 Wednesday, October 7, 29 7:3 to 9:3

More information

Chapter 2. - DC Biasing - BJTs

Chapter 2. - DC Biasing - BJTs Chapter 2. - DC Biasing - BJTs Objectives To Understand : Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented

More information

Metal-oxide-semiconductor field effect transistors (2 lectures)

Metal-oxide-semiconductor field effect transistors (2 lectures) Metal-ide-semiconductor field effect transistors ( lectures) MOS physics (brief in book) Current-voltage characteristics - pinch-off / channel length modulation - weak inversion - velocity saturation -

More information

Recitation 17: BJT-Basic Operation in FAR

Recitation 17: BJT-Basic Operation in FAR Recitation 17: BJT-Basic Operation in FAR BJT stands for Bipolar Junction Transistor 1. Can be thought of as two p-n junctions back to back, you can have pnp or npn. In analogy to MOSFET small current

More information

Lecture 17 - The Bipolar Junction Transistor (I) Forward Active Regime. April 10, 2003

Lecture 17 - The Bipolar Junction Transistor (I) Forward Active Regime. April 10, 2003 6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 17-1 Lecture 17 - The Bipolar Junction Transistor (I) Contents: Forward Active Regime April 10, 2003 1. BJT: structure and basic operation

More information

Lecture 16 The pn Junction Diode (III)

Lecture 16 The pn Junction Diode (III) Lecture 16 The pn Junction iode (III) Outline I V Characteristics (Review) Small signal equivalent circuit model Carrier charge storage iffusion capacitance Reading Assignment: Howe and Sodini; Chapter

More information

Digital Integrated CircuitDesign

Digital Integrated CircuitDesign Digital Integrated CircuitDesign Lecture 5a Bipolar Transistor Dep. Region Neutral Base n(0) b B C n b0 P C0 P e0 P C xn 0 xp 0 x n(w) b W B Adib Abrishamifar EE Department IUST Contents Bipolar Transistor

More information

BJT Biasing Cont. & Small Signal Model

BJT Biasing Cont. & Small Signal Model BJT Biasing Cont. & Small Signal Model Conservative Bias Design (1/3, 1/3, 1/3 Rule) Bias Design Example Small-Signal BJT Models Small-Signal Analysis 1 Emitter Feedback Bias Design R B R C V CC R 1 R

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

BJT - Mode of Operations

BJT - Mode of Operations JT - Mode of Operations JTs can be modeled by two back-to-back diodes. N+ P N- N+ JTs are operated in four modes. HO #6: LN 251 - JT M Models Page 1 1) Forward active / normal junction forward biased junction

More information

Lecture 35 - Bipolar Junction Transistor (cont.) November 27, Current-voltage characteristics of ideal BJT (cont.)

Lecture 35 - Bipolar Junction Transistor (cont.) November 27, Current-voltage characteristics of ideal BJT (cont.) 6.720J/3.43J - Integrated Microelectronic Devices - Fall 2002 Lecture 35-1 Lecture 35 - Bipolar Junction Transistor (cont.) November 27, 2002 Contents: 1. Current-voltage characteristics of ideal BJT (cont.)

More information

Charge-Storage Elements: Base-Charging Capacitance C b

Charge-Storage Elements: Base-Charging Capacitance C b Charge-Storage Elements: Base-Charging Capacitance C b * Minority electrons are stored in the base -- this charge q NB is a function of the base-emitter voltage * base is still neutral... majority carriers

More information

Investigation of Ge content in the BC transition region with respect to transit frequency

Investigation of Ge content in the BC transition region with respect to transit frequency Investigation of Ge content in the BC transition region with respect to transit frequency P.M. Mans (1),(2), S. Jouan (1), A. Pakfar (1), S. Fregonese (2), F. Brossard (1), A. Perrotin (1), C. Maneux (2),

More information

Investigation of New Bipolar Geometry Scaling Laws

Investigation of New Bipolar Geometry Scaling Laws Investigation of New Bipolar Geometry Scaling Laws D. CELI 20 th Bipolar Arbeitskreis Munich, October 2007 Purpose Robust and high-performance RF circuit design need optimization of transistors. Therefore

More information

Chapter 2 - DC Biasing - BJTs

Chapter 2 - DC Biasing - BJTs Objectives Chapter 2 - DC Biasing - BJTs To Understand: Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented

More information

MEXTRAM (level 504) the Philips model for bipolar transistors

MEXTRAM (level 504) the Philips model for bipolar transistors MEXTRAM (level 504) the Philips model for bipolar transistors Jeroen Paasschens, Willy Kloosterman, Ramses van der Toorn FSA modeling workshop 2002 Philips Electronics N.V. 2002 apple PHILIPS Philips Research

More information

Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model. April 8, 2003

Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model. April 8, 2003 6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 16-1 Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model April 8, 2003 Contents: 1. I-V characteristics (cont.) 2. Small-signal

More information

VBIC. SPICE Gummel-Poon. (Bipolar Junction Transistor, BJT) Gummel Poon. BJT (parasitic transistor) (avalance mutliplication) (self-heating)

VBIC. SPICE Gummel-Poon. (Bipolar Junction Transistor, BJT) Gummel Poon. BJT (parasitic transistor) (avalance mutliplication) (self-heating) page 4 VBC SPCE Gummel-Poon (Bipolar Junction Transistor, BJT) 1970 Gummel Poon GP BJT (parasitic transistor) (avalance mutliplication) (self-heating) (qusai-saturation) Early GP BJT (Heter-junction Bipolar

More information

Holes (10x larger). Diode currents proportional to minority carrier densities on each side of the depletion region: J n n p0 = n i 2

Holes (10x larger). Diode currents proportional to minority carrier densities on each side of the depletion region: J n n p0 = n i 2 Part V. (40 pts.) A diode is composed of an abrupt PN junction with N D = 10 16 /cm 3 and N A =10 17 /cm 3. The diode is very long so you can assume the ends are at x =positive and negative infinity. 1.

More information

12. Memories / Bipolar transistors

12. Memories / Bipolar transistors Technische Universität Graz Institute of Solid State Physics 12. Memories / Bipolar transistors Jan. 9, 2019 Technische Universität Graz Institute of Solid State Physics Exams January 31 March 8 May 17

More information

Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime

Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime Outline The Bipolar Junction Transistor (BJT): structure and basic operation I V characteristics in forward active regime Reading Assignment:

More information

Bipolar junction transistor operation and modeling

Bipolar junction transistor operation and modeling 6.01 - Electronic Devices and Circuits Lecture 8 - Bipolar Junction Transistor Basics - Outline Announcements Handout - Lecture Outline and Summary; Old eam 1's on Stellar First Hour Eam - Oct. 8, 7:30-9:30

More information

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

The Mextram Bipolar Transistor Model

The Mextram Bipolar Transistor Model Date of issue: March 12, 2012 The Mextram Bipolar Transistor Model level 504.10.1 R. van der Toorn, J.C.J. Paasschens, and W.J. Kloosterman Mextram definition document NXP Semiconductors March 12, 2012

More information

BJT Biasing Cont. & Small Signal Model

BJT Biasing Cont. & Small Signal Model BJT Biasing Cont. & Small Signal Model Conservative Bias Design Bias Design Example Small Signal BJT Models Small Signal Analysis 1 Emitter Feedback Bias Design Voltage bias circuit Single power supply

More information

figure shows a pnp transistor biased to operate in the active mode

figure shows a pnp transistor biased to operate in the active mode Lecture 10b EE-215 Electronic Devices and Circuits Asst Prof Muhammad Anis Chaudhary BJT: Device Structure and Physical Operation The pnp Transistor figure shows a pnp transistor biased to operate in the

More information

Homework Assignment 08

Homework Assignment 08 Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

More information

The Mextram Bipolar Transistor Model

The Mextram Bipolar Transistor Model Date of issue: January 25, 2016 The Mextram Bipolar Transistor Model level 504.12 G. Niu, R. van der Toorn, J.C.J. Paasschens, and W.J. Kloosterman Mextram definition document NXP Semiconductors 2006 Delft

More information

The Devices. Devices

The Devices. Devices The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors

More information

For the following statements, mark ( ) for true statement and (X) for wrong statement and correct it.

For the following statements, mark ( ) for true statement and (X) for wrong statement and correct it. Benha University Faculty of Engineering Shoubra Electrical Engineering Department First Year communications. Answer all the following questions Illustrate your answers with sketches when necessary. The

More information

Lecture 20 - p-n Junction (cont.) October 21, Non-ideal and second-order effects

Lecture 20 - p-n Junction (cont.) October 21, Non-ideal and second-order effects 6.70J/3.43J - Integrated Microelectronic Devices - Fall 00 Lecture 0-1 Lecture 0 - p-n Junction (cont.) October 1, 00 Contents: 1. Non-ideal and second-order effects Reading assignment: del Alamo, Ch.

More information

DATA SHEET. PRF957 UHF wideband transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Mar 01.

DATA SHEET. PRF957 UHF wideband transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Mar 01. DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D1 Supersedes data of 1999 Mar 1 1999 Jul 3 FEATURES PINNING Small size Low noise Low distortion High gain Gold metallization ensures excellent reliability.

More information

DC and AC modeling of minority carriers currents in ICs substrate

DC and AC modeling of minority carriers currents in ICs substrate DC and AC modeling of minority carriers currents in ICs substrate Camillo Stefanucci, Pietro Buccella, Maher Kayal and Jean-Michel Sallese Swiss Federal Institute of Technology Lausanne, Switzerland MOS-AK

More information

Schottky Rectifiers Zheng Yang (ERF 3017,

Schottky Rectifiers Zheng Yang (ERF 3017, ECE442 Power Semiconductor Devices and Integrated Circuits Schottky Rectifiers Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Power Schottky Rectifier Structure 2 Metal-Semiconductor Contact The work function

More information

ECE 305 Fall Final Exam (Exam 5) Wednesday, December 13, 2017

ECE 305 Fall Final Exam (Exam 5) Wednesday, December 13, 2017 NAME: PUID: ECE 305 Fall 017 Final Exam (Exam 5) Wednesday, December 13, 017 This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the ECE policy,

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

Bipolar Junction Transistor (BJT) Model. Model Kind. Model Sub-Kind. SPICE Prefix. SPICE Netlist Template Format

Bipolar Junction Transistor (BJT) Model. Model Kind. Model Sub-Kind. SPICE Prefix. SPICE Netlist Template Format Bipolar Junction Transistor (BJT) Model Old Content - visit altiumcom/documentation Modified by Admin on Sep 13, 2017 Model Kind Transistor Model Sub-Kind BJT SPICE Prefix Q SPICE Netlist Template Format

More information

1 Introduction -1- C continuous (smooth) modeling

1 Introduction -1- C continuous (smooth) modeling 1 Introduction For over 0 years the SPICE Gummel-Poon (SGP) model (Gummel, 1970; Nagel, 1975) has been the IC industry standard for circuit simulation for bipolar junction transistors (BJTs). This is a

More information

Lecture 19 - p-n Junction (cont.) October 18, Ideal p-n junction out of equilibrium (cont.) 2. pn junction diode: parasitics, dynamics

Lecture 19 - p-n Junction (cont.) October 18, Ideal p-n junction out of equilibrium (cont.) 2. pn junction diode: parasitics, dynamics 6.720J/3.43J - Integrated Microelectronic Devices - Fall 2002 Lecture 19-1 Lecture 19 - p-n Junction (cont.) October 18, 2002 Contents: 1. Ideal p-n junction out of equilibrium (cont.) 2. pn junction diode:

More information

EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions

EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 pn Junction p-type semiconductor in

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 21: Bipolar Junction Transistor Administrative Midterm Th 6:30-8pm in Sibley Auditorium Covering everything

More information

Bipolar Junction Transistor (BJT) - Introduction

Bipolar Junction Transistor (BJT) - Introduction Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification

More information

Microelectronic Circuit Design Fourth Edition - Part I Solutions to Exercises

Microelectronic Circuit Design Fourth Edition - Part I Solutions to Exercises Page Microelectronic Circuit esign Fourth Edition - Part I Solutions to Exercises CHAPTER V LSB 5.V 0 bits 5.V 04bits 5.00 mv V 5.V MSB.560V 000000 9 + 8 + 4 + 0 785 0 V O 785 5.00mV or ) 5.V 3.95 V V

More information

Lecture 15 - The pn Junction Diode (I) I-V Characteristics. November 1, 2005

Lecture 15 - The pn Junction Diode (I) I-V Characteristics. November 1, 2005 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 15-1 Lecture 15 - The pn Junction Diode (I) I-V Characteristics November 1, 2005 Contents: 1. pn junction under bias 2. I-V characteristics

More information

The PSP compact MOSFET model An update

The PSP compact MOSFET model An update The PSP compact MOSFET model An update Gert-Jan Smit, Andries Scholten, D.B.M. Klaassen NXP Semiconductors Ronald van Langevelde Philips Research Europe Gennady Gildenblat, Weimin Wu, Xin Li, Amit Jha,

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

CHAPTER 4: P-N P N JUNCTION Part 2. M.N.A. Halif & S.N. Sabki

CHAPTER 4: P-N P N JUNCTION Part 2. M.N.A. Halif & S.N. Sabki CHAPTER 4: P-N P N JUNCTION Part 2 Part 2 Charge Storage & Transient Behavior Junction Breakdown Heterojunction CHARGE STORAGE & TRANSIENT BEHAVIOR Once injected across the junction, the minority carriers

More information

Semiconductor Physics Problems 2015

Semiconductor Physics Problems 2015 Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 105: Microelectronic Devices and Circuits Spring 2008 MIDTERM EXAMINATION #1 Time

More information

LOW TEMPERATURE MODELING OF I V CHARACTERISTICS AND RF SMALL SIGNAL PARAMETERS OF SIGE HBTS

LOW TEMPERATURE MODELING OF I V CHARACTERISTICS AND RF SMALL SIGNAL PARAMETERS OF SIGE HBTS LOW TEMPERATURE MODELING OF I V CHARACTERISTICS AND RF SMALL SIGNAL PARAMETERS OF SIGE HBTS Except where reference is made to the work of others, the work described in this thesis is my own or was done

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to

More information

Lecture 29: BJT Design (II)

Lecture 29: BJT Design (II) NCN www.nanohub.org C606: Solid State Devices Lecture 9: JT Design () Muhammad Ashraful Alam alam@purdue.edu Alam C 606 S09 1 Outline 1) Problems of classical transistor ) Poly Si emitter 3) Short base

More information

EKV MOS Transistor Modelling & RF Application

EKV MOS Transistor Modelling & RF Application HP-RF MOS Modelling Workshop, Munich, February 15-16, 1999 EKV MOS Transistor Modelling & RF Application Matthias Bucher, Wladek Grabinski Electronics Laboratory (LEG) Swiss Federal Institute of Technology,

More information

Electronic Circuits Summary

Electronic Circuits Summary Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

More information

Semiconductor Device Modeling and Characterization EE5342, Lecture 15 -Sp 2002

Semiconductor Device Modeling and Characterization EE5342, Lecture 15 -Sp 2002 Semiconductor Device Modeling and Characterization EE5342, Lecture 15 -Sp 2002 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/ L15 05Mar02 1 Charge components in the BJT From Getreau,

More information

Solid State Physics SEMICONDUCTORS - IV. Lecture 25. A.H. Harker. Physics and Astronomy UCL

Solid State Physics SEMICONDUCTORS - IV. Lecture 25. A.H. Harker. Physics and Astronomy UCL Solid State Physics SEMICONDUCTORS - IV Lecture 25 A.H. Harker Physics and Astronomy UCL 9.9 Carrier diffusion and recombination Suppose we have a p-type semiconductor, i.e. n h >> n e. (1) Create a local

More information

Circle the one best answer for each question. Five points per question.

Circle the one best answer for each question. Five points per question. ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions

More information

Plan Bipolar junction transistor Elements of small-signal analysis Transistor Principles: PETs and FETs Field effect transistor Discussion

Plan Bipolar junction transistor Elements of small-signal analysis Transistor Principles: PETs and FETs Field effect transistor Discussion Physics of silicon transistors - 1 - Plan Bipolar junction transistor homojunction and heterojunction Doping considerations Transport factor and current gain Frequency dependence of gain in a microwave

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

Erik Lind

Erik Lind High-Speed Devices, 2011 Erik Lind (Erik.Lind@ftf.lth.se) Course consists of: 30 h Lectures (H322, and Fys B check schedule) 8h Excercises 2x2h+4h Lab Excercises (2 Computer simulations, 4 RF measurment

More information

Session 6: Solid State Physics. Diode

Session 6: Solid State Physics. Diode Session 6: Solid State Physics Diode 1 Outline A B C D E F G H I J 2 Definitions / Assumptions Homojunction: the junction is between two regions of the same material Heterojunction: the junction is between

More information

Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two -

Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two - 6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Outline Announcements Exam Two Coming next week, Nov. 5, 7:309:30 p.m. Review Subthreshold operation of MOSFETs Review Large

More information