HICUM Parameter Extraction Methodology for a Single Transistor Geometry

Transcription

1 HICUM Parameter Extraction Methodology for a Single Transistor Geometry D. Berger, D. Céli, M. Schröter 2, M. Malorny 2, T. Zimmer 3, B. Ardouin 3 STMicroelectronics,, France 2 Chair for Electron Devices and Integrated Circuits, Dresden, Germany 3 Laboratoire de Microélectronique IXL, Bordeaux, France BCTM 2002, Monterey, CA

2 Goals Describe step by step the extraction procedure of main HICUM parameters for a single transistor geometry. Illustrate each step by the required characteristics and intermediate results. Present comparison between simulation and measurements of DC and AC characteristics of the transistor. Validate the methodology on different devices from various ST BiCMOS processes. /7

3 HICUM s features Parasitic PNP Substrate network Q js I jsc S I TS su Q su S Intrinsic transistor Weak avalanche C CX C Q BCx Q BCx I jbcx QdS C rbi I jbci Q jci B B* B I jbep Q jep Bx bi Q jei Q dc Q de I AVL I T I BEt I jbei Q Eox E E Self-heating Peripheral & extrinsic transistor Tunnelling E P th T C th AC crowding 2/7

4 Measurements Performed on HF structures, temperature regulated at 27 o C, using GSG- HF probes to avoid oscillation problems at DC operation. Depletion capacitances from Cold S parameters (HP850XF). DC measurements on HP442B and consisting of I B and I C versus V CB at constant V BE for the avalanche parameters extraction. Forward Gummel plot at positive and negative V BC for the collector, base and substrate parameters and the emitter resistance extraction. Output characteristics at fixed I B for the collector resistance determination. The transit time is deduced of the f T (I C,V BC ) curves obtained from S parameters in the range GHz. Transistors has been measured from different ST BiCMOS processes. 3/7

5 Extraction flow at room temperature Total BE, BC and CS Junction Capacitances Split of BE and BC Junction Capacitances C JEI0, C JEP0, C JCI0, C JCX0 BC avalanche F AVL, Q AVL Transfer at low C 0, Q P0, H JCI assuming H JEI = Internal BE I BEIS, M BEI, I EIS, M EI Parasitic substrate transistor everse BC I TSS, I BCIS, I BCXS Series esistances CX, E Transit time at low T 0, T BVL, D T0H, A LJEI (=A LJEP ) Transfer at low and medium H JEI, correction of C 0, Q P0, H JCI obtained in 4 Critical CI0, V CES, V PT, V Lim Transit time at high T EF0, G TFE, T HCS, A LHC Base esistance BI0, BX, F GEO, F DQ0 NQS effect A LIT, A LQF 4/7

6 - BC Avalanche - Transfer at low - BE at low - Substrate and reverse -Im(y 2 )/ω [ff] Total junction capacitance extraction Im( y 2 + y ) C BE ω Im( y 2 ) C BC ω Im( y 2 + y 22 ) C CS ω Frequency [GHz] V BC =0.6 V V BC =-0.6 V C ln(c) [x0 5 BC [ff] ] ln(c J0.V ZJ J ) -z J ln(v J -V) Z J lnc = ln C J0 V J Z J ln( V J V) Iteration on V J in order to obtain the best linear regression V BC [V] 5/7

7 Split of the BE junction capacitance C BE = C + C 2 C = X JBE C BE = A E C JEA C 2 = ( X JBE ) C BE = P E C JEP B r j E C C 2 - BC Avalanche - Transfer at low C JEA A E X JBE = = C BE C JEA A E A E C JEA + P E C JEP W E r j - BE at low - Substrate and reverse Assumption : C 2 π r j ( L E + W E ) C JEA = π -- r 2 j P E C JEA L E X JBE = π P E r j A E C JEI0 = X JBE C BE P E = 2 ( L E + W E ) C JEP0 = ( X JBE ) C BE A E = W E L E 6/7

8 - BC Avalanche - Transfer at low - BE at low - Substrate and reverse Im(Y 2 ) / ω [ff] Split of the BC junction capacitance [] fixed V BE -30 -a-c JCX lim --- Im( Y ω 2 ) ω 0 ω [0 9 rad/s] = - C JCX0 a C JCX0 --- Im( Y ω 2 ) a b ω 2 C JCX0 The external part C JCX0 of the BC capacitance comes from an optimization of the imaginary part of Y 2 at and for a fixed V BE. Then, the internal BC capacitance can be deduced from C JCI0 = C BC C JCX0 Y 2 = jωg b C JCI jωc g b + g π + jω( C π + C JCI0 ) JCX0 = g C b JCI0 where g = b ; a = ; b = B g + g b π lim --- Im( Y ω 2 ) ω = C + C JCI0 π g + g b π C JCX0 [] Seonghearn Lee, "A New Technique to Extract Intrinsic and Extrinsic Base-Collector Capacitances of Bipolar Transistors Using Y-parameter Equations", submitted to 2003 IEEE ICMTS, Monterey, CA. 7/7

9 - BC Avalanche - Transfer at low - BE at low - Substrate and reverse ln[(m-)/(v DCI + V CB )] I AVL B I B I B0 C I C0 Q AVL C V JCI0 DCI ln(f AVL ) [(V DCI + V CB )/V DCI ] Z CI - BC avalanche I = I + I = M I C CO AVL CO I B = I I BO = I B AVL The multiplication factor M is given by I C E M I C = I I C B I B / I B V BE =0.7V V CB [V] I B =I AVL I AVL Q M = F ( V V I AVL DCI + AVL = ) exp CB CO C ( V V JCI DCI + ) CB M ln = V + V DCI CB Q AVL V + V DCI CB Z CI ln( F ) AVL C V V JCI0 DCI DCI Linear regression on ln vs. V DCI + V CB Z CI V DCI parameters F AVL and Q AVL. M V + V DCI CB gives the avalanche 8/7

10 - BC Avalanche - Transfer at low - BE at low - Substrate and reverse I C /(C 0 /Q P0.exp(V BE /V T ) I I = C T Transfer at low C exp Q PT A linear regression on C Q gives 0 C 0 and P0 = Q H P0 = H JEI JEI V B'E' V B'C' V exp T V T At low and Q = Q + H Q PT P0 JEI JEI V B'E' exp C V 0 T Q P0 Q = JEI H JEI I H C JEI V BE [V] I C [A] Q JEI [fc] exp(v B E /V T )/I C [0-6 A - ] V BE [V] 9/7

11 - BC Avalanche - Transfer at low - BE at low - Substrate and reverse (I C -I AVL )/(C 0 /H JEI )/[exp(v B E /V T )-exp(v B C /V T )] [fc] I C /I C (V CB =0V) V B E =0.7V V B E =0.7V Q JCI [fc] V CB [V] Forward Early effect H JCI H JCI = H JEI Collector at V BE =0.7V and sweep of V BC. The collector is corrected by the BC avalanche I AVL I I Q H C AVL P0 JCI = Q Q C V 0 B'E' V B'C' H JEI H JCI JEI JEI exp exp H V JEI T V T H A linear regression gives JCI H JCI = H JEI I Normalized collector C versus I ( V = 0V) C CB V CB 0/7

12 - BC Avalanche - Transfer at low - BE at low Base Emitter, Substrate and reverse β I C [A] Assuming and M BEI = I B V B'E' I I = + exp V BEIS EIS B'E' V T M M EI BEI exp M V BEI T A sweep of M EI is made (and M BEI in case of non ideal base ) I BEIS and I EIS comes from linear regression with the best correlation coefficient - Substrate and reverse I C, I B [A] I C V BC =0.5V As the emitter is connected to the substrate, the HF measurements do not allow to directly measure the substrate. Therefore, in order to determine the parameters of the substrate PNP, we performed measurements with positive V BC (Substrate PNP on). 0-0 I B The transfer I TSS is then optimized on the I C (V BE ) curves at V BC >0V V BE [V] /7

13 - BC Avalanche - Transfer at low - BE at low - Substrate and reverse /gm [Ω] I C [ma] Emitter and collector series resistances E /I C [A - ] I B =0.,, 2, 4, 8, 20, 50 µa V CE [V] Using a simple equivalent circuit the following expression can be deduced B = with g g E β β m mi 0 0 Assuming B «, I I, m a linear regression is β E C T C = 0 di I T T di g mi and C = g = dv m ( I ) V m BEi C T T dv BE applied on g m V T = I E C Due to these assumptions, E obtained with this method is 0-20% over estimated A first value of CX is given by estimation from the transistor layout and sheet resistances. A fit on I C (V CE ) in hard saturation region is then performed 2/7

14 Transfer at medium β /β 50 H JEI = H JEI optimization BC Avalanche - Transfer at low - BE at low V BE [V] I C [ma] - Substrate and reverse Q Approximate effective knee P0 I = Keff due to T 0 the rough estimation of Q P0 assuming H JEI = H JEI is obtained by dichotomy in the region where I -- vs. I is linear at : C β C β β max I Keff The calculated H JEI allows to correct the collector parameters extracted previously at low density of :,, H = H H C C H JCI JCI JEI 0 0 JEI = Q = Q H P0 P0 JEI β H JEI = V BE [V] 3/7

15 - BC Avalanche - Transfer at low - BE at low - Substrate and reverse B [Ω] Base resistance extraction [2] A modified h is used in order to avoid the split of the BC capacitance. h = y + y 2 lim h B + E ω Im(h* ) [Ω] V BE =0.94V e(h* ) [Ω] Optimization of ln( + η) Q JEI + Q F F QI B = BX + I η Q JEI + Q F I I BEI η = F GE V T Q 0 I = BI Q 0 + Q JEI + Q JCI + Q F I C [ma] Q 0 = Q P0 ( + F DQ0 ) [2] T.Nakadai, K.Hashimoto, Measuring the Base esistance of Bipolar Transistors, BCTM 99, pp /7

16 Main results (50 GHz SiGeC BiCMOS process, 0.25x2.65 µm 2 ) β 500 Avalanche f T [GHz] 40 V BC =-0.5, -0.25, 0, 0.2, 0.4, 0.6V V BC =-, -0.5, 0, 0.5 V I C [ma] I C [ma] I B =0.,, 2, 4, 8, 20, 50, 00 µa I C [ma] I C, I B [A] V BC =-, -0.5, 0, 0.5 V V CE [V] V BE [V] 5/7

17 Temperature behavior (f T =70 GHz, A E =0.25x6.25µm 2 ) f T [GHz] C -40C 0C 0C 27C 27C 60C 60C 20C 20C TH =0 K/W I C [ma] I C [ma] TH =0 K/W C C 0C 0-4 0C 27C C 60C 60C C 20C V BE [V] TH =0 K/W TH =3500 K/W V BE [V] V BE [V] I B =0.,4, 8, 6, 40, 80 µa 0.7 I B =0.,4, 8, 6, 40, 80 µa V CE [V] V CE [V] 6/7

18 Conclusion and perspectives Conclusion and Perspectives The HICUM compact model has been evaluated on different BiCMOS processes up to 50 GHz f T. Comparisons to measurement demonstrate the suitability of the model for high speed applications. A single transistor parameter extraction method has been developed and applied to different processes and devices The main extracted parameters follow geometry scaling laws, validating the method used and the physical meaning of parameters. The next step is the extension of the extraction procedure to obtain a geometry scalable parameter set. Detailed investigation of temperature behaviour and self-heating is also in progress. 7/7