Investigation of New Bipolar Geometry Scaling Laws

Transcription

1 Investigation of New Bipolar Geometry Scaling Laws D. CELI 20 th Bipolar Arbeitskreis Munich, October 2007

2 Purpose Robust and high-performance RF circuit design need optimization of transistors. Therefore accurate geometry-scalable models and geometry-specific parameter extraction are needed. Despite we provide HICUM scalable libraries to designers since end of 2003, the extraction of geometry scalable HICUM parameters is always a nightmare!... How to accurately fit devices with both variable length and width? How to extract specific model parameters? Which geometry scaling laws to be used? Is the process scalable? Is the model scalable? We will try to answer some of these interrogations and to propose alternative to the existing solutions. This study is in the continuity of the work presented to the 7 th HICUM workshop [1]. 2/32

3 Availability of HICUM in DKs Process Performance Device Model Forecasted µm BiCMOS 50 GHz SiGe HBT LV and HV NPN 0.25µm BiCMOS 70, 55, 30 GHz SiGe:C HBT HS, LV and HV NPN Vertical isolated PNP 0.13µm BiCMOS 45 GHz SiGe:C low cost HBT LV NPN 0.13µm BiCMOS 160, 80 GHz SiGe:C HBT LV and HV NPN 0.13µm BiCMOS 250 GHz SiGe:C HBT LV NPN HICUM/L2 and STBJT scalable models HICUM/L2 and STBJT scalable models HICUM/L2 and STBJT scalable models HICUM/L2 and STBJT scalable models HICUM/L2 and STBJT scalable models HICUM/L0 scalable model HICUM/L0 scalable model HICUM/L0 scalable model 3/32

4 Example of 0.13µm BiCMOS GHz SiGe:C HBTs f T (I C ) for V CB = umx1.66um nbe=1 nbb=2 nbc=2 0.3umx3.70um nbe=1 nbb=2 nbc=2 0.3umx5.74um nbe=1 nbb=2 nbc=2 0.3umx9.82um nbe=1 nbb=2 nbc=2 0.3umx14.92um nbe=1 nbb=2 nbc=2 f T [GHz] F. Pourchon I C [ma] Real dimension = drawn dimension µm 4/32

5 Main Blocking Points No problem to fit DC current, capacitance and transit time for transistor with variable emitter widths and constant emitter length. But using the specific parameters, determined from transistors with variable emitter widths and constant emitter length, give less accurate fit on DC current, capacitance and transit time, for transistor with minimum emitter width and variable emitter lengths. Unfortunately, 95% of the design applications used transistors with minimum emitter width and variable lengths. Even, variable emitter width is not allowed in most of our BiCMOS technologies. Questions: which is responsible of this problem? Is it a problem of non-standard geometry scaling effect? Is it a problem of non-scalable model? Is it a problem of scalable parameter extraction? We will try to understand what happens and to answer to these questions... 5/32

6 Principle of Scalable BJT Models Generation Drawn dimensions W E, L E,... Real dimensions W E0, L E0, r 0,... Specific parameter extraction Scalable model Scaling laws - HICUM Effective dimensions - SGP W E*, L E*, r*, γ C,... One of the main critical path in this flowchart is the determination or the knowledge of the real dimensions of the transistor W E0 = W E Δ WE L E0 = L E Δ LE Drawn Emitter Window L E r c ΔW E 2 Real Emitter Window L E0 Δ WE, Δ LE can be positive or negative depending on the architecture of the transistor and are estimated from SEM measurements. ΔL E 2 W E0 6/32

7 Standard Specific Parameters Extraction Method The other critical point is the determination of the geometry-specific parameters Standard geometry scaling laws approach [2] X = X A A + X P P + 4X C (1) X is variable which is geometry dependent such as current, charge, capacitance, transit time... A and P are respectively the window Area and the Perimeter of the considered layer. X A, X P and X C are respectively the specific parameter per unit of area, per unit of perimeter and per corner. Extraction method For 2D devices (emitter length L E0 larger than the emitter width W E0 ), the corner component is negligible and the specific parameter X A and X P can be easily determined from the normalized quantity X/A vs. P/A X P --- = X A A + X P --- A X/A X A is deduced from the intercept of this characteristic and X P from the slope. X P X A P/A 7/32

8 Comments on standard approach As it is impossible (to be discussed) to exactly know the real size (W E0, L E0 ) of the devices, we can observe several behaviors for X/A vs. P/A as depicted in [3] All these cases are physical (X P >0) X/A and can be possible. The value of X P depends on the assumptions done to estimate the real dimensions of the devices. It is important to notice that in every case X A is the same and correspond to the real value of the area specific parameter. X P > 0 X A X P = 0 Very unlikely case, that corresponds to the case where the real emitter area is equal to the effective emitter area (X P =0). X P < 0 P/A larger devices All these cases (X P <0) are nonphysical and correspond to an overestimation of the real sizes of the device. 8/32

9 This method is applicable (accurate) if and only if the P/A ratio varies significantly. It is the case if devices with constant length L E0 (>> W E0 ) and variable widths W E0 are used. In the contrary, if we used devices with minimum emitter width W E0 and variable lengths L E0 (>>W E0 ) gives P --- A ( + ) = = = cst 2L E0 L E0 W E0 W E0 2L E0 L E0 W E0 W E0 Therefore, in this case, the P/A ratio is almost constant and the specific parameter X A and X P cannot be determined accurately. X/A X P X A P/A 9/32

10 Application to a Real Case In order to exhibit only geometry scaling issues and not possible problems due to measurement precision, we will work on a X variable easy to measure We will study the geometry dependence of the collector current I C at V BE = 0.65 V and V BC = 0V But same behavior can be observed on charge, capacitance and transit time. I C /A [μa/μm 2 ] Results (data given in Appendix A) L E0 = µm W E0 = 0.25 µm non-standard geometry scaling effects [2] W E0 = 0.45 µm W E0 = 0.65 µm W E0 = 1.05 µm W E0 = 1.45 µm As expected, for devices with constant length and variable widths, measured data I C /A vs. P/A are well aligned, excepted the largest transistor. It is certainly due to non-standard scaling effects [2]. J CA = µa/µm 2 +/- 4.39% J CP = µa/µm +/- 1.90% What happens for devices width minimum width and variable length (the most used in circuit design)? P/A [μm -1 ] 10/32

11 I C /A [μa/μm 2 ] Results on devices with variable lengths and constant minimum width Constant length W E0 = 0.25 µm Constant width L E0 = 6.25 µm L E0 = µm L E0 = µm Despite the small range of P/A ratio, for devices with constant width and variable lengths, measured data I C /A vs. P/A are well aligned. But the obtained specific parameters are totally in disagreement with the previous ones. And more serious is the negative value of the area component. J CA = µa/µm 2 +/ % Negative J CA P/A [μm -1 ] J CP = µa/µm +/ % This behavior cannot be explained with the theory previously developed. How to explain this strange result? Measurement accuracy, P/A ratio too small? Non-standard geometry scaling effects? Process spread? Wrong scaling equations? 11/32

12 Verification The same extraction has been performed on devices with other constant width and variable lengths L E0 = 6.25 µm L E0 = µm Whatever is the constant width, we observe the same behavior. I C /A [μa/μm 2 ] Length increase W E0 = 0.65 µm W E0 = 1.05 µm W E0 = 1.45 µm L E0 = µm W E0 = 0.45 µm What we see on the curves is certainly not a coincidence: all characteristics with constant emitter width are almost parallel. The dependence of the collector current with the emitter width and emitter length is not the same Width increase W E0 = 0.25 µm Why? P/A [μm -1 ] 12/32

13 Value of Specific Parameters for the Different Widths W EO 0.25 µm 0.45 µm 0.65 µm 1.05 µm 1.45 µm J CA (µa/µm 2 ) / % / % / % / % / % J CP (µa/µm) / % / % / % / % / % The peripheral collector current J CP is almost constant (parallel line) The area collector current J CA is non-physical (negative values) and is strongly dependent on the emitter width. Explanation? 13/32

14 New Scaling Geometry Approach (1) Drawn dimension Emitter windows Real dimension Spacer Do we know with exactitude the real size of the transistors? NO... Are we certain that the doping level in x and y directions is identical? NO... Transistors with orthogonal emitter have not the same current gain. Proposed geometry scaling law X = X A A + 2X L L + 2X W W + 4X C (2) 2 new geometry-specific parameters X L and X W X L specific parameter per unit of length X W specific parameter per unit of width 14/32

15 New Scaling Geometry Approach (2) Equation (2) can be written X = X A A + 2X L L + 2X W W + 4X C + ( 2X L W + 2X W L) ( 2X L W + 2X W L) or X = X A A + X L P + X W P ( 2X L W + 2X W L) + 4X C = X A A + X P P 2X L W 2X W L + 4X C and finally X = X A A + X P P 2X L W 2X W L + 4X C where X P = X L + X W (3) Equation (3) is similar to equation (1) with the addition of 2 correcting factors 2X L.W and 2X W.L Before to explain the methodology for extracting X A, X L, X W and X C, we will show the impact of these new specific parameters on the X/A vs. P/A characteristics in 2 cases: For devices with variable W and with constant L (2D case: L>>W) For devices with variable L and constant W (2D case: L>>W). 15/32

16 Consequence on X/A vs. P/A Characteristics for Devices with Variable W and Constant L L >> W, corner component becomes negligible. From (3) we can write X P 2X --- X A A X P --- L W 2X W L P 2X X A A A A X P --- L 2X W 2X L = + = X A L W A ( X L L + X W ) P --- A 2X W W As L >> W (2D devices) P 2L ( + W) = A LW W That leads to X 2X --- X L P A A X L L --- A therefore 2X W P X W W --- A X A X/A 2X L L X L as L is large, X A 2X L X P/A L A In conclusion, contrary to the standard approach, the intercept and the slope of the X/A vs. P/A do not give respectively X A and X P but X A - 2.X L /L X A and X L. 16/32

17 Consequence on X/A vs. P/A Characteristics for Devices with Variable L and Constant W From (3) we can write X P 2X --- X A A X P --- L W 2X W L P 2X X A A A A X P --- L 2X W 2X = = X W A L W A ( X W L + X W ) P --- A 2X L L As L >> W (2D devices) X/A 2X L L is negligible and that leads to X 2X --- X W P A A ( X W L + X W ) --- A Moreover as W is small, X A 2X W W could be negative X P = X W + X L In conclusion, contrary to the standard approach, the intercept and the slope of the X/A vs. P/A do not give respectively X A and X P but X A - 2.X W /W and X W +X L. X A 2X W W P/A To summarize, the introduction of X W and X L allows to explain the behaviors of X/A vs. P/A characteristics in all cases. 17/32

18 Extraction of New Geometry Specific Parameters The method is a little bit more complex than for the standard approach. We have now at least 3 parameters to be extracted: X A, X L and X W. 4 if we include X C. Normalized characteristics X/A vs. P/A can be no more used. The extraction is performed in 2 steps, on devices with variable W for different constant L In the first step, for each constant L, we will determine the slope S and the intercept I of the characteristic X vs. W In a second step, from the dependence of S and I vs. L, parameters X A, X L, X W and X C will be determined. 18/32

19 First Step Extraction Study of X vs. W characteristics for devices with constant L From equation (3) we can write X = X A A + X P P 2X L W 2X W L + 4X C = X A W L+ 2( X L + X W ) ( L + W) ( W 2X W L) + 4X C that leads to X = ( X A L + 2X W ) W+ 2X L L + 4X C X S(L) straight line L 3 L 2 L 1 slope = S = X A L + 2X W intercept = I = 2X L L + 4X C This method requires 3 time more transistors, with 3 different lengths, then the standard approach.. I(L) W 19/32

20 Second Step Extraction Study of S vs. L and I vs. L characteristics gives X A, X W and X L, X C S = X A L + 2X W I = 2X L L + 4X C S I X A 2X L 2X W 4X C Finally X A is deduced from the slope of the S vs. L plot X W is deduced from the intercept of the S vs. L plot X L is deduced from the slope of the I vs. L plot X C is deduced from the intercept of the I vs. L plot L L 20/32

21 Application to the Collector Current Step 1: I C vs. W E0 characteristics for devices with constant L E0 I C [μa] V BE = 0.65 V and V BC = 0 V L E0 = 6.25 μm W E0 [μm] L E0 = μm 6 I C [μa] V BE = 0.65 V and V BC = 0 V L E0 = μm W E0 [μm] I C [μa] V BE = 0.65 V and V BC = 0 V W E0 [μm] L EO 6.25 µm µm µm Slope (µa/µm) Intercept (µa) / % / % / % / % / % / % 21/32

22 Step 2: Slope vs. L E0 and Intercept vs. L E0 characteristics Slope [μa/μm] S = X A L + 2X W I = 2X L L + 4X C Intercept [μa] L E0 [μm] L E0 [μm] X A (µa/µm 2 ) X W (µa/µm) X L (µa/µm) X C /- 0.11% /- 2.48% /- 1.36% / % 22/32

23 Validation IC/A E0 vs. P E0 /A E0 for devices with variable widths W E0 and different length L E0 I C /A E0 [μa/μm 2 ] New approach Length increase I C /A E0 [μa/μm 2 ] Standard approach 0.1 Width increase P E0 /A E0 [μm -1 ] P E0 /A E0 [μm -1 ] X A (µa/µm 2 ) X W (µa/µm) X L (µa/µm) X C X A (µa/µm 2 ) X P (µa/µm) /- 0.11% /- 2.48% /- 1.36% / % /- 4.39% /- 1.90% 23/32

24 Device Geometry Needed For New Specific Parameter Extraction L E 64Wmin 32Wmin New structures for X L and X W extraction CBEBC structures Is it the best stucture for specific parameters extraction? L E, W E drawn emitteur dimensions 16Wmin 8Wmin Model verification Other structures CBE, CBEB, CBEC Multi-emitter fingers 4Wmin 2Wmin New structures including 3D effects verification Parameter extraction Parameter verification Wmin 1.5Wmin 2Wmin 3Wmin W E 24/32

25 Extended Notion of Effective Emitter Area The proposed approach is compatible with the notion of effective emitter area which is the keystone of HICUM geometry scaling equations [5]. We can define a new emitter effective area by A Eeff = ( L E0 + 2γ CL ) ( W E0 + 2γ CW ) with 2 γ C parameters, one associated to the length γ CL and the other associated to the width γ CW. If we compare we can easily deduce X W γ CL = X A X L γ CW = X A X C = X A γ CL γ CW with X = X A ( L + 2γ CL ) ( W+ 2γ CW ) X = X A A + 2X L L + 2X W W + 4X C For small devices, 3-D effects can be always improved by taking into account the corner rounding caused by lithography. For more detail see Appendix B. 25/32

26 Summary and Conclusion Since the beginning [4] we work on HICUM geometry scalable parameter extraction, we are facing an important geometry scaling issue Why the slope of X/A vs. P/A characteristics are not the same for devices with variable W and devices width variable L. This behavior is observed on all parameters which are geometry dependent (e.g. current, charge, capacitance, transit time...), and for all process we have characterized up to now. We demonstrated that this effect is well explained if a different peripheral specific parameter is chosen for the length and the width of the device. The origin of this behavior is under investigation (any are welcome). Some hypothesis are possible Real size of devices not known with enough accuracy? Doping level not identical in L and W? 26/32

27 Extraction procedure was developed and validated. In order to extract the additional geometry specific parameters, more test structures are needed At least devices with 4 variable widths for 3 different lengths. Then, if we want to use this new scaling approach, a non-negligible work has to be done in order to update The extraction tools The scalable library generation tools or templates As usual, any suggestions or comments are welcome... didier.celi@st.com 27/32

28 Appendix A: Measured Data Measurements of collector current at V BE = 0.65 V and V BC = 0 V (27 C) Structures BEC W E L E W E0 L E0 I C (µa) /32

29 Appendix B: Corner Rounding Effects Real emitter area A E0 and P E0 calculation r c r c r c 2 2 π r c 2 Area = r c = r 4 c 1 π 4 -- r c L E0 r c r c L E0 W E0min W E0 W E0min By taking into account the corner rounding, the actual emitter area A E0 and perimeter P E0 can be expressed as 2 A E0 W E0 L E0 4 r c 1 π = = W E0 L E0 r c ( 4 π) Corner rounding P E0 = 2 ( W E0 + L E0 ) 4 2 r c + 2 π r c = 2 ( W E0 + L E0 ) 2 ( 4 π) r c Corner rounding W E0min By default r c is set to r c = , where W E0min is the minimum emitter width allowed by the process. 2 29/32

30 Corner rounding effects for different widths of the emitter window rc = 0.2 μm rc = 0.2 μm rc = 0.2 μm rc rc rc (a) 0.4 μm (c) 0.8 μm 1.6 μm rc = 0.2 μm rc = 0.2 μm rc rc (b) (e) 0.6 μm (d) 1.2 μm Corner rounding for different width of the emitter windows (before spacer). (a) 0.4µm, (b) 0.6µm, (c) 0.8µm, (d) 1.2µm and (e) 1.6µm. For all devices, the emitter windows length is equal to 12.8 µm. We can notice that for all emitter windows, the corners rounding are similar and equal to W min r c = = 0.2μm. 2 20th Bipolar Arbeitskreis Didier CELI 30/32

31 Effective emitter area A E* calculation Taken into account the corner rounding and the 2 different values of γ CL and γ CW, the effective emitter area A E* is expressed as W E* Ellipse A E = W E L a b ( 4 π) E r c b with W E = W E0 + 2γ CW L E = L E0 + 2γ CL a = r c + γ CW b = r c + γ CL L E* γ CL a γ CW L E0 W E0 Reminder: area A and perimeter P of an ellipse a b A = π ab P = π { 3a ( + b) ( a + 3b) ( 3a + b) } Ramanujan's approximation 31/32

32 References [1] D. Céli, Review of Some HICUM Geometry Scaling Laws: Issue and Proposal, 7 th HICUM Workshop, Dresden, June [2] M. Schröter, S. Lehmann, D. Céli, Non-Standard Geometry Scaling Effects in High-Frequency SiGe Bipolar Transistors, NSTI Nanotech, WCM May [3] Jörg Berkner, Bipolar Model Parameter Extraction, BCTM Short Course [4] D. Céli, γ CW = γ CL Myth or Reality!..., internal ST report, DC18.00, September [5] M. Schröter, D.J. Walkey, Physical Modeling of Lateral scaling in Bipolar transistor, IEEE J. Solid-State Circuits, Vol. 31, PP , 1996 and Vol. 32, pp. 171, /32