Nonlinear distortion in mm-wave SiGe HBTs: modeling and measurements

Size: px
Start display at page:

Download "Nonlinear distortion in mm-wave SiGe HBTs: modeling and measurements"

Transcription

1 Nonlinear distortion in mm-wave SiGe HBTs: modeling and measurements P. Sakalas $,#, A. Pawlak $, M. Schroter $ $ CEDIC, Technische Universität Dresden, Mommsenstrasse 13, Germany # FRLab. Semiconductor Physics Inst., Center of Physical Sciences and Technology, Lithuania paulius.sakalas@tu-dresden.de

2 Outline Outline Motivation Compact modeling approaches, requirements for mm-wave frequencies Standard compact models for SiGe HBTs, location of nonlinear effects Investigation method of distortion effects in SiGe HBTs Harmonic distortion: core model verification vs. intrinsic (1D) and internal (2D) transistors, analysis of distortion HICUM L2 verification on DC and RF characteristics of measured advanced SiGe HBTs HICUM L2 verification on harmonic distortion (FoM) on two tone load pull of SiGe HBTs Analysis of external parasitic compact model elements on harmonic distortion. Summary

3 Motivation Motivation Benefits: SiGe based HBTs have proven to be among the fastest transistors on the market today. Recent SiGe HBT technology offers f T /f max = 3/5 GHz and enables mm wave circuits for various applications: optical communications with 1 Gbit/s 77 to 15 GHz collision radar applications LNA at 26 GHz for receivers, Heterodyne receivers for operation at THz frequencies cryogenic applications Issues: =>All those applications require physics based accurate models capable to capture nonlinearities at high frequency.

4 Motivation Fundamental compact modeling approaches Goal: cover large variety of applications & circuit optimization (bias, T, f) Criteria Behavioral, X-par. Physics-based accuracy high (within narrow ranges) moderate to high over wide range numerical stability compromised outside fitting ranges fabricated devices need every possible layout used in circuits on test chip high (for standard models) only few devices (6 HF trs, 6 test structures) measurement effort moderate to high moderate to low par. extraction effort moderate (single device), very high for library, imposs. at high f moderate (single device) very low for library geometry scaling inconsistent (typically) consistent predictive capability none moderate to high statistical modeling none (very high effort) good to excellent Physics-based model (cuts design cycle & supports process dev.)

5 Motivation Compact HBT modeling at (sub-)mm-wave frequencies Circuit design related requirements: design at the physical device and process technology limit => meeting specs is very challenging large variety of applications (implemented in BiCMOS SoCs) => need careful individual and sophisticated optimization (by e.g. device sizing) accurate models up to very high frequencies incl. subharmonics (i.e. distortion) consequences for compact modeling (e.g. for foundries) physics-based => enables: geometry scaling (i.e. contact configuration & emitter size) extension into non-measurable operation (bias, frequency, temperature) ranges with reasonable accuracy predictive and statistical design geometry scalable models => enables circuit optimization large-signal capability => enables accurate small-signal and distortion modeling good modeling pays for itself if it saves just one design iteration!!

6 Existing standard large-signal BJT and HBT models Existing standard large-signal BJT and HBT models SPICE Gummel-Poon model addresses effects present in "7ies" BJT technologies, no HBT effects. HICUM/L2, MEXTRAM, VBIC include some or all SiGe HBT related effects. HICUM includes mm-wave technology related effects in SiGeC HBTs (s. DOTFIVE). S I_Rsu S R su S Q js i jsc S I_SCi i Ts C su internal transistor R Cx S I_Rcx C Q BCx Q BCx i jbcx Q ds S I_BCx C ds S I_rBi S I_BCi i jbci Q jci Q r i AVL S I_AVL B R Bx S I_RBx S I_BEp C jep i BEtp R Bi B * B Q jep S I_BEi i jbei Q jei Q f i BEti i T i jbep C BEpar1 C BEpar2 R E S I_RE noise correlation I nc =sqrt(2qi T ) I nb =sqrt(2qi jbei ) V nc 1S. V nc V nb 1S. V nb E thermal network P ΔT j T R th C th vertical NQS effects Q f,qs/τ Bf Q f,nqs α Qf R=τ Bf T b1 V nb T b2 V nc noiseless internal transistor g nc2 V nc T b1 =1+jωτ Bf sqrt(b f (2α Qf - α it ) 2 ) T b2 = jωτ Bf α it I T,qs/τ Bf V C1 V C2/τ Bf α IT I T,nqs=V C2 V C1 /τ Bf R= τ Bf α IT/3

7 Existing standard large-signal BJT and HBT models Where are the nonlinear effects in HBTs? I C ~ exp(v BE /V T ); Q mobile ~ I C γ (γ 1); I aval ~ I C exp(v CB /V B ); Q depl ~ (1-V j /V D ) z... schematic cross-section typical profile 25 Doping ( ) x (μm) Mol fraction ( ) (%) 1D (or intrinsic) transistor (here: f T,peak = 25 GHz) internal transistor (includes internal base resistance) device nonlinearity is mostly defined by intrinsic transistor

8 Existing standard large-signal BJT and HBT models Goals of this presentation consider intrinsic model based on 1D device simulation (as reference) start with single tone signal at fundamental frequencies of 1Hz, (1, 5, 2) GHz => verify compact model distortion behavior up to subharmonics of several peak f T (i.e. far above measurable frequencies!!) extension to internal transistor (with 2D device simulation as reference) => impact of nonlinear internal base resistance extension to complete (3D) transistor structure and experimental characteristics => impact of external regions.

9 Investigation method of distortion effects in SiGe HBTs Investigation method of distortion effects in SiGe HBTs Start with 1D transistor => use 1D device simulation as reference define suitable DC bias point => simple amplifier circuit (R G = 5 Ω, R L = 97 Ω) 25 J C V B E /V.9.88 R G C B V B L B T 1D V C L C CC i RL 5 v in R L v out V (V) CE T 1D : use either 1D numerical transistor or compact model (HICUM) => same numerical "environment" for compact model and reference run mixed-mode device simulator with single-tone input signal

10 Investigation method of distortion effects in SiGe HBTs Model evaluation and verification procedure... time domain transient simulation is employed input voltage amplitude from small-signal (1 mv) to large-signal is varied (2 mv) => input power P in = [-4, ] dbm (= [.1μW, 1mW]) fundamental frequencies f of input signal are selected: - f = 1 Hz (no capacitive effects, guaranteed quasi-static (qs) operation) - f = 1 GHz (some capacitive effects, qs operation) - f = 5 GHz (5 th harmonic close to f T,peak, capac. effects, some non-qs operation) - f = 2 GHz (close to f T,peak, 5th harmonic = 1THz, significant non-qs effects) to ensure stead-state at least 1 periods were simulated for each simulation: time domain waveform of last periods for node voltages, branch currents and charges were recorded Fourier transformation of waveforms of desired variables was applied => frequency components (=> harmonic distortion) of variables and FoMs single-tone and resulting harmonic distortion (HD) was considered => reveals fundamental model limitations evolution of FoMs {P out (P in ), P 1dB (J C ), OIP 3 (J C )} with f is analyzed

11 Investigation method of distortion effects in SiGe HBTs f = 1 Hz 1D: Harmonic distortion: P out vs. P in V BE =.88V, V CE 2= 1V P out D sim. f1 1D sim. f2 1D sim. f3 1D sim. f4 1D sim. f5 HICUM/L2 (tr) P avs P out D sim. f1 1D sim. f2 1D sim. f3 1D sim. f4 1D sim. f5 HICUM/L2 (tr) f = 1 GHz P avs 2 2 f = 2 GHz P out D sim. f1 1D sim. f2 1D sim. f3 1D sim. f4 1D sim. f5 HICUM/L2 (tr) f = 5 GHz P avs P out D sim. f1 1D sim. f2 1D sim. f3 1D sim. f4 1D sim. f5 HICUM/L2 (tr) P avs very good agreement up to f = f T,peak /5

12 Investigation method of distortion effects in SiGe HBTs J C D: Harmonic distortion: bias point shift vs. P in 1D simulation HICUM/L2 (HB) HICUM/L2 (tr) 1D simulation HICUM/L2 (HB) HICUM/L2 (tr) P 1dB P avs V BE =.88V, V CE = 1V f = 1 Hz f = 5 GHz J C P avs D simulation HICUM/L2 (HB) HICUM/L2 (tr) 1D simulation HICUM/L2 (HB) HICUM/L2 (tr) P 1dB f = 1 GHz f = 2 GHz J C 2 15 P 1dB J C 2 15 P 1dB P avs P avs excellent agreement (also for harmonics) even beyond P 1dB

13 Investigation method of distortion effects in SiGe HBTs 1D: Harmonic distortion: P out vs. J C at P 1dB 2 f = 1 Hz variable R L 2 f = 1 GHz P out D sim. f1. 1D sim. f2. 1D sim. f3. 1D sim. f4. 1D sim. f5 HICUM/L2 (tr) J C peak f T P out D sim. f1. 1D sim. f2. 1D sim. f3. 1D sim. f4. 1D sim. f5 HICUM/L2 (tr) J C peak ft 2 f = 5 GHz 2 f = 2 GHz P out D sim. f1. 1D sim. f2. 1D sim. f3. 1D sim. f4. 1D sim. f5 HICUM/L2 (tr) J C peak f T P out D sim. f1. 1D sim. f2. 1D sim. f3. 1D sim. f4. 1D sim. f5 HICUM/L2 (tr) J C peak f T very good agreement up to f = f T,peak /5, some Δ at f f T,peak & high J C

14 Investigation method of distortion effects in SiGe HBTs OIP 3 OIP f = 1 Hz ~J C 1D: Harmonic distortion: OIP 3 vs. J C 1 1D simulation HICUM/L2 (tr) f = 5 GHz J C V CE = 1V OIP 3 variable R L OIP D simulation HICUM/L2 (tr) f = 1 GHz J C f = 2 GHz 2 1D simulation HICUM/L2 (tr) J C 2 1D simulation HICUM/L2 (tr) J C model tracks trend very well, some deviation beyond J C (f T,peak )

15 Investigation method of distortion effects in SiGe HBTs 1D: Time domain results at P 1dB : V B E =.88V J RL dbm -23 dbm f = 1 Hz 1D Simulation HICUM/L t ( s) 1-12 dbm f = 5 GHz -1 dbm J RL 5 5 f = 1 GHz 1D Simulation HICUM/L t (ps) f = 2 GHz J RL 5 5 1D Simulation 1 1 HICUM/L2 2 t (ps) 3 4 J RL 5 5 1D Simulation 1 2 HICUM/L2 4 6 t (ps) 8 1 excellent agreement up to f = f T,peak /5, some deviation at f f T,peak

16 1D: Analysis of distortion effects 1D: Analysis of distortion effects Impact of i T and g m modeling on bias point shift classical approximation i T = I S v B'E' exp m C V T => no compression due to missing impact of mobile charge I C (ma) D simulation HICUM/L2 classical ICCR P avs simplified GICCR approximation (ICCR) i T = c 1 ( v B'E' V T ) v B'C' V T Q p + Q j, T + h f τ f i T exp exp( ) Δi C (ma) D simulation HICUM/L2 simple (5th) ICCR => deviations, but correct trend P avs simple form of GICCR can already explain trends

17 1D: Analysis of distortion effects P out D: Impact of high-current effects: P out vs. P in 1D sim. on, on off, on on, off off, off I T (ΔQ f,t ), Q f (ΔQ f ) f = 1 Hz P avs 2 1 I (ΔQ ), Q (ΔQ ) T f,t f f V BE =.88V, V CE = 1V high-current effect related model parameters turned on/off separately for charge (ΔQ f ) and transfer current (ΔQ f,t ) low f: deviations from ΔQ f,t at f 2 and P 1dB high f: deviations from ΔQ f at f 3 and P 1dB I T (ΔQ f,t ), Q f (ΔQ f ) P out D sim. on, on off, on on, off off, off f = 5 GHz P avs P out D sim. on, on off, on on, off off, off f = 2 GHz P avs high-current effects should be considered

18 1D: Analysis of distortion effects J RL 1D: Impact of high-current effects: time domain at P 1dB D sim. on, on off, on on, off off, off I T (ΔQ f,t ), Q f (ΔQ f ) f = 1 Hz V BE =.88V, V CE = 1V high-current effect related model parameters turned off/on separately for charge (ΔQ f ) and transfer current (ΔQ f,t ) low f: amplitude deviations from ΔQ f,t J RL t ( s) D sim. on, on off, on on, off off, off I T (ΔQ f,t ), Q f (ΔQ f ) f = 5 GHz high f: only small deviations from ΔQ f J RL D sim. on, on off, on on, off off, off I T (ΔQ f,t ), Q f (ΔQ f ) f = 2 GHz t (ps) t (ps) high-current effect impact mainly on amplitude, less on phase

19 1D: Analysis of distortion effects P out D: Impact of BC depletion capacitance: P out vs. P in 1D sim. HICUM/L2 Q jci, lin Q jci, 2nd Q jci, 5th f = 1 GHz V BE =.8V, V CE = 1V P out D sim. HICUM/L2 Q jci, lin Q jci, 2nd Q jci, 5th f = 5 GHz P avs P avs Q jci (V B C ) approximated by 5th-order polynomial over relevant voltage range => consider only linear or 2nd-order approximation for charge term (keep using complete analytical term in GICCR to keep bias current unaffected) linear Q jci (i.e. C jci =const): visible impact from f 3 on & already at low power level 2nd-order polynomial: visible impact from f 4 on & at low power level

20 1D: Analysis of distortion effects Impact of BC depletion capac.: time domain results at P 1dB J RL D sim. HICUM/L2 Q jci, lin Q jci, 2nd Q jci, 5th f = 1 GHz V BE =.8V, V CE = 1V J RL D sim. HICUM/L2 Q jci, lin Q jci, 2nd Q jci, 5th f = 5 GHz t (ps) t (ps) low f: mostly amplitude and some shape deviation for linear Q jci high f: - amplitude and shape deviation increase, also incorrect phase - 2nd-order approximation of Q jci is worse than first-order approximation need to have accurate Q jci (V B C ), do not need Q jci (J C )

21 1D: Analysis of distortion effects B l E i jbci i BEi 2D: Impact of nonlinear internal base resistance E C Q jci Q jei E emitter window b E /2 B B* T i Z Bi n + p Q r Q f n-sic n + buried layer I Bi /2 V BE =.88V, V CE = 1V i AVL p + i T C emitter perimeter junction internal transistor P out P out D 2D P avs D 2D f = 2 GHz f = 5 GHz P avs significant impact of R Bi on higher order distortion at high frequencies

22 Measured devices Measured devices SiGe HBTs: IHP, Frankfurt/Oder, f T = 3 GHz, f max = 5 GHz, A E = 8*.12 μm*.96 μm ST Microelectronics, f T = 32 GHz, f max = 37 GHz, A E =.12 μm*9.94 μm

23 3D: model verification: IV characteristics 3D: model verification: IV characteristics J C, J B (ma/µm 2 ) SiGe HBT A E =.12 um*9.94 um V BC = V J C J B HICUM a) V BE (V) b) J C (ma/µm 2 ) SiGe HBT, A E =.12 um*9.94 um Meas. HICUM V BE [.6-.99, 5m] V V CE (V) a) Forward Gummel plot with V BC = V. => High collector current linearity and current gain β =3. b) Output characteristic with a V BE drive. => HICUM is in a perfect agreement.

24 3D: model verification: IV characteristics 3D: model verification: f T, f max, C BC f T, f max (GHz) 4 SiGe HBT A E =.12 um*9.94 um 3 V BC = V 2 1 f T f max HICUM C BC (ff) SiGe HBT A =.12um*9.94um E A =.12um*.96um*8 E HICUM a) b) J C (ma/µm 2 ) V BC (V) => good agreement in a whole bias range. => weakly nonlinear depletion capacitance behavior. => HICUM is in good agreement.

25 5 GHz SiGe HBT, harmonic distortion: Pout (Pavs) 5 GHz SiGe HBT, harmonic distortion: P out (P avs ) Fundamental frequency of 1 GHz, five harmonics were measured. 1 GHz 1 GHz 2 GHz 3 GHz 4 GHz 5 GHz a) b) SiGe HBT A E = 8*.12 μm*.96 μm, V CE = 1 V, V BE =.9 V. The 5 th harmonic is on the limit of network analyzer frequency, 5 GHz. From the linearized capacitance simulations it was found a negligible impact of base/ collector junction capacitance C BC on nonlinearity. HICUM is in a good agreement.

26 5 GHz SiGe HBT, harmonic distortion: Pout (Pavs) 5 GHz SiGe HBT, HD: I C (P avs ), load circles Fundamental frequency 1 GHz a) HICUM: solid line SiGe HBT A E = 8*.12 μm*.96 μm, V CE = 1 V, V BE =.9 V. I C (A) b) V CE (V) Pin -21dBm HICUM I C Pin -11dBm V BE =.9V Deviation from quiescent collector current with input power is due to self-biasing. At high input power non quiescent bias can may trigger impact ionization (V CE >1.6 V) and pronounced selfheating => increase of HD Avl.

27 5 GHz SiGe HBT, HD: Impact of external capacitances 5 GHz SiGe HBT, HD: Impact of external capacitances Time domain, excitation with 1 GHz and -21 dbm CW power. HICUM: solid line Excluded external parasitic capacitances a) b) SiGe HBT: A E = 8*.12 μm*.96 μm, V CE = 1 V, V BE =.9 V. Exclusion of the external parasitic base/emitter and base/collector capacitances only slightly impacts the dynamic collector current. At higher frequencies an impact may be more evident.

28 5 GHz SiGe HBT, HD: Impact of external base resistance 5 GHz SiGe HBT, HD: Impact of external base resistance A E = 8*.12 μm*.96 μm, V CE = 1 V, V BE =.9 V, excitation with 1 GHz. Rbx/2 Rbx/2 a) b) Reduced external base resistance from 11 Ω to 5.5 Ω increase f max value. Standard IV and RF characteristics are preserved. No impact on HD since external parasitic resistance is constant with bias.

29 5 GHz SiGe HBT, HD: Impact of external collector resistance 5 GHz SiGe HBT, HD: Impact of external collector resistance A E = 8*.12 μm*.96 μm, V CE = 1 V, V BE =.9 V, excitation with 1 GHz. Rcx/2 Rcx/2 a) b) Reduced external collector resistance from 1 Ω to 5 Ω. =>increase f max and f T values, improves IV and RF performance. negligible impact on HD.

30 5 GHz SiGe HBT, HD: Impact of emitter resistance 5 GHz SiGe HBT, HD: Impact of emitter resistance A E = 8*.12 μm*.96 μm, V CE = 1 V, V BE =.9 V, excitation with 1 GHz Re/2 Re/2 a) b) Reduced external emitter resistance from 2.9 to 1.45 Ω. => slight increase f T, f max. => decrease of J C at peak f T, f max. => base and collector current increase at high V BE. =>HD increase, G T increase due to lower negative feedback, ie. lower linearization by constant resistor.

31 5 GHz SiGe HBT, HD: modeling at high input power 5 GHz SiGe HBT, HD: modeling at high input power Excitation with 5 and 1 GHz Pin -11 dbm and +1 dbm CW power. 5 GHz, -11 dbm 5 GHz, -11 dbm a) 1 GHz, 1 dbm b) c) d)

32 5 GHz SiGe HBT, GT and PAE% 5 GHz SiGe HBT, G T and PAE% A E = 8*.12 μm*.96 μm, V CE = 1 V, V BE =.9 V, excitation with 1 GHz Linear gain up to -11 dbm is observed. 35% of maximum power added efficiency at 1 GHz is achieved.

33 5 GHz SiGe HBT, IIP3, OIP3 versus IC 5 GHz SiGe HBT, IIP3, OIP3 versus I C A E = 8*.12 μm*.96 μm, V CE = 1 V, V BE =.9 V, excitation with 1 GHz Good agreement with HICUM of third order input IIP3 and output OIP3 interception points.

34 37 GHz SiGe HBT, HD: Pout (Pavs) 37 GHz SiGe HBT, HD: P out (P avs ) Fundamental frequency 1 GHz a) b) SiGe HBT A E =.12 μm*9.94 μm, V CE = 1 V, V BE =.9 V. HICUM is in fair agreement.

35 37 GHz fmax SiGe HBT, HD: IC,DC (Pavs), load circles 37 GHz f max SiGe HBT, HD: I C,DC (P avs ), load circles Fundamental freq. 1 GHz 4 E V BE [.6-.9, 5m] V J C (ma/µm 2 ) Meas. -11 dbm -21 dbm HICUM SiGe HBT A E =.12 μm*9.94 μm, V CE = 1 V, V BE =.9 V Collector current drops with input power with a following increase. V CE (V) Dynamic current circles at P in = -11 dbm hit the region of impact ionization BV CE = 1.6V. HICUM is in fair agreement but not for the load circles.

36 37 GHz SiGe HBT, HD: GT (Pavs), PAE% 37 GHz SiGe HBT, HD: G T (P avs ), PAE% Fundamental frequency 1 GHz a) b) SiGe HBT A E =.12 μm*9.94 μm, V CE = 1 V, V BE =.9 V. PAE reaches 4%. Good agreement with HICUM.

37 37 GHz SiGe HBT, HD: dynamic base and collector current and voltage waves and IIP3 and 37 GHz SiGe HBT, HD: dynamic base and collector current and voltage waves and IIP3 and OIP3 versus bias. SiGe HBT A E =.12 μm*9.94 μm, V CE = 1 V, V BE =.9 V. a) b) c) a) base dynamic current and voltage at 5 GHz and P in = 5 dbm. b) collector dynamic current and voltage at 5 GHz and P in = 5 dbm. IIP3 and OIP3 at 1 GHz.

38 SiGe HBT, measured load pull at 45 GHz SiGe HBT, measured load pull at 45 GHz a) V in =.88V, V out =1V Γ in =.15+j.88, P in = 15dBm HICUM P out in dbm b) P in = 15dBm, V out =1V meas. sim. HICUM V BE in V P out in dbm c) V in =.88V, V out =1V meas. sim. HICUM P in in dbm SiGe HBT A E = 8*.12 μm*.96 μm, V CE = 1 V, V BE =.88 V. a) Simulated load isopower lines fairly matches the measured data at 45 GHz. Measurements were performed with Maury impedance automated tuner (MT984A) system ATS. b) The power of the sum of harmonics versus V BE. HICUM is solid line. c) Output power versus input power.

39 Summary HBT modeling approaches Summary physics-based vs. behavioral v: clear advantages for physics-based models => exclusively used in SiGe HBT design kits Detailed comparison of core compact model formulation with 1D device simulation typical distortion characteristics over wide range of input power, bias, and frequency => - very good agreement up to at least P 1dB, J C (f T, peak ), and f = f T,peak /4 - still reasonable agreement at f =.8 f T, peak (with f 5 = 1THz!!) Analysis of distortion in advanced SiGe HBTs impact of high-current effects, BC depletion capacitance, internal base resistance => identification of the contribution of transfer current and charge-storage nonlinearity Detailed comparison of compact model with measurements (3D) Perfect agreement of DC, RF characteristics of high speed SiGe HBTs (f T / f max = 32/37 GHz), SiGe HBTs (f T /f max = 3 /5 GHz).

40 Summary Nonlinear characteristics were measured on wafer with a 5 GHz PNA -X. Load pull single and two tone measurements were carried out with automated impedance tuner system from Maury. HICUM model agrees fairly well with measured nonlinear data up to measure 5 GHz. External parasitic bias independent capacitances for SiGe HBTs have negligible influence on the harmonics. Acknowledgment European Union's Seventh Programme for research, technological development and demonstration under grant agreement No European CATRENE Office (project RF2THz) Keysight Technologies (PNA-X loan) and constant support. Steffen Lehmann is acknowledged for the load pull simulation.

41 Summary References [1] MTT IMS 214, WMF workshop, "Physiscs-based Nonlinear Compact Transistor modeling for mm-wave Applications", Drs. P. Sakalas, M. Schroter. [2] S. Narayanan, Transistor distortion analysis using Volterra Series representation, BSTJ, pp , [3] S. Chisholm and L. Nagel, Efficient computer simulation of distortion in electronic circuits, IEEE Trans. Circ. Theory, pp , Nov [4] D. Weiner and J. Spina, Sinusoidal analysis and modeling of weakly nonlinear circuits, Van Nostrand, NY, 198. [5] R. Meyer, Intermodulation in high-frequency bipolar transistor integrated-circuit mixers, IEEE. J. Sol.-St. Circ., Vol. 21, pp , [6] S. Maas et al., Intermodulation distortion in heterojunction bipolar transistors, IEEE Trans. MTT, Vol. 4, pp ,1992. [7] M. Schroter, et al., Compact modeling of high-frequency distortion in Si integrated bipolar transistors, IEEE Trans. on Electron Dev., Vol. 47, pp , 2. [8] M. Vaidyanathan et al., "High-frequency distortion in bipolar transistors", IEEE Trans. MTT, Vol. 51, pp , 23. [9] P. Sakalas, et al., Modeling of SiGe power HBT intermodulation distortion using HI- CUM, Proc. ESSDERC 23, Lisboa, pp , 23.

Modeling high-speed SiGe-HBTs with HICUM/L2 v2.31

Modeling high-speed SiGe-HBTs with HICUM/L2 v2.31 Modeling high-speed SiGe-HBTs with HICUM/L2 v2.31 A. Pawlak, M. Schroter, A. Mukherjee, J. Krause Chair for Electron Devices and Integrated Circuits (CEDIC) Technische Universität Dresden, Germany pawlak@iee.et.tu-dresden.de,

More information

HICUM release status and development update L2 and L0

HICUM release status and development update L2 and L0 HICUM release status and development update L2 and L0 M. Schröter, A. Pawlak 17th HICUM Workshop Munich, Germany May 29th, 2017 Contents HICUM/L2 in a nutshell Release of HICUM/L2 version 2.4.0 Strong

More information

Accurate transit time determination and. transfer current parameter extraction

Accurate transit time determination and. transfer current parameter extraction Accurate transit time determination and transfer current parameter extraction T. Rosenbaum, A. Pawlak, J. Krause, M. Schröter Chair for Electron Devices and Integrated Circuits (CEDIC) University of Technology

More information

HICUM Parameter Extraction Methodology for a Single Transistor Geometry

HICUM Parameter Extraction Methodology for a Single Transistor Geometry HICUM Parameter Extraction Methodology for a Single Transistor Geometry D. Berger, D. Céli, M. Schröter 2, M. Malorny 2, T. Zimmer 3, B. Ardouin 3 STMicroelectronics,, France 2 Chair for Electron Devices

More information

HICUM / L2. A geometry scalable physics-based compact bipolar. transistor model

HICUM / L2. A geometry scalable physics-based compact bipolar. transistor model HICUM HICUM / L2 A geometry scalable physics-based compact bipolar transistor model M. Schroter, A. Pawlak, A. Mukherjee Documentation of model version 2.32 August, 2013 M. Schroter 16/5/14 1 HICUM List

More information

A new transit time extraction algorithm based on matrix deembedding techniques

A new transit time extraction algorithm based on matrix deembedding techniques 27 A new transit time extraction algorithm based on matrix deembedding techniques C. Raya, N. Kauffmann, D. Celi, T. Zimmer State of art Method Result Introduction T F importance: - T F physical information

More information

Transistor's self-und mutual heating and its impact on circuit performance

Transistor's self-und mutual heating and its impact on circuit performance Transistor's self-und mutual heating and its impact on circuit performance M. Weiß, S. Fregonese, C. Maneux, T. Zimmer 26 th BipAk, 15 November 2013, Frankfurt Oder, Germany Outline 1. Motivation. Research

More information

Non-standard geometry scaling effects

Non-standard geometry scaling effects Non-standard geometry scaling effects S. Lehmann 1), M. Schröter 1),2), J. Krause 1), A. Pawlak 1) 1) Chair for Electron Devices and Integr. Circuits, Univ. of Technol. Dresden, Germany 2) ECE Dept., University

More information

2 nd International HICUM user s meeting

2 nd International HICUM user s meeting 2 nd International HICUM user s meeting Monterey, September 22 D. Berger, D. Céli, T. Burdeau STMicroelectronics,, France esults HICUM status in ST Implementation of HICUM model equation in an in-house

More information

About Modeling the Reverse Early Effect in HICUM Level 0

About Modeling the Reverse Early Effect in HICUM Level 0 About Modeling the Reverse Early Effect in HICUM Level 0 6 th European HICUM Workshop, June 12-13, 2006, Heilbronn Didier CELI, STMicroelectronics 1/21 D. Céli Purpose According to the bipolar models,

More information

Regional Approach Methods for SiGe HBT compact modeling

Regional Approach Methods for SiGe HBT compact modeling Regional Approach Methods for SiGe HBT compact modeling M. Schroter 1),2) and H. Tran 2) 1) ECE Dept., University of California San Diego, La Jolla, CA, USA 2) Chair for Electron Devices and Integr. Circuits,

More information

Breakdown mechanisms in advanced SiGe HBTs: scaling and TCAD calibration

Breakdown mechanisms in advanced SiGe HBTs: scaling and TCAD calibration Breakdown mechanisms in advanced SiGe HBTs: scaling and TCAD calibration T. Rosenbaum 1,2,3, D. Céli 1, M. Schröter 2, C. Maneux 3 Bipolar ArbeitsKreis Unterpremstätten, Austria, November 6, 2015 1 STMicroelectronics,

More information

Working Group Bipolar (Tr..)

Working Group Bipolar (Tr..) Department of Electrical Engineering and Information Technology Institute of Circuits and Systems Chair for Electron Devices and Integrated Circuits Working Group Bipolar (Tr..) I T parameter extraction

More information

Charge-storage related parameter calculation for Si and SiGe bipolar transistors from device simulation

Charge-storage related parameter calculation for Si and SiGe bipolar transistors from device simulation Charge-storage related parameter calculation for Si and SiGe bipolar transistors from device simulation M. Schroter ),) and H. Tran ) ) ECE Dept., University of California San Diego, La Jolla, CA, USA

More information

Status of HICUM/L2 Model

Status of HICUM/L2 Model Status of HICUM/L2 Model A. Pawlak 1), M. Schröter 1),2), A. Mukherjee 1) 1) CEDIC, University of Technology Dresden, Germany 2) Dept. of Electrical and Computer Engin., University of Calif. at San Diego,

More information

DISCRETE SEMICONDUCTORS DATA SHEET. BFG541 NPN 9 GHz wideband transistor. Product specification File under Discrete Semiconductors, SC14

DISCRETE SEMICONDUCTORS DATA SHEET. BFG541 NPN 9 GHz wideband transistor. Product specification File under Discrete Semiconductors, SC14 DISCRETE SEMICONDUCTORS DATA SHEET BFG4 File under Discrete Semiconductors, SC4 September 99 BFG4 FEATURES High power gain Low noise figure High transition frequency Gold metallization ensures excellent

More information

A Novel Method for Transit Time Parameter Extraction. Taking into Account the Coupling Between DC and AC Characteristics

A Novel Method for Transit Time Parameter Extraction. Taking into Account the Coupling Between DC and AC Characteristics A Novel Method for Transit Time Parameter Extraction Taking into Account the Coupling Between DC and AC Characteristics Dominique BEGE and Didier CELI STMicroelectronics, 850, rue jean Monnet F-38926 Cedex

More information

Methodology for Bipolar Model Parameter Extraction. Tzung-Yin Lee and Michael Schröter February 5, TYL/MS 2/5/99, Page 1/34

Methodology for Bipolar Model Parameter Extraction. Tzung-Yin Lee and Michael Schröter February 5, TYL/MS 2/5/99, Page 1/34 Methodology for Bipolar Model Parameter Extraction Tzung-Yin Lee and Michael Schröter February 5, 1999 TYL/MS 2/5/99, Page 1/34 Outline General Remarks Brief overview of TRADICA Parameter extraction flowchart

More information

Investigation of New Bipolar Geometry Scaling Laws

Investigation of New Bipolar Geometry Scaling Laws Investigation of New Bipolar Geometry Scaling Laws D. CELI 20 th Bipolar Arbeitskreis Munich, October 2007 Purpose Robust and high-performance RF circuit design need optimization of transistors. Therefore

More information

TCAD setup for an advanced SiGe HBT technology applied to the HS, MV and HV transistor versions

TCAD setup for an advanced SiGe HBT technology applied to the HS, MV and HV transistor versions TCAD setup for an advanced SiGe HBT technology applied to the HS, MV and HV transistor versions T. Rosenbaum 1,2,3, D. Céli 1, M. Schröter 2, C. Maneux 3 Bipolar ArbeitsKreis München, Germany, November

More information

Semiconductor Device Simulation

Semiconductor Device Simulation motivation and target applications compact model development under conditions relevant for circuit design development of test structures and measurement methods (fast) predicting device performance and

More information

MEXTRAM (level 504) the Philips model for bipolar transistors

MEXTRAM (level 504) the Philips model for bipolar transistors MEXTRAM (level 504) the Philips model for bipolar transistors Jeroen Paasschens, Willy Kloosterman, Ramses van der Toorn FSA modeling workshop 2002 Philips Electronics N.V. 2002 apple PHILIPS Philips Research

More information

BEOL-investigation on selfheating and SOA of SiGe HBT

BEOL-investigation on selfheating and SOA of SiGe HBT BEOL-investigation on selfheating and SOA of SiGe HBT Rosario D Esposito, Sebastien Fregonese, Thomas Zimmer To cite this version: Rosario D Esposito, Sebastien Fregonese, Thomas Zimmer. BEOL-investigation

More information

13. Bipolar transistors

13. Bipolar transistors Technische Universität Graz Institute of Solid State Physics 13. Bipolar transistors Jan. 16, 2019 Technische Universität Graz Institute of Solid State Physics bipolar transistors npn transistor collector

More information

Modeling of Devices for Power Amplifier Applications

Modeling of Devices for Power Amplifier Applications Modeling of Devices for Power Amplifier Applications David E. Root Masaya Iwamoto John Wood Contributions from Jonathan Scott Alex Cognata Agilent Worldwide Process and Technology Centers Santa Rosa, CA

More information

Circle the one best answer for each question. Five points per question.

Circle the one best answer for each question. Five points per question. ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions

More information

HICUM/L2 version 2.21: Release Notes

HICUM/L2 version 2.21: Release Notes HICUM/L2 version 2.21: Release Notes Chair for Electron Devices & Integrated Circuits (CEDIC) University of Technology Dresden, Germany M. Schroter and A. Chakravorty mschroter@ieee.org http://www.iee.et.tu-dresden.de/iee/eb/

More information

Homework Assignment 08

Homework Assignment 08 Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

More information

HICUM/L2 version 2.2: Summary of extensions and changes

HICUM/L2 version 2.2: Summary of extensions and changes HICUM/L2 version 2.2: Summary of extensions and changes M. Schroter Chair for Electron Devices & Integrated Circuits Dept. of Electrical and Computer Engineering (CEDIC) University of Technology Dresden,

More information

Electronic Circuits Summary

Electronic Circuits Summary Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

More information

The PSP compact MOSFET model An update

The PSP compact MOSFET model An update The PSP compact MOSFET model An update Gert-Jan Smit, Andries Scholten, D.B.M. Klaassen NXP Semiconductors Ronald van Langevelde Philips Research Europe Gennady Gildenblat, Weimin Wu, Xin Li, Amit Jha,

More information

Thermal Capacitance cth its Determination and Influence on Transistor and Circuit Performance

Thermal Capacitance cth its Determination and Influence on Transistor and Circuit Performance Thermal Capacitance cth its Determination and Influence on Transistor and Circuit Performance Gerhard G. Fischer IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany IHP Im Technologiepark 25 15236

More information

Bipolar Junction Transistor (BJT) - Introduction

Bipolar Junction Transistor (BJT) - Introduction Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification

More information

ELEC 3908, Physical Electronics, Lecture 19. BJT Base Resistance and Small Signal Modelling

ELEC 3908, Physical Electronics, Lecture 19. BJT Base Resistance and Small Signal Modelling ELEC 3908, Physical Electronics, Lecture 19 BJT Base Resistance and Small Signal Modelling Lecture Outline Lecture 17 derived static (dc) injection model to predict dc currents from terminal voltages This

More information

DISCRETE SEMICONDUCTORS DATA SHEET. BFS520 NPN 9 GHz wideband transistor. Product specification File under Discrete Semiconductors, SC14

DISCRETE SEMICONDUCTORS DATA SHEET. BFS520 NPN 9 GHz wideband transistor. Product specification File under Discrete Semiconductors, SC14 DISCRETE SEMICONDUCTORS DATA SHEET BFS File under Discrete Semiconductors, SC4 September 99 BFS FEATURES High power gain Low noise figure High transition frequency Gold metallization ensures excellent

More information

Chapter 2. - DC Biasing - BJTs

Chapter 2. - DC Biasing - BJTs Chapter 2. - DC Biasing - BJTs Objectives To Understand : Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented

More information

DISCRETE SEMICONDUCTORS DATA SHEET. BFR106 NPN 5 GHz wideband transistor. Product specification File under Discrete Semiconductors, SC14

DISCRETE SEMICONDUCTORS DATA SHEET. BFR106 NPN 5 GHz wideband transistor. Product specification File under Discrete Semiconductors, SC14 DISCRETE SEMICONDUCTORS DATA SHEET File under Discrete Semiconductors, SC14 September 1995 DESCRIPTION PINNING NPN silicon planar epitaxial transistor in a plastic SOT3 envelope. It is primarily intended

More information

ELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and Self-Heating

ELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and Self-Heating ELEC 3908, Physical Electronics, Lecture 18 The Early Effect, Breakdown and Self-Heating Lecture Outline Previous 2 lectures analyzed fundamental static (dc) carrier transport in the bipolar transistor

More information

Device Physics: The Bipolar Transistor

Device Physics: The Bipolar Transistor Monolithic Amplifier Circuits: Device Physics: The Bipolar Transistor Chapter 4 Jón Tómas Guðmundsson tumi@hi.is 2. Week Fall 2010 1 Introduction In analog design the transistors are not simply switches

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

Investigation of Ge content in the BC transition region with respect to transit frequency

Investigation of Ge content in the BC transition region with respect to transit frequency Investigation of Ge content in the BC transition region with respect to transit frequency P.M. Mans (1),(2), S. Jouan (1), A. Pakfar (1), S. Fregonese (2), F. Brossard (1), A. Perrotin (1), C. Maneux (2),

More information

Chapter 2 - DC Biasing - BJTs

Chapter 2 - DC Biasing - BJTs Objectives Chapter 2 - DC Biasing - BJTs To Understand: Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented

More information

Whereas the diode was a 1-junction device, the transistor contains two junctions. This leads to two possibilities:

Whereas the diode was a 1-junction device, the transistor contains two junctions. This leads to two possibilities: Part Recall: two types of charge carriers in semiconductors: electrons & holes two types of doped semiconductors: n-type (favor e-), p-type (favor holes) for conduction Whereas the diode was a -junction

More information

Didier CELI, 22 nd Bipolar Arbeitskreis, Würzburg, October 2009

Didier CELI, 22 nd Bipolar Arbeitskreis, Würzburg, October 2009 HICUM/L0 v1.2: Application to Millimeter Wave Devices Didier CELI, 22 nd Bipolar Arbeitskreis, Würzburg, October 2009 Outline Purpose ariation of reverse Early effect with the evolution of technologies

More information

DISCRETE SEMICONDUCTORS DATA SHEET. BLW96 HF/VHF power transistor

DISCRETE SEMICONDUCTORS DATA SHEET. BLW96 HF/VHF power transistor DISCRETE SEMICONDUCTORS DATA SHEET August 1986 DESCRIPTION N-P-N silicon planar epitaxial transistor intended for use in class-a, AB and B operated high power industrial and military transmitting equipment

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

At point G V = = = = = = RB B B. IN RB f

At point G V = = = = = = RB B B. IN RB f Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F

More information

DC and AC modeling of minority carriers currents in ICs substrate

DC and AC modeling of minority carriers currents in ICs substrate DC and AC modeling of minority carriers currents in ICs substrate Camillo Stefanucci, Pietro Buccella, Maher Kayal and Jean-Michel Sallese Swiss Federal Institute of Technology Lausanne, Switzerland MOS-AK

More information

KH600. 1GHz, Differential Input/Output Amplifier. Features. Description. Applications. Typical Application

KH600. 1GHz, Differential Input/Output Amplifier. Features. Description. Applications. Typical Application KH 1GHz, Differential Input/Output Amplifier www.cadeka.com Features DC - 1GHz bandwidth Fixed 1dB (V/V) gain 1Ω (differential) inputs and outputs -7/-dBc nd/3rd HD at MHz ma output current 9V pp into

More information

DISCRETE SEMICONDUCTORS DATA SHEET. BFQ19 NPN 5 GHz wideband transistor. Product specification File under Discrete Semiconductors, SC14

DISCRETE SEMICONDUCTORS DATA SHEET. BFQ19 NPN 5 GHz wideband transistor. Product specification File under Discrete Semiconductors, SC14 DISCRETE SEMICONDUCTORS DATA SHEET File under Discrete Semiconductors, SC14 September 1995 DESCRIPTION PINNING NPN transistor in a SOT89 plastic envelope intended for application in thick and thin-film

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 105: Microelectronic Devices and Circuits Spring 2008 MIDTERM EXAMINATION #1 Time

More information

EE105 Fall 2014 Microelectronic Devices and Circuits

EE105 Fall 2014 Microelectronic Devices and Circuits EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)

More information

Lecture 38 - Bipolar Junction Transistor (cont.) May 9, 2007

Lecture 38 - Bipolar Junction Transistor (cont.) May 9, 2007 6.72J/3.43J - Integrated Microelectronic Devices - Spring 27 Lecture 38-1 Lecture 38 - Bipolar Junction Transistor (cont.) May 9, 27 Contents: 1. Non-ideal effects in BJT in FAR Reading material: del Alamo,

More information

Volterra Series: Introduction & Application

Volterra Series: Introduction & Application ECEN 665 (ESS : RF Communication Circuits and Systems Volterra Series: Introduction & Application Prepared by: Heng Zhang Part of the material here provided is based on Dr. Chunyu Xin s dissertation Outline

More information

ECE-305: Spring 2018 Final Exam Review

ECE-305: Spring 2018 Final Exam Review C-305: Spring 2018 Final xam Review Pierret, Semiconductor Device Fundamentals (SDF) Chapters 10 and 11 (pp. 371-385, 389-403) Professor Peter Bermel lectrical and Computer ngineering Purdue University,

More information

BJT Biasing Cont. & Small Signal Model

BJT Biasing Cont. & Small Signal Model BJT Biasing Cont. & Small Signal Model Conservative Bias Design (1/3, 1/3, 1/3 Rule) Bias Design Example Small-Signal BJT Models Small-Signal Analysis 1 Emitter Feedback Bias Design R B R C V CC R 1 R

More information

Self-heat Modeling of Multi-finger n-mosfets for RF-CMOS Applications

Self-heat Modeling of Multi-finger n-mosfets for RF-CMOS Applications Self-heat Modeling of Multi-finger n-mosfets for RF-CMOS Applications Hitoshi Aoki and Haruo Kobayashi Faculty of Science and Technology, Gunma University (RMO2D-3) Outline Research Background Purposes

More information

ESE319 Introduction to Microelectronics. Output Stages

ESE319 Introduction to Microelectronics. Output Stages Output Stages Power amplifier classification Class A amplifier circuits Class A Power conversion efficiency Class B amplifier circuits Class B Power conversion efficiency Class AB amplifier circuits Class

More information

Biasing BJTs CHAPTER OBJECTIVES 4.1 INTRODUCTION

Biasing BJTs CHAPTER OBJECTIVES 4.1 INTRODUCTION 4 DC Biasing BJTs CHAPTER OBJECTIVES Be able to determine the dc levels for the variety of important BJT configurations. Understand how to measure the important voltage levels of a BJT transistor configuration

More information

Transistor Characteristics and A simple BJT Current Mirror

Transistor Characteristics and A simple BJT Current Mirror Transistor Characteristics and A simple BJT Current Mirror Current-oltage (I-) Characteristics Device Under Test DUT i v T T 1 R X R X T for test Independent variable on horizontal axis Could force current

More information

Chapter 5. BJT AC Analysis

Chapter 5. BJT AC Analysis Chapter 5. Outline: The r e transistor model CB, CE & CC AC analysis through r e model common-emitter fixed-bias voltage-divider bias emitter-bias & emitter-follower common-base configuration Transistor

More information

Homework Assignment 09

Homework Assignment 09 Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

ECE 145A/218A Power Amplifier Design Lectures. Power Amplifier Design 1

ECE 145A/218A Power Amplifier Design Lectures. Power Amplifier Design 1 Power Amplifiers; Part 1 Class A Device Limitations Large signal output match Define efficiency, power-added efficiency Class A operating conditions Thermal resistance We have studied the design of small-signal

More information

EKV MOS Transistor Modelling & RF Application

EKV MOS Transistor Modelling & RF Application HP-RF MOS Modelling Workshop, Munich, February 15-16, 1999 EKV MOS Transistor Modelling & RF Application Matthias Bucher, Wladek Grabinski Electronics Laboratory (LEG) Swiss Federal Institute of Technology,

More information

Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits

Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 10, OCTOBER 2003 1297 Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits Peng Li, Student

More information

DISCRETE SEMICONDUCTORS DATA SHEET. BLW33 UHF linear power transistor

DISCRETE SEMICONDUCTORS DATA SHEET. BLW33 UHF linear power transistor DISCRETE SEMICONDUCTORS DATA SHEET August 1986 DESCRIPTION N-P-N silicon planar epitaxial transistor primarily intended for use in linear u.h.f. amplifiers for television transmitters and transposers.

More information

DATA SHEET. PRF957 UHF wideband transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Mar 01.

DATA SHEET. PRF957 UHF wideband transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Mar 01. DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D1 Supersedes data of 1999 Mar 1 1999 Jul 3 FEATURES PINNING Small size Low noise Low distortion High gain Gold metallization ensures excellent reliability.

More information

Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER

Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Outline. Introduction 2. CMOS multi-stage voltage amplifier 3. BiCMOS multistage voltage amplifier 4. BiCMOS current buffer 5. Coupling amplifier

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

DISCRETE SEMICONDUCTORS DATA SHEET. BFQ67W NPN 8 GHz wideband transistor. Product specification File under Discrete Semiconductors, SC14

DISCRETE SEMICONDUCTORS DATA SHEET. BFQ67W NPN 8 GHz wideband transistor. Product specification File under Discrete Semiconductors, SC14 DISCRETE SEMICONDUCTORS DATA SHEET File under Discrete Semiconductors, SC4 September 99 FEATURES PINNING High power gain Low noise figure High transition frequency Gold metallization ensures excellent

More information

Inducing Chaos in the p/n Junction

Inducing Chaos in the p/n Junction Inducing Chaos in the p/n Junction Renato Mariz de Moraes, Marshal Miller, Alex Glasser, Anand Banerjee, Ed Ott, Tom Antonsen, and Steven M. Anlage CSR, Department of Physics MURI Review 14 November, 2003

More information

Lecture 17 - The Bipolar Junction Transistor (I) Forward Active Regime. April 10, 2003

Lecture 17 - The Bipolar Junction Transistor (I) Forward Active Regime. April 10, 2003 6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 17-1 Lecture 17 - The Bipolar Junction Transistor (I) Contents: Forward Active Regime April 10, 2003 1. BJT: structure and basic operation

More information

CHAPTER.4: Transistor at low frequencies

CHAPTER.4: Transistor at low frequencies CHAPTER.4: Transistor at low frequencies Introduction Amplification in the AC domain BJT transistor modeling The re Transistor Model The Hybrid equivalent Model Introduction There are three models commonly

More information

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

More information

Runtime Analysis of 4 VA HiCuM Versions with and without Internal Solver

Runtime Analysis of 4 VA HiCuM Versions with and without Internal Solver Runtime Analysis of 4 VA HiCuM Versions with and without Internal Solver Didier Céli, Jean Remy 28 th ArbeitsKreis Bipolar - Letter Session Unterpremstaetten, Austria, November 5/6, 215 dm23a.15 Outline

More information

Problem 9.20 Threshold bias for an n-channel MOSFET: In the text we used a criterion that the inversion of the MOSFET channel occurs when V s = ;2 F w

Problem 9.20 Threshold bias for an n-channel MOSFET: In the text we used a criterion that the inversion of the MOSFET channel occurs when V s = ;2 F w Prof. Jasprit Singh Fall 2001 EECS 320 Homework 11 The nals for this course are set for Friday December 14, 6:30 8:30 pm and Friday Dec. 21, 10:30 am 12:30 pm. Please choose one of these times and inform

More information

DISCRETE SEMICONDUCTORS DATA SHEET. BFQ149 PNP 5 GHz wideband transistor. Product specification File under Discrete Semiconductors, SC14

DISCRETE SEMICONDUCTORS DATA SHEET. BFQ149 PNP 5 GHz wideband transistor. Product specification File under Discrete Semiconductors, SC14 DISCRETE SEMICONDUCTORS DATA SHEET File under Discrete Semiconductors, SC14 September 1995 DESCRIPTION PINNING PNP transistor in a SOT89 envelope. It is intended for use in UHF applications such as broadband

More information

DISCRETE SEMICONDUCTORS DATA SHEET. BLU86 UHF power transistor

DISCRETE SEMICONDUCTORS DATA SHEET. BLU86 UHF power transistor DISCRETE SEMICONDUCTORS DATA SHEET September 1991 FEATURES SMD encapsulation Emitter-ballasting resistors for optimum temperature profile Gold metallization ensures excellent reliability. DESCRIPTION NPN

More information

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom ID # NAME EE-255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.

More information

ECE-342 Test 2 Solutions, Nov 4, :00-8:00pm, Closed Book (one page of notes allowed)

ECE-342 Test 2 Solutions, Nov 4, :00-8:00pm, Closed Book (one page of notes allowed) ECE-342 Test 2 Solutions, Nov 4, 2008 6:00-8:00pm, Closed Book (one page of notes allowed) Please use the following physical constants in your calculations: Boltzmann s Constant: Electron Charge: Free

More information

CMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process

CMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process EECS240 Spring 202 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS Technology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 Today s Lecture

More information

Structured Electronic Design. Building the nullor: Distortion

Structured Electronic Design. Building the nullor: Distortion Structured Electronic Design Building the nullor: Distortion 1 Specs 1 N verification Topology Best nullor implementation Voltage and current swing Power consumption FINAL Noise level All stages maximal

More information

KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D II )

KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D II ) KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D II ) Most of the content is from the textbook: Electronic devices and circuit theory,

More information

A High-Order Compensated Op-amp-less Bandgap Reference with 39 ppm/ºc over -260~125 ºC Temperature Range and -50 db PSRR

A High-Order Compensated Op-amp-less Bandgap Reference with 39 ppm/ºc over -260~125 ºC Temperature Range and -50 db PSRR A High-Order Compensated Op-amp-less Bandgap Reference with 39 ppm/ºc over -26~125 ºC Temperature Range and -5 db PSRR Hechen Wang, Student Member, IEEE, Fa Foster Dai, Fellow, IEEE, and Michael Hamilton,

More information

Type Marking Pin Configuration Package BFR93AW R2s 1=B 2=E 3=C SOT323

Type Marking Pin Configuration Package BFR93AW R2s 1=B 2=E 3=C SOT323 Low Noise Silicon Bipolar RF Transistor For low distortion amplifiers and oscillators up to GHz at collector currents from 5 ma to 30 ma 3 Pbfree (RoHS compliant) and halogenfree package with visible leads

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 21: Bipolar Junction Transistor Administrative Midterm Th 6:30-8pm in Sibley Auditorium Covering everything

More information

Semiconductor Device Modeling and Characterization EE5342, Lecture 15 -Sp 2002

Semiconductor Device Modeling and Characterization EE5342, Lecture 15 -Sp 2002 Semiconductor Device Modeling and Characterization EE5342, Lecture 15 -Sp 2002 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/ L15 05Mar02 1 Charge components in the BJT From Getreau,

More information

55:041 Electronic Circuits The University of Iowa Fall Exam 2

55:041 Electronic Circuits The University of Iowa Fall Exam 2 Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.

More information

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,

More information

Biasing the CE Amplifier

Biasing the CE Amplifier Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

More information

Workshop WMB. Noise Modeling

Workshop WMB. Noise Modeling Workshop WMB Noise Modeling Manfred Berroth, Markus Grözing, Stefan Heck, Alexander Bräckle University of Stuttgart, Germany WMB (IMS) Parameter Extraction Strategies For Compact Transistor Models IMS

More information

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D. Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT-3 Department of Electrical and Computer Engineering Winter 2012 1. A common-emitter amplifier that can be represented by the following equivalent circuit,

More information

Lateral SiC bipolar junction transistors for high current IC driver applications

Lateral SiC bipolar junction transistors for high current IC driver applications KTH ROYAL INSTITUTE OF TECHNOLOGY Lateral SiC bipolar junction transistors for high current IC driver applications Carl-Mikael Zetterling M. Ekström, H. Elahipanah, M. W. Hussain, K. Jacobs, S. Kargarrazi,

More information

BJT Biasing Cont. & Small Signal Model

BJT Biasing Cont. & Small Signal Model BJT Biasing Cont. & Small Signal Model Conservative Bias Design Bias Design Example Small Signal BJT Models Small Signal Analysis 1 Emitter Feedback Bias Design Voltage bias circuit Single power supply

More information

Spring Semester 2012 Final Exam

Spring Semester 2012 Final Exam Spring Semester 2012 Final Exam Note: Show your work, underline results, and always show units. Official exam time: 2.0 hours; an extension of at least 1.0 hour will be granted to anyone. Materials parameters

More information

A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load

A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load Presented by Tan Xiao Liang Supervisor: A/P Chan Pak Kwong School of Electrical and Electronic Engineering 1 Outline

More information

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +

More information

R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition. Figures for Chapter 6

R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition. Figures for Chapter 6 R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition Figures for Chapter 6 Free electron Conduction band Hole W g W C Forbidden Band or Bandgap W V Electron energy Hole Valence

More information

Including the Effect of Temperature Sukla Basu*, Parijat Sarkar** Received 24 December 2010, accepted 3 January 2011

Including the Effect of Temperature Sukla Basu*, Parijat Sarkar** Received 24 December 2010, accepted 3 January 2011 Journal of Electron Devices, Vol. 9, 11, pp. 35-39 JED [ISSN: 168-347 ] Journal of Electron Devices www.jeldev.org Analytical Modeling of AlGaAs/GaAs and Si/SiGe HBTs Including the Effect of Temperature

More information