Extraction of the substrate complex for HBT/BJT transistors

Transcription

1 -May- Extraction of the substrate complex for HBT/BJT transistors An extended substrate circuit Fig. which is a streamlined version of that proposed in [] for modeling deep trench isolated structures was introduced in hicumlv. []. The additional eventually bias dependent component C SCp represents the capacitance of the deep trench. c s C SCp RCX C su ci C js si R su Fig. New substrate complex in hicumlv. In the first part an extraction theory will be proposed for the substrate network. Extraction examples are given originated from synthetic data and from a physically measured device. A scaling example is also demonstrated on a measured geometry matrix.. Model analysis The driving point admittance between (c,s) can be obtained with Cp = as C SCp s = jω and for breivity, s( Cjs Rsu Csu + Rcx Cp Cjs + Cp Rsu Csu + Rsu Cp Cjs) + ( Cjs + Cp Rcx Cp Cjs Rsu Csu) Y = s s (Rcx Cjs + Rsu Csu + Rsu Cjs) + ( ω Rcx Cjs Rsu Csu) Introducing one arrives at τ τ C xs js = Rcx Cjs Rsu Csu = Rsux Cjs + Rsu Csu; τ js τ = ( ωτ τ = ) [ ( ωτ ) ] ω () Cjs + Cp ω Rcx Cp Cjs Rsu Csu Cjs = = Cp + ( ωτ ) ( ωτ xs xs Rcx Cp Cjs + Rsu ( Cp Cjs + Cp Csu + Cjs Csu) Y Cjs + Cp + sτ This can be manipulated as follows + s τ + s τ + s ( τ τ) Y = s C = s C = s C + s τ + s τ ω C ( τ τ )( s τ) Y = s C + = s C + ( ω τ) The real part reads R Rsux = Rsu + Rcx xs xs ) () = s C () + sτ ω C ( τ τ ) + + s τ ω C ( τ τ ) ω C ( τ τ ) τ + + ( ω τ) + ( ω τ) ω C ( τ τ ) ( Y ) = () + ( ω τ)

2 -May- and consequently, I( Y ) = C τ R( Y ) () ω Substutions from () result in I( Y ) = Cp + [ Cjs τ ( Y )] js R ω ( ωτ xs ) and using the (small) correction factor ( ωτ xs ) Ccorr = [ Cjs τ ( Y )] js R () ( ωτ xs ) one arrives at I( Y ) Ccorr = Ctot τ js R( Y ) () ω where C tot = Cjs + Cscp () Initially the linear regression is solved by assuming C corr =. The trench capacitance part C is separated from the total by optimization an additive constant to the capacitance SCp equation. Though this is a weak process for a realiable determination of the trench capacitance it does not introduce an appreciable error since C corr is small. A second regression w.r.t. the known Cjs(Vsc) yields Csu and Rsux from the additional linear regression τ = Rsux Cjs( Vsc) + Rsu Csu () js Having arrived here τ xs = Rcx Cjs Rsu Csu can be computed with the extracted values and the iteration can be performed with the updated correction capacitance known from () and () ( k ) ( k + ) ( ωτ xs ) I( Y ) ( k) ( k C = ) corr C ( k) SCp Ccorr () ( ωτ xs ) ω The influence of Rcx is typically small and the iteration usually terminates in a few steps if it is performed at all. Practically the process is placed in a for...end loop with two execution cycles. The linear nature of () allows a visual compliance test for deciding if the measurements describe the structure of Fig.. If so, there must be a linear section on the I (Y ) vs. R (Y ) plot. Taking the reciprocal of () one obtains I( Z) = + τ R( Z) () ω C Owing to the complexity of the time constant τ this equation is not suitable for parameter extraction. Nevertheless this form can also be used for testing compliance of the given transistor to Fig.. Conventionally the substrate admittance as a basis function is available from cold measurements Y = y + y () Formula () utilizes the whole information included in the measured complex admittance Y. The correlating content of the real and imaginary parts is fully transformed to the coefficients C tot = C js + CSCp and τ js linked only by the junction capacitance C js. The primary model parameters cjs, zs, vds,vpts, cscp, rsu, csu (plus the additial parameters if C SCp is bias dependent) can be all determined from the resulting coefficient functions by the demonstrated methods.

3 -May- At decreasing frequencies R (Y ) () vanishes and I(Y ) ω gradually levels off to the total capacitance. This flat region is typically not directly accessible due to elevated measurement noise below appr. GHz. Equation () returns this value as a zero intercept avoiding this serious disadvantage of the former substrate extraction attempts. Separation of Cscp and the junction capacitance Cjs can be performed over a set of devices with different geometries. This allows the determination of a bias dependent trench capacitance as well. When a constant Cscp can be assumed an alternative way of separation is offered by the rearrangement of () Ctot = Cz τ js () Rsux A linear regression Ctot vs. τ js yields Rsux and the zero intercept Rsu Cz = Cscp Csu Cscp Csu () Rsux The split can be performed by utilizing that Csu is area, Cscp is perimeter dependent. Alternatively () allows a robust optimization of Cscp utilizing the feedback from the fit of the model to the basis function. The various extraction methodologies will be discussed in detail and illustrated with diagrams in the experimental section.. Distributed substrates It is a serious challenge at modeling deep trench isolated processes that the substrate network tends to be distributed. For demonstration purposes we select the approach of [] which analysed a deep trench isolated bipolar process. The black curve on the right pane of Fig. (Fig. R) represents the compliance test () on the distributed R-C line formula cited in [] c Y = jω tanh( jω r c ) = ( s τ ) tanh( s τ ); τ = r c () r r with r and c as the total resistance and capacitance of the line. Distributed RC line, virtual capacitance and real part - Distributed RC line, compliance test. I(Y)/ω [ff] lumped, ~ω distributed ~ ω R(Y) [ms] I(Y)/ω [ff] ~-R(Y)... R(Y) x - Fig. Compliance test on a distributed transmission line The left pane (Fig. L) shows two disctinct slopes for the real part. At low frequencies a lumped behaviour is reflected by a slope of db/d then above a breakpoint of ~GHz the r=kω c=ff ~/R(Y).. Im(Y) [ms]

4 -May- slope reduces to db/d as governed by the distributed nature. Accordingly, we can refer to the first section as the lumped, to the second one as the distributed branch. Taylor expansion of () for small frequencies yields I( Y ) τ = c R( Y ) () ω Hence the compliance condition prevails along the lumped branch and the truncated- model of Fig. can be extracted this region by the methods described later. The distributed branch is incompliant to Fig. since at high frequencies ωτ I ( Y ) = R( Y ) = () r This represents a straight line shown in blue on Fig. R. The compliance curve on the left axis I( Y ) τ approximates = that is, a hyperbola in this domain. ω R( Y ) r () can be expanded to fractional form using the power series of the sinh() and cosh() functions: n s τ ( s τ ) ( s τ ) L+ + L!! [ ( n + ) ]! Y = s c () n s τ ( s τ ) ( s τ ) L+ + L!! (n)! At medium-small frequencies () is returned which represents the lumped branch in correspondence to (). The results above hold for the simplest distributed line while the actual substrate equivalent can be more complicated. Nevertheless the fractional form () prevails just with different terms. It is expected that I (Y ) / ω vs. R (Y ) on the linear plane will provide similar shapes than the left axis curve shown on the right pane of Fig.. It can be concluded that a linear-to hyperbolic boomerang shaped compliance curve must be the indication of distributed substrates.. A new basis function Y Often, strange characteristics can be found by inspecting devices from different processes. These are mainly manifested by the irregular, unexpected shape of the conductance curves. For a possible explanation and for finding a fix we start from () which is the definition of the extraction basis. First of all, y + y is not a two port parameter. The combination is aimed at decoupling the collector capacitance with the assumption that the transistor is a pure Π network. Fig. shows consecutive equivalent transformations on the original HICUM equivalent in cold mode. Star-delta (Y- ) conversions are adopted for the encircled nodes until the last, lower-right network is arrived at. During the process the transformed elements are merged with the parallel branches resulting in the left (L), right (R) and top (T) components in each numbered step. It is seen that despite the intended elimination of the transfer element by the combination Y = y + y there remains an undesired component y R connected parallel to the substrate structure. The distorting effect is increasing with frequency. At rbx=rbi= nodes b, bp and bi collapse and Y = y + y provides the desired pure substrate complex. This corresponds to small frequencies when the resistances are negligible to the reactive impedances. On the other hand at high frequencies we have the influence of practically all elements left to node ci.

5 -May- cbcx b cbcx rbx bp rbi crbi bi cjci ci cjs rcx c cbcx b cbcx rbx bp bi cjci ci yt cjs rcx c cbepar cbepar cjep ei re cjei rsu csu cscp cbepar cbepar yl yr rsu csu cscp cbcx cbcx b rbx cbepar cbepar hicumlv. cold yt yl yr rsu cjs csu rcx c cscp st star-delta conversion and merging b rcx c yt cjs yl yr rsu csu cscp nd star-delta conversion and merging Y=y +y includes yr (rcx is small) Fig. The HICUM structure in cold mode and its conversions There is an even more serious problem though. It is known from passive network theory that the port admittances - as two-terminal devices - are positive real (PR) functions characterized by R( y ) ; R( y ) on the whole complex frequency plane. This is not so for the transfer admittance for which theory can only state the inequality R ( y ) R( y) R( y ) or () R( y) R( y ) R( y ) R( y) R( y ) The condition allows negative real parts that is, a non PR transfer function as shown on the very simple example of Fig.. There appears a negative conductance in the transfer branch of the Π equivalent with a value of / r at high frequencies. The imaginary part correctly returns c / corresponding to the original T. c/ c c -/r r yp yp Fig. T-Π conversion Assuming a network Π (or T) type when it is actually not can easily lead to this issue. A typical such case is parameter determination from cold state. If y is strongly non PR it can make Y = y + y also non PR. More precisely, adding R ( y ) to () we arrive at the constraint [ R( y ) R( y ) ] R( Y ) R( y )[ R( y ) + R( )] R( y ) y () Hence the conventional basis function defined by () can become non-positive real when R ( y) > R( y ) which makes parameter extraction impossible. The real part from a physical device is shown in absolute value on Fig. L but the downward peaks clearly identify the points where the conductance turns negative. It is directly seen on the compliance curves of Fig. R with the real part on the x-axis.

6 -May- I(y+y)/ω [ff] non PR Y abs(r(y+y)) [ms] I(y+y)/om [ff] Vsc=-.V Vsc=.V non PR Y.GHz <= f <=.GHz R(y+y) [ms] Fig. A physical device showing a non PR basis function Y Consequently Y in () is not generally applicable for the extraction of the substrate network. It is so because the real part of the possibly non PR y is unnecessarily included in the cancellation of the transfer capacitance. While this is not a problem at extracting Cje and Cjc from cold the disturbance may make it impossible to determine the substrate resistance. The issue can be resolved by replacing the basis function () with Y = y + j I( y ) () which must always be a PR function. The capacitance curves are unchanged on Fig. L while the negative sections dispappeared from the conductance curves. The compliance plots on Fig. R exhibit the expected behaviour making it possible a succesful parameter extraction by the proposed new methods. I(y+y)/ω [ff] non PR Y, corrected - - ( y R(y) [ms] I(y+y)/om [ff] non PR Y, corrected.ghz <= f <=.GHz Vsc=-.V Vsc=.V..... R(y) [ms] Fig. Using Y = y + j I ) on the device of Fig.. Examples The following series of experiments have been performed and presented. - Group I. The extraction concept is verified on a synthetic dataset of machine precision ( digits). Mesurement errors are imitated by rounding the simulated results to, and digits. This makes it possible to estimate the minimal measurement readout which still allows the identification of model compliance. - Group II. A physically measured single device will be extracted here. Moreover a highly advised extraction technique is introduced in this example. - Group III. The geometry scaling proces will be presented on a set of devices with various geometries. Disturbing issues are discussed in detail. It is shown that the

7 -May- proposed extraction methods provide reasonably good scaled models even at model incompliance due to distributed effects.. Preferred extraction methods Decide by the matrix-vector technique ()...() if the trench capacitance is constant or bias dependent ( Fig. III.) a. constant Cscp. Mark at least points on the lumped branch of the compliance curve and make linear regressions for Ctot and τ js for each bias point of all devices (Fig. Ia, Fig. II etc.). Regression of Ctot by τ js yields the final Rsux and zero intercept Cz (Fig. II, III). Select a guessed Cscp max( Cz,) for calculating Csu = Cscp Cz and Cjs = Ctot Cscp.. Compute the structure of Fig. with the obtained parameters and compare the resulting curves to measurements (Fig. II-II). Optimize Cscp automatically on the marked points or manually by visual inspection in a heuristic way from. until the best fit is achieved.. If necessary perform scaling directly on the regressed parameters (Fig. III) b. bias dependent Cscp. Separate Cscp by the matrix-vector technique from Ctot using relatively large test transistors. Determine the perimeter specific cscp [ff/um] and its parameters vdsp, zsp, vptsp. Deembed the extraction data by the bias dependent perimeter capacitance at the measurement frequencies using Cscp=P*cscp and then deembed the series Rcx. Extract Cjs, Rsu and Csu by step a./ above (Ctot=Cjs, Rsux=Rsu, Csu=-Cz) observing that the master equation () holds for the former HICUM substrate as well. Summary - a unique equation has been derived for the extraction of the hicumlv. substrate complex - a new basis function has been introduced for substrate extraction - synthetic data with different round-off errors showed that a VNA readout of minimum digits is needed for reasonable results - the robustness of the method has been demonstrated by producing fully scalable substrate models within harsh incompliance conditions - the method as a compliance test detects the presence of distributed substrates - the rigorous extraction of the substrate elements may improve FMAX prediction [] - Failures of directly splitting Ctot imply that Cjs may absorb the eventual bias dependence of Cscp. It is proposed to start the extraction always with a constant Cscp - the generic nature of the new hicumlv. substrate model has been verified in that it is able to provide compromise models both for lumped and distributed substrates ACKNOWLEDGEMENT Thank is due to Didier Celi for his active participation in this project and providing the data for the extractions. Dr. Franz Sischka is acknowledged for his information on VNA accuracy/precision issues.

8 -May- I. Synthetic data hicumlv. synthetic hicumlv. synthetic I(y+y)/ω [ff] abs(r(y+y)) [ms] I(y+y)/ω [ff] R(y) [ms] - - Fig. I Testing the PR nature of the basis function - - The basis function () for synthetic data on Fig. IL has a non PR section above the second vertical markerline. The downward peaks at ~GHz witness that the condition R ( y) > R( y ) for () holds true. Therefore the new basis function () will be used for this (Fig. IR) and all subsequent extractions. a. Synthetic, digits (machine precision) I(y+y)/ω [ff] hicumlv. synthetic R(y) [ms] I(y+y)/om [ff] hicumlv. synthetic Vsc=-.V Vsc=.V.GHz <= f <=.GHz I(y+y)/ω [ff] - - Vsc=-.V Vsc=.V selected bias lines - f [GHz] R(y) [S] R(y) [ms] - - selected bias lines Vsc=-.V Vsc=.V - f [GHz] Fig. Ia Top: virtual capacitance and admittance (left), regression curves at three bias voltages (right). Simulation in cold (off state) mode: Vbe=V, Vsc=Vec=[-V, step.,.v] Bottom: selected bias curves

9 -May- The full simulated data is shown on the left pane. The feasibility window between the vertical marker lines selected for the extractions is also shown on the compliance plot as the interval covered by the curves. This is included in the standard HBT measurement frequency range of typically [.GHz...GHz]. The filled points have been used for linear regression. substrate capacitance extraction substrate resistance and capacitance regression Cjs [ff] cjs=.ff vds=.v zs=. cscp=.ff τ js [ps] rsu=.kω csu=.ff vd [V] cjs [ff] Fig. Ia Substrate and perimeter capacitance (left), substrate resistance and capacitance (right) b. Synthetic, rounded to digits I(y+y)/ω [ff] hicumlv. synthetic R(y) [ms] I(y+y)/om [ff] hicumlv. synthetic Vsc=-.V Vsc=.V.GHz <= f <=.GHz I(y+y)/ω [ff] - - selected bias lines Vsc=-.V Vsc=.V R(y) [S] R(y) [ms] - selected bias lines - f [GHz] - - Vsc=-.V Vsc=.V - f [GHz] Fig. Ib Top: virtual capacitance and admittance (left), regression curves at three bias voltages (right). Simulation in cold (off state) mode: Vbe=V, Vsc=Vec=[-V, step.,.v] Bottom: selected bias curves

10 -May- substrate capacitance extraction substrate resistance and capacitance regression Cjs [ff] cjs=.ff vds=.v zs=. cscp=.ff τ js [ps] rsu=.kω csu=.ff vd [V] cjs [ff] Fig. Ib Substrate and perimeter capacitance (left), substrate resistance and capacitance (right) c. Synthetic, rounded to digits I(y+y)/ω [ff] hicumlv. synthetic R(y) [ms] I(y+y)/om [ff] hicumlv. synthetic.ghz <= f <=.GHz Vsc=-.V Vsc=.V I(y+y)/ω [ff] - - selected bias lines Vsc=-.V Vsc=.V R(y) [S] R(y) [ms] selected bias lines - f [GHz] - - Vsc=-.V Vsc=.V - f [GHz] Fig. Ic Top: virtual capacitance and admittance (left), regression curves at three bias voltages (right). Simulation in cold (off state) mode: Vbe=V, Vsc=Vec=[-V, step.,.v] Bottom: selected bias curves

11 -May- substrate capacitance extraction substrate resistance and capacitance regression Cjs [ff] cjs=.ff vds=.v zs=. cscp=.ff τ js [ps] rsux=.kω csu=.ff vd [V] cjs [ff] Fig. Ic Substrate and perimeter capacitance (left), substrate resistance and capacitance (right) d. Synthetic, rounded to digits hicumlv. synthetic - hicumlv. synthetic.ghz <= f <=.GHz Vsc=-.V Vsc=.V I(y+y)/ω [ff] - - R(y) [ms] I(y+y)/om [ff] I(y+y)/ω [ff] - - selected bias lines Vsc=-.V Vsc=.V R(y) [S] R(y) [ms] selected bias lines - f [GHz] - - Vsc=-.V Vsc=.V - f [GHz] Fig. Id Top: virtual capacitance and admittance (left), regression curves at three bias voltages (right). Simulation in cold (off state) mode: Vbe=V, Vsc=Vec=[-V, step.,.v] Bottom: selected bias curves

12 -May- substrate capacitance extraction substrate resistance and capacitance regression cjs=.ff vds=.v zs=. cscp=.ff Cjs [ff] τ js [ps] rsu=-.kω csu=.ff vd [V] - cjs [ff] Fig. Id Substrate and perimeter capacitance (left), substrate resistance and capacitance (right) Evaluation of the Group I. results Table I. Parameter Card digits digits digits digits cjs [ff]..... vds [V]..... zs..... rsu [kω] csu [ff]..... cscp [ff]... cjs+cscp [ff]..... hicumlv. synthetic: comparision of simulation with extracted parameters I(y+y)/ω [ff] R(y) [ms] card extr. from digits data - extr. from digits data extr. from digits data Fig. I. Re-simulation with the extracted parameters inserted in the card. Bias: Vsc=.V, V -V top to bottom The synthetic data was re-simulated with the obtained parameters summarized in Table I. The results of Fig. I. confirm the extraction theory.

13 -May- The junction capacitance parameters stay reasonable even for the digits data. Really, the imaginary parts remain well recognizable in all investigated precisions. ( I starts always with the st Taylor term ω, while R begins either with constant or, as this case with the nd order ω ). Despite that the separation of Cscp was impossible at and below digits the total capacitance Cjs+Cscp is the same for all cases. The advantage of obtainig Ctot as a zero intercept mentioned on p. is apparent. Note also that the extracted substrate capacitance is approximately % of the card value at the digits data. It can be concluded that - the extraction of the Cjs parameters is quite robust with the proposed method - Cjs+Cscp have a dominant influence on the low frequency capacitance - a small Csu (see digits) suppresses the impact of Cjs at medium-high frequencies - measurements which exhibit a capacitance collapse into a bias independent filament like curve towards increasing frequencies (Fig. -) reflect small substrate capacitance. Rsu gets dominating Cjs in lack of the shunting Csu implying a nearly constant ohmic ci-si-s branch such cases The observations are in agreement with Table I_ showing the low and high frequency limits separated by the the knee frequency ω τ. = js Table I_. Regional asymptotes to Fig. (with Rcx=) ω τ R (Y ) I (Y ) = js ω << ω ( Rsu Cjs) Rsu ω = ω ω >> ω Rsu Rsu ω Cjs Cjs + Csu + Csu Cjs Cjs Cp + Cjs ( Cjs + Csu) ( ω Rsu Cjs) Cp + Cjs ( Cjs + Csu) Cp + Cjs Csu It is important to observe that the compliance identification is possible down to digits precision. It appears that a random type measurement noise does not inhibit the recognition of distributed substrates. II. Measured device from the BiCMOSMW STM process BiCMOSMW.xum SiGe HBT [] I(y+y)/ω [ff] Measured BiCMOSMW.xum R(y) [ms] I(y+y)/om [ff].... Measured BiCMOSMW.xum.GHz <= f <=.GHz Vsc=-.V Vsc=.V..... R(y) [ms]

14 -May- selected bias lines Vsc=-.V Vsc=.V - selected bias lines - I(y+y)/ω [ff] - - f [GHz] R(y) [S] - - Vsc=-.V Vsc=.V - - f [GHz] Fig. II Top: virtual capacitance and admittance (left), regression curves at three bias voltages (right). Simulation in cold (off state) mode: Vbe=V, Vsc=Vec=[-V, step.,.v] Bottom: selected bias curves Substrate junction capacitance extraction Substrate resistance and zero intercept capacitance regression.. Cjs [ff].. cjs=.ff vds=.v zs=. Ctot [ff].. Rsux=.kΩ Cz=.fF Cscp=.fF vd [V]. τ js [ps] Fig. II Substrate and perimeter capacitance (left), Cz and substrate resistance Rsux (right) Evaluation of the Group II. results The transistor is compliant to the hicumlv. substrate model as demonstrated by the wide linear sections on the top-right plot of Fig. II. The single transistor extraction did not make it possible to extract Cscp from the capacitance data. Therefore Rsux and Cz had been regressed by () and the best Cscp value was looked for heuristically using Csu = Cscp Cz from () and Cjs = Ctot Cscp until the best fit was found to selected measurement lines on the top left plot of Fig. II. Alternatively an optimization could also be adopted using the marked points at the cost of a more complex extraction environment. The Rsux-Cz regression on Fig. IIR is invariant, only the junction capacitance extraction shall be updated during the iterations due to Cjs=Ctot-Cscp. Table II_. Parameter Value Cjs ff. vds. zs. Cscp ff. Rsu kohm. Csu ff.

15 -May- Measured BiCMOSMW.xum Measured BiCMOSMW.xum - - I(y+y)/ω [ff] filled: extraction points - - R(y) [ms] I(y+y)/ω [ff] filled: extraction points - - R(y) [ms] Fig. II Heuristic adjustment of Cscp. Left: Cscp=fF, right: Cscp=fF. The optimal value was found to be Cscp=.fF with the result shown on Fig. IIL. Measured BiCMOSMW.xum hicumlv. synthetic I(y+y)/ω [ff] filled: extraction points R(y) [ms] I(y+y)/ω [ff] filled: extraction points Fig. II. Comparision of measurements to the substrate structure of hicumlv. computed with the parameters of Table II_ (left), synthetic data fit to external substrate network (right) Substrate modeling is usually performed in the initial part of the extraction flow. In this phase it is not possible to check the substrate parameters by integrating them in the fully extracted model. The only way is to compute the network of Fig. separately and compare the results externally to measurements. On Fig. IIR the digits synthetic data was compared to the externally computed substrate model. While there was a nearly perfect fit with the built-in parameters on Fig. I serious misalignments arose using the external circuit. The real part flattens out and the capacitance also saturates at high frequencies in agreement with the regional behaviour summarized in Table I_. The observed pseudo misfit is the consequence of the residual parasitic admittance yr on Fig.. The gap between the substrate model and measurements is filled by its hidden contribution. R(y) [ms] III. Scaling a measured device matrix STM process B [] By the courtesy of Didier Celi STM, the following device matrix along with the corresponding on-wafer size correction formulas have been made available.

16 -May- Table III_ As drawn dimensions [um] W L Extraction from the lumped branch. B:.xum. B:.xum Vsc=-.V Vsc=.V - I(y+y)/ω [ff] - R(y) [ms] I(y+y)/om [ff]...ghz <= f <=.GHz -. I(y+y)/ω [ff] - - B:.xum R(y) [ms] I(y+y)/om [ff].... R(y) [ms] B:.xum.GHz <= f <=.GHz Vsc=-.V Vsc=.V R(y) [ms] Fig. III Virtual capacitance and admittance (left), compliance curves at three bias voltages (right) for the smallest (top) and larges (bottom) device. Simulation in cold (off state) mode: Vbe=V, Vsc=Vec=[-V, step.,.v] The compliance plots show the boomerang shaped charasterisitcs of Fig. identifying a distributed substrate. The linear regression () has been performed by the lines (not shown) laid across the filled points for each device and bias point. The first trial was to split the total capacitance into junction and perimeter components by matrix-vector techniques. Theoretically this is the only way to recognize a bias dependent perimeter capacitance. Bold lowercase letters stand for column vectors, T means transpose. Matrices will be denoted by bold uppercase. The unary vectors e V ; e G () have #bias and #geometry unities respectively. At geometry scaling the on-wafer area and perimeter vectors are computed from the drawn dimensions W, L by semi-empirical conversion formulas area = a( W, L); perimeter = p( W, L) () yielding the applied area and perimeter vectors T T a = area ; p = perimeter () { } { }

17 -May- It is assumed that Cjs and Cscp scale by area and perimeter respectively. () takes the following matrix-vector form T T Ctot = cjs a + cscp p () C tot is a matrix of size [#bias,#geometry] that is, has one row for each bias and one column for each geometry. Column vector cjs is the bias dependent specific substrate junction capacitance, cscp is the generally also bias dependent specific perimeter capacitance. () can be rearranged as T a Ctot = [ cjs + cscp] = X G () T p which has the solution T T X = Ctot G inv( G G ) () The specific capacitance vectors are in the st and nd columns respectively cjs = X(:, ); cscp = X(:,) () It will be apparent by inspection if cscp is truely bias depenent which case the capacitance parameters available in the model need to be extracted. Otherwise the average csc p = mean( cscp) () is computed across the bias points. With the trench capacitance known cjs from () will be discarded and the net junction capacitance is computed more accurately by the function T cjsp p if cjsp is bias dependent Cjsp = () T csc p ev p if cjsp is constant as Cjs_net = C tot Cjsp () Cjs for all geometries from capacitance split cscp from capacitance split. Cjs [ff] Vd [V] cscp [ff/um] cscp=.ff/um std. deviation= Vd [V] Fig. III Result of the Ctot split by the matrix-vector technique For this set of transistors the net (normalized) junction capacitance has become negative at elevated negative biases approximately below -.V as displayed on Fig. IIIL. The reason must have been inadequate calculated on-wafer sizes, data acquisition errors or both. A solution might be to prepare test transistors of relatively large dimensions reducing the effect of mask to wafer offsets and data acquisition errors. Applying the matrix technique to... such dimensions a robust perimeter specific either constant or bias dependent - trench capacitance definition can be expected for the given process. Using this data the extraction transistor structures shall be deembedded from Cscp and Rcx and the remaining substrate complex of the former HICUM versions can be extracted in one shot by equations (), ().

18 -May- For this case Cscp showed no tentative bias dependence on Fig. IIIR which made it possible to adopt (), (). Instead of using the geometry splitting proposed in the text observe that Rsux and Cz are completely defined by the regression from the points on the compliance curve. Therefore Rsux is done and the technique used for Group II. is taken over for allocating Csu by the refinement of Cscp. Actually this is an automatic or heuristic single variable optimization. On Fig. III Rsux and Cz is portrayed for the smallest and largest transistor. Once Cz is known, the fit to measurements is inspected for several estimated Cscp values. The indicated Cscp and Csu = Cscp Cz belong to the best fit conditions. The individual parameters of the transistors are scaled by perimeter (Cscp) and by area (Rsu, Csu, Cjs) as shown on the subplots of Fig. III. The junction capacitance is computed by Cjs = Ctot Cscp and each row of the Cjs matrix is normalized by the zero bias row vector providing a unit zero bias capacitance for each device. The mean of the normalized matrix columns is only bias dependent as marked by the white circles on Fig. III. The asterisks stand for the individual transistors whose in the ideal case should all collapse onto the white circles. The capacitance fit to the white circles is shown by the solid line. Finally the zero bias vector is scaled by area as demonstrated on Fig. III for providing Cjs for each geometry. Looking at Ctot=Cjs+Cscp one might expect that the possible bias dependence of the trench capacitance can be absorbed by Cjs. This assumption is supported by the split of Cje from cold to Cjei and Cjep where each extraction exhibit approximately the same fit quality. Start the process every case with a constant Cscp. Arriving at a reasonable fit it is indifferent if Cscp had been actually bias dependent or not. The resulting slightly modified temperature behaviour migh not be prohibitive. Rsu and Csu using optimized Cscp for B:.xum Rsu and Csu using optimized Cscp for B:.xum. Rsux=.kΩ Cz=.fF Rsux=.kΩ Cz=.fF Ctot [ff].. Cscp=.fF Csu=.fF Ctot [ff] Cscp=.fF Csu=.fF. τ js [ps] Fig. III Regression of Rsux and Cz τ js [ps]. Scaling Rsu Scaling Csu.. /Rsu=/rsu+A/rsuA rsu=.kω rsua=.kω.. Csu=csu+A*csuA csu=.ff csua=.ff/um /Rsu [ms]. Csu [ff] A [um ]. A [um ]

19 -May- Scaling Cscp Scaling Cjs Cscp [ff].. Cscp=cscp+P*cscpP cscp=-.ff cscpp=.ff/um Cjs [ff]... cjs=cjs+a*cjsa cjsa=.ff/um cjs=.ff... P [um] A [um ] Fig. III Geometry scaling of the regressed parameters Cjs [ff].... Specific substrate capacitance extraction stars: all devices circles: mean cjs=.ff vds=.v zs=. vpts= vd [V] Fig. III. Junction capacitance parameters Evaluation of the Group III. results Table III_ Extracted parameters Parameter Value Equation Cjs [ff]. cjsa [ff/um ]. Cjs = Cjs + A cjsa vds [V]. zs. vpts [V] Csu [ff]. csua [ff/um ]. Csu = Csu + A csua Rsu [kω]. A = + rsua[kω um] Rsu Rsu rsua Cscp [ff/um] -. cscpp [ff/um]. Cscp = Cscp + P csc pp The admittance matrix of the hicumlv. substrate complex of Fig. has been computed with the parameters and equations of Table III_ and the simulations have been benchmarked to measurements. The results are shown for selected devices on Fig. III.

20 -May- B,.xum: measurement to scaled substrate model scaled model B,.xum: measurement to scaled substrate model scaled model - - I(y+y)/ω [ff] filled: extraction points - - R(y) [ms] I(y+y)/ω [ff] filled: extraction points - - R(y) [ms] - - B,.xum: measurement to scaled substrate model scaled model - - B,.xum: measurement to scaled substrate model scaled model - - I(y+y)/ω [ff] filled: extraction points - - R(y) [ms] I(y+y)/ω [ff] filled: extraction points - - R(y) [ms] Fig. III Fit of the scaled substrate model to measurements The model agreement can be regarded satisfactory till about GHz. Above this frequency a pseudo misfit discussed at Group II. can be observed which is flavoured this case by the influence of the distributed nature of the substrates. It can be concluded that the theory and extraction technique is suitable for generating scaled substrate models for the design kits. REFERENCES [] S. Fregonese, D. Celi, T. Zimmer, C. Maneux and P.Y. Sulima,, A scalable substrate network for compact modelling of deep trench insulated HBT, Solid-State Electronics () -. [] M. Schroter and A. Pawlak, HICUM/L version. Release Notes, August [] S. D. Harker et al., An S-parameter Technique for Substrate Resistance Characterization of RF Bipolar Transisitors, IEEE BCTM,., pp. -. [] G. Fischer, Looking for the Adequate f max HICUM Workshop, München, May [] G. Avenier, et al, ".um SiGe BiCMOS Technology for mm-wave Applications," IEEE BCTM., pp. -, October -,, Monterey, CA [] P. Chevalier et al., A nm Triple Gate Oxide Metal Layers SiGe BiCMOS Technology FeaturingGHz ft/ GHz fmaxhbt and High-Q Millimeter-Wave Passives, IEDM, San Francisco CA USA, December -,