2 nd International HICUM user s meeting

Transcription

1 2 nd International HICUM user s meeting Monterey, September 22 D. Berger, D. Céli, T. Burdeau STMicroelectronics,, France

2 esults HICUM status in ST Implementation of HICUM model equation in an in-house program. This implementation corresponds to the DEVICE equations (HICUM version 2.1). HICUM test structures implemented in test masks. Extraction procedures were developed for a single geometry transistor. Implementation in an industrial tool ICCAP is in progress. Test on different devices and processes have been realized in order to validate the flow and the model equations. egular comparisons between DEVICE and different circuit simulators are made to insure the right implementation of HICUM into CAD tools. 1/12

3 - SPEED - ICCAP esults Extraction tools All HICUM model equations (version 2.1) have been implemented in a ST in-house program named SPEED (Spice Parameter Extraction tool for Electron Devices). Internal AC-DC solver. Allows to access to internal variables like junction capacitances, currents, transit time... very useful to understand the model and for global optimization. At this time HICUM was not correctly implemented in various circuit simulators. Implementation in ICCAP is in progress. ELDO: good convergence but slow interface with ICCAP. ADS : good interface with ICCAP but some convergence problems in high injection level. 2/12

4 SPEED: Spice Parameter Extraction tool for Electron Devices - SPEED - ICCAP GNUPLOT postcript file esults DC Solver AC Solver Optimizer Graphic Interface Model equations User Interface Parameter Extraction Exit Work File Measurement Device Dimension File Input Parameters File Extracted Parameters File 3/12

5 ICCAP - SPEED - ICCAP esults 4/12

6 - Status - Extraction flow esults Parameters status An flow for a single transistor geometry has been developed using SPEED (see BCTM paper). Some points still need to be improved to obtain more physical and scalable parameters. The methodology has been successfully tested on different processes and devices. A scalable parameter strategy is under development. DC parameters AC parameters Preliminary temperature s have been done and must be confirmed and automated in order to take into account the self-heating. Self-heating becomes more and more important for SiGe transistors (high f T, trench isolation,...). 5/12

7 - Status - Extraction flow esults Extraction flow at room temperature Total BE, BC and CS Junction Capacitances Split of BE and BC Junction Capacitances C JEI, C JEP, C JCI, C JCX BC avalanche current F AVL, Q AVL Transfer current at low injection C 1, Q P, H JCI assuming H JEI =1 Internal BE current I BEIS, M BEI, I EIS, M EI Parasitic substrate transistor everse BC current I TSS, I BCIS, I BCXS Series esistances CX, E Transit time at low injection T, T BVL, D TH, A LJEI (=A LJEP ) Transfer current at low and medium injection H JEI, correction of C 1, Q P, H JCI obtained in 4 Critical current CI, V CES, V PT, V Lim Transit time at high injection T EF, G TFE, T HCS, A LHC Base esistance BI, BX, F GEO, F DQ NQS effect A LIT, A LQF Improvement are required for scalable parameter 6/12

8 esults esults Transistor with.25x12.65µm 2 emitter area, 7GHz f T BiCMOS process β J C [ma/ µm 2 ] V CE [V] J C [ma/µm 2 ] I C, I B [ma] V BE [V] f T [GHz] /12

9 esults esults on different processes and devices ft [GHz] J C [ma/µm 2 ] V BC =-1.5, -1, -.5, -.25,,.25,.5 V.25x12.65 µm GHz f T 15 GHz f T ft [GHz] J C [ma/µm 2 ] x12.65 µm 2 V BC =-.5, -.25,,.2,.4 V J C [ma/µm 2 ] x6.25 µm J C [ma/µm 2 ] V BC =-1.5, -1, -.5, -.25,,.25,.5 V f T [GHz] GHz f T f T [GHz] V BC =-1.5, -1, -.5, -.25,,.25,.5 V x25.45 µm /12

10 Y 11 and Y 12 parameters (.25x12.65 µm 2, 15GHz SiGe-C f T ) V BC =V V BE = V step=.1 f T peak at V BE =.94V esults e(y 11 ) [S] Im(y 11 ) [S] e(-y 12 ) [S] Im(-y 12 ) [S] /12

11 Y 21 and Y 22 parameters (.25x12.65 µm 2, 15GHz SiGe-C f T ) V BC =V V BE = step=.1 f T peak at V BE =.94V esults e( y 21 ) [S] Im(-y 21 ) [S] e(y 22 ) [S] Im(y 22 ) [S] /12

12 2.5 2 Scalability (7GHz f T process) esults C [A.C] Q P [fc] A E 2 [µm 4 ] A E [µm 2 ] τ [ps] A E [µm 2 ] E [Ω] /A E [µm -2 ] 11/12

13 esults Extraction issues Main issues Improvement needed to obtain more reliable parameters (physical and scalable) for multigeometry approach. The split of the junction capacitances with taking into account overlap capacitances would be more accurate with the multigeometry flow. Work in progress. The collector resistance is still a major issue because of its impact on the transit time determination. A better solution would be to calculate CX from layout and sheet resistance. The transit time calculation for f T curves is still a critical point. Direct 1 2πf T from vs curves is not enough accurate for transistor with high f T. Solutions? 1 I C 12/12