Working Group Bipolar (Tr..)

Size: px
Start display at page:

Download "Working Group Bipolar (Tr..)"

Transcription

1 Department of Electrical Engineering and Information Technology Institute of Circuits and Systems Chair for Electron Devices and Integrated Circuits Working Group Bipolar (Tr..) I T parameter extraction issues in HiCuM/L for very advanced HBTs M. Schroter, J. Krause Hamburg,

2 Outline 1 Introduction Doping profiles 3 Transit frequency 4 Parameter extraction 5 Extraction results 6 Results from device simulations M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide /15

3 1 Introduction Currently, weight factors in the GICCR charge integral are assumed to be constant over bias. Depending on the extraction method experimental determination of the transfer current related model parameters Q p0 and c 10 may lead to issues for certain advanced devices. It is unclear whether this problem is caused by the method or the model formulation. exp( V B'E' V T ) exp( V B'C' V T ) exp( V I T c B'E' V T ) exp( V B'C' V T ) = 0 = c x 10 u Q p0 + h jei Q jei + h jci Q jci + Q ft, + Q r, T h g pdx x l with h g = μ nb n ib μ n ( x)n i ( x) Reproducing the issue by 1D device simulation allows to find the cause. M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 3/15

4 Doping profiles Two different reference profiles 500 GHz 300 GHz D [cm 3 ] Ge [%atom] D [cm 3 ] x [μm] x [μm] all investigations based on 1D DD device simulation indicated ft values are for 1D HD/MC simulation M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 4/15

5 3 Transit frequency Transit frequency 500 GHz 300 GHz f T [GHz] f T [GHz] f T V CE = (0.6, 0.8, 1.0, 1., 1.5)V M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 5/15

6 4 Parameter extraction 1st step: BE junction capacitance parameter extraction Q jei [fc/μm ] Q jei [fc/μm ] V [V] BE V [V] BE from extended HiCuM formulation, allows to analytically determine Q jei Note: C j,max is not directly measurable experimentally M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 6/15

7 4 Parameter extraction (cont d) nd step: c 10 and Q p0 extraction 7.5 analytical value numerical value linear fit 7.5 analytical value numerical value linear fit 7 7 Q jei [fc/μm ] 6.5 Q jei [fc/μm ] exp(v BE /V T )/ [μm /aa] c 10 exp( V BE V T ) Q jei h jei 0.65 V BE V BE 0.75 Q p exp(v BE /V T )/ [μm /aa] = V BC = 0V and very low h jei Slope and intercept of Q jei vs. exp(v BE /V T )/ represent auxiliary parameters c 10 =c 10 /h jei and Q p0 =Q p0 /h jei, resp. M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 7/15

8 4 Parameter extraction (cont d) Q p0 variation over V BE range (varied extraction intervals) Q p0 [fc/μm ] Q p0 [fc/μm ] V BE,max [V] V BE,max [V] Wide variation range of Q p0! Linear fit of Q jei vs. exp(v BE /V T )/ using increasing V BE interval with fixed starting point and V BE,max as final value M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 8/15

9 5 Extraction results Extracted model parameters parameter 500 GHz 300 GHz 100 GHz C jei ff/µm² ff/µm² ff/µm² V DEi V V V z Ei a jei Q p0,tech fc/µm² fc/µm² fc/µm² Q p0,rsbi fc/µm² fc/µm² 75.5 fc/µm² Q p0,extr fc/µm² fc/µm² fc/µm² c AC/µm AC/µm AC/µm 4 I S A/µm² A/µm² A/µm² h jci h jei Direct extraction gives too low or negative value for Q p0! M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 9/15

10 5 Extraction results (cont d) Forward gummel V BC = 0V simulated modeled simulated modeled V [V] BE V BE [V] Despite of the negative/non-physical value obtained for Q p0, the fit in the gummel plot shows good conformance. M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 10/15

11 6 Results from device simulations Q p0h from DEVICE simulations Q p0h [fc/μm ] 50 Q p0 Q p0h [fc/μm ] Q p0 f T peak 0 f T peak V [V] BE V BE [V] Q p0h significantly larger than Q p0 distinctive bias dependence of Q p0h M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 11/15

12 6 Results from device simulations (cont d) weight factors from DEVICE simulations hje hjc hfe hfb hfc hp hje hjc hfe hfb hfc hp0 10 h h f T peak 10 0 f T peak most weight factors are fairly constant up to peak f T Q jei largest contribution in low-/medium bias range -> bias dependence of h jei relevant M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 1/15

13 6 Results from device simulations (cont d) calculation of Q jeih and h jei from internal quantities hjei const. value 0.4V < VBE < 0.7V hjei 8 6 const. value 0.4V < VBE < 0.7V V BE [V] ΔQ jeh Q jeih q A E h g ( Δp Δn) dx with h jei (V BE ) = Q jeih (V BE )/(Q jei (V BE ). h p0 ) V BE [V] x μ Bn nr n ir = = h x g = me μ n ( x)n i ( x) M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 13/15

14 7 Results from device simulations (cont d) Insertion in GICCR h jei (V BE ) h jei (V BE ) const. h jei V BE [V] V BE [V] Total weighted charge Q pt, = Q p0h + Q jeih low-/medium bias cond.: only Q jeih and Q p0h significant c 10 i T = ( V Q BE V T ) V BC V T c 10 ( qa E ) = V T μ nb n ib pt, [ exp exp( )] with const. h jei M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 14/15

15 8 Summary Extracting Q p0 from I C may not give accurate values. Ignoring the bias dependence of h p0 (or Q p0 ) and h jei obviously leads to the observed extraction issue. Pros and cons of existing compact GICCR formulation to be investigated and evaluated on advanced HBT: Keeping existing absolute charge term seems more favorable if bias dependence is mainly caused by Q p0h => otherwise h p0 (bias) mixed with bias dependence of other weight factors M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 15/15

16 9 Appendix 3rd Extraction step: h jci determination simulated modeled c 10 exp(v BE /V T )/I C [fc] c 10 exp(v BE /V T )/I C [fc] Q jci [fc/μm ] simulated modeled Q jci [fc/μm ] c 10 [exp(v BE /V T )]/I C plotted vs. Q jci is linear and the slope gives the auxiliary parameter h jci =h jci /h jei. h jei is currently set to 1 per default! M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 16/15

17 Appendix (cont d) Extraction of Q p0 from R SBi V CE = 0V linear fit V CE = 0V linear fit /r r /r r Q x j [C/μm ] Q x j [C/μm ] Q j = Q jei + Q jci vs. r = r SBi /r V CE = 0V 1 r Q j -- r = > Q p0 as the slope Q p0 M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 17/15

18 9 Appendix (cont d) Internal BC capacitance C jci [ff/μm ] C jci0 = ff/µm² V DCi = V z Ci = a jci = V PTCi = V C jci [ff/μm ] C jci0 = ff/µm² V DCi = V z Ci = a jci =.336 V PTCi = V V [V] BC V [V] BC M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 18/15

19 9 Appendix (cont d) from DEVICE REGAP postprocessor τ f τ f [ps] 10 τ f [ps] =0.356 ps, = ps τ 0500GHz, τ 0300GHz, M. Schroter, J. Krause IT parameter extraction issues in HiCuM/L for very advanced HBTs Slide 19/15

Modeling high-speed SiGe-HBTs with HICUM/L2 v2.31

Modeling high-speed SiGe-HBTs with HICUM/L2 v2.31 Modeling high-speed SiGe-HBTs with HICUM/L2 v2.31 A. Pawlak, M. Schroter, A. Mukherjee, J. Krause Chair for Electron Devices and Integrated Circuits (CEDIC) Technische Universität Dresden, Germany pawlak@iee.et.tu-dresden.de,

More information

Non-standard geometry scaling effects

Non-standard geometry scaling effects Non-standard geometry scaling effects S. Lehmann 1), M. Schröter 1),2), J. Krause 1), A. Pawlak 1) 1) Chair for Electron Devices and Integr. Circuits, Univ. of Technol. Dresden, Germany 2) ECE Dept., University

More information

Regional Approach Methods for SiGe HBT compact modeling

Regional Approach Methods for SiGe HBT compact modeling Regional Approach Methods for SiGe HBT compact modeling M. Schroter 1),2) and H. Tran 2) 1) ECE Dept., University of California San Diego, La Jolla, CA, USA 2) Chair for Electron Devices and Integr. Circuits,

More information

About Modeling the Reverse Early Effect in HICUM Level 0

About Modeling the Reverse Early Effect in HICUM Level 0 About Modeling the Reverse Early Effect in HICUM Level 0 6 th European HICUM Workshop, June 12-13, 2006, Heilbronn Didier CELI, STMicroelectronics 1/21 D. Céli Purpose According to the bipolar models,

More information

HICUM / L2. A geometry scalable physics-based compact bipolar. transistor model

HICUM / L2. A geometry scalable physics-based compact bipolar. transistor model HICUM HICUM / L2 A geometry scalable physics-based compact bipolar transistor model M. Schroter, A. Pawlak, A. Mukherjee Documentation of model version 2.32 August, 2013 M. Schroter 16/5/14 1 HICUM List

More information

Accurate transit time determination and. transfer current parameter extraction

Accurate transit time determination and. transfer current parameter extraction Accurate transit time determination and transfer current parameter extraction T. Rosenbaum, A. Pawlak, J. Krause, M. Schröter Chair for Electron Devices and Integrated Circuits (CEDIC) University of Technology

More information

Status of HICUM/L2 Model

Status of HICUM/L2 Model Status of HICUM/L2 Model A. Pawlak 1), M. Schröter 1),2), A. Mukherjee 1) 1) CEDIC, University of Technology Dresden, Germany 2) Dept. of Electrical and Computer Engin., University of Calif. at San Diego,

More information

HICUM Parameter Extraction Methodology for a Single Transistor Geometry

HICUM Parameter Extraction Methodology for a Single Transistor Geometry HICUM Parameter Extraction Methodology for a Single Transistor Geometry D. Berger, D. Céli, M. Schröter 2, M. Malorny 2, T. Zimmer 3, B. Ardouin 3 STMicroelectronics,, France 2 Chair for Electron Devices

More information

A Novel Method for Transit Time Parameter Extraction. Taking into Account the Coupling Between DC and AC Characteristics

A Novel Method for Transit Time Parameter Extraction. Taking into Account the Coupling Between DC and AC Characteristics A Novel Method for Transit Time Parameter Extraction Taking into Account the Coupling Between DC and AC Characteristics Dominique BEGE and Didier CELI STMicroelectronics, 850, rue jean Monnet F-38926 Cedex

More information

Didier CELI, 22 nd Bipolar Arbeitskreis, Würzburg, October 2009

Didier CELI, 22 nd Bipolar Arbeitskreis, Würzburg, October 2009 HICUM/L0 v1.2: Application to Millimeter Wave Devices Didier CELI, 22 nd Bipolar Arbeitskreis, Würzburg, October 2009 Outline Purpose ariation of reverse Early effect with the evolution of technologies

More information

HICUM release status and development update L2 and L0

HICUM release status and development update L2 and L0 HICUM release status and development update L2 and L0 M. Schröter, A. Pawlak 17th HICUM Workshop Munich, Germany May 29th, 2017 Contents HICUM/L2 in a nutshell Release of HICUM/L2 version 2.4.0 Strong

More information

Nonlinear distortion in mm-wave SiGe HBTs: modeling and measurements

Nonlinear distortion in mm-wave SiGe HBTs: modeling and measurements Nonlinear distortion in mm-wave SiGe HBTs: modeling and measurements P. Sakalas $,#, A. Pawlak $, M. Schroter $ $ CEDIC, Technische Universität Dresden, Mommsenstrasse 13, Germany # FRLab. Semiconductor

More information

Methodology for Bipolar Model Parameter Extraction. Tzung-Yin Lee and Michael Schröter February 5, TYL/MS 2/5/99, Page 1/34

Methodology for Bipolar Model Parameter Extraction. Tzung-Yin Lee and Michael Schröter February 5, TYL/MS 2/5/99, Page 1/34 Methodology for Bipolar Model Parameter Extraction Tzung-Yin Lee and Michael Schröter February 5, 1999 TYL/MS 2/5/99, Page 1/34 Outline General Remarks Brief overview of TRADICA Parameter extraction flowchart

More information

2 nd International HICUM user s meeting

2 nd International HICUM user s meeting 2 nd International HICUM user s meeting Monterey, September 22 D. Berger, D. Céli, T. Burdeau STMicroelectronics,, France esults HICUM status in ST Implementation of HICUM model equation in an in-house

More information

Charge-storage related parameter calculation for Si and SiGe bipolar transistors from device simulation

Charge-storage related parameter calculation for Si and SiGe bipolar transistors from device simulation Charge-storage related parameter calculation for Si and SiGe bipolar transistors from device simulation M. Schroter ),) and H. Tran ) ) ECE Dept., University of California San Diego, La Jolla, CA, USA

More information

Digital Integrated CircuitDesign

Digital Integrated CircuitDesign Digital Integrated CircuitDesign Lecture 5a Bipolar Transistor Dep. Region Neutral Base n(0) b B C n b0 P C0 P e0 P C xn 0 xp 0 x n(w) b W B Adib Abrishamifar EE Department IUST Contents Bipolar Transistor

More information

Investigation of New Bipolar Geometry Scaling Laws

Investigation of New Bipolar Geometry Scaling Laws Investigation of New Bipolar Geometry Scaling Laws D. CELI 20 th Bipolar Arbeitskreis Munich, October 2007 Purpose Robust and high-performance RF circuit design need optimization of transistors. Therefore

More information

ELEC 3908, Physical Electronics, Lecture 19. BJT Base Resistance and Small Signal Modelling

ELEC 3908, Physical Electronics, Lecture 19. BJT Base Resistance and Small Signal Modelling ELEC 3908, Physical Electronics, Lecture 19 BJT Base Resistance and Small Signal Modelling Lecture Outline Lecture 17 derived static (dc) injection model to predict dc currents from terminal voltages This

More information

Runtime Analysis of 4 VA HiCuM Versions with and without Internal Solver

Runtime Analysis of 4 VA HiCuM Versions with and without Internal Solver Runtime Analysis of 4 VA HiCuM Versions with and without Internal Solver Didier Céli, Jean Remy 28 th ArbeitsKreis Bipolar - Letter Session Unterpremstaetten, Austria, November 5/6, 215 dm23a.15 Outline

More information

HICUM/L2 version 2.2: Summary of extensions and changes

HICUM/L2 version 2.2: Summary of extensions and changes HICUM/L2 version 2.2: Summary of extensions and changes M. Schroter Chair for Electron Devices & Integrated Circuits Dept. of Electrical and Computer Engineering (CEDIC) University of Technology Dresden,

More information

Thermal Capacitance cth its Determination and Influence on Transistor and Circuit Performance

Thermal Capacitance cth its Determination and Influence on Transistor and Circuit Performance Thermal Capacitance cth its Determination and Influence on Transistor and Circuit Performance Gerhard G. Fischer IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany IHP Im Technologiepark 25 15236

More information

Device Physics: The Bipolar Transistor

Device Physics: The Bipolar Transistor Monolithic Amplifier Circuits: Device Physics: The Bipolar Transistor Chapter 4 Jón Tómas Guðmundsson tumi@hi.is 2. Week Fall 2010 1 Introduction In analog design the transistors are not simply switches

More information

13. Bipolar transistors

13. Bipolar transistors Technische Universität Graz Institute of Solid State Physics 13. Bipolar transistors Jan. 16, 2019 Technische Universität Graz Institute of Solid State Physics bipolar transistors npn transistor collector

More information

Bipolar junction transistor operation and modeling

Bipolar junction transistor operation and modeling 6.01 - Electronic Devices and Circuits Lecture 8 - Bipolar Junction Transistor Basics - Outline Announcements Handout - Lecture Outline and Summary; Old eam 1's on Stellar First Hour Eam - Oct. 8, 7:30-9:30

More information

Breakdown mechanisms in advanced SiGe HBTs: scaling and TCAD calibration

Breakdown mechanisms in advanced SiGe HBTs: scaling and TCAD calibration Breakdown mechanisms in advanced SiGe HBTs: scaling and TCAD calibration T. Rosenbaum 1,2,3, D. Céli 1, M. Schröter 2, C. Maneux 3 Bipolar ArbeitsKreis Unterpremstätten, Austria, November 6, 2015 1 STMicroelectronics,

More information

A new transit time extraction algorithm based on matrix deembedding techniques

A new transit time extraction algorithm based on matrix deembedding techniques 27 A new transit time extraction algorithm based on matrix deembedding techniques C. Raya, N. Kauffmann, D. Celi, T. Zimmer State of art Method Result Introduction T F importance: - T F physical information

More information

Semiconductor Device Modeling and Characterization EE5342, Lecture 15 -Sp 2002

Semiconductor Device Modeling and Characterization EE5342, Lecture 15 -Sp 2002 Semiconductor Device Modeling and Characterization EE5342, Lecture 15 -Sp 2002 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/ L15 05Mar02 1 Charge components in the BJT From Getreau,

More information

Sample Exam # 2 ECEN 3320 Fall 2013 Semiconductor Devices October 28, 2013 Due November 4, 2013

Sample Exam # 2 ECEN 3320 Fall 2013 Semiconductor Devices October 28, 2013 Due November 4, 2013 Sample Exam # 2 ECEN 3320 Fall 203 Semiconductor Devices October 28, 203 Due November 4, 203. Below is the capacitance-voltage curve measured from a Schottky contact made on GaAs at T 300 K. Figure : Capacitance

More information

Lecture 17 - The Bipolar Junction Transistor (I) Forward Active Regime. April 10, 2003

Lecture 17 - The Bipolar Junction Transistor (I) Forward Active Regime. April 10, 2003 6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 17-1 Lecture 17 - The Bipolar Junction Transistor (I) Contents: Forward Active Regime April 10, 2003 1. BJT: structure and basic operation

More information

MEXTRAM (level 504) the Philips model for bipolar transistors

MEXTRAM (level 504) the Philips model for bipolar transistors MEXTRAM (level 504) the Philips model for bipolar transistors Jeroen Paasschens, Willy Kloosterman, Ramses van der Toorn FSA modeling workshop 2002 Philips Electronics N.V. 2002 apple PHILIPS Philips Research

More information

I. Semiconductor Device Capacitance-Voltage Characteristics

I. Semiconductor Device Capacitance-Voltage Characteristics Project 1 Assignment Diode Characterization (Solution Draft) EE 534 - Semiconductor Device Theory Project 1 Test on March 4, 005 Download this assignment at http://www.uta.edu/ronc/534/projects/534project1.pdf

More information

ELEC 3908, Physical Electronics, Lecture 17. Bipolar Transistor Injection Models

ELEC 3908, Physical Electronics, Lecture 17. Bipolar Transistor Injection Models LC 3908, Physical lectronics, Lecture 17 Bipolar Transistor njection Models Lecture Outline Last lecture looked at qualitative operation of the BJT, now want to develop a quantitative model to predict

More information

HICUM/L2 version 2.21: Release Notes

HICUM/L2 version 2.21: Release Notes HICUM/L2 version 2.21: Release Notes Chair for Electron Devices & Integrated Circuits (CEDIC) University of Technology Dresden, Germany M. Schroter and A. Chakravorty mschroter@ieee.org http://www.iee.et.tu-dresden.de/iee/eb/

More information

Bipolar Junction Transistor (BJT) - Introduction

Bipolar Junction Transistor (BJT) - Introduction Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification

More information

Lecture 20 - p-n Junction (cont.) October 21, Non-ideal and second-order effects

Lecture 20 - p-n Junction (cont.) October 21, Non-ideal and second-order effects 6.70J/3.43J - Integrated Microelectronic Devices - Fall 00 Lecture 0-1 Lecture 0 - p-n Junction (cont.) October 1, 00 Contents: 1. Non-ideal and second-order effects Reading assignment: del Alamo, Ch.

More information

ELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and Self-Heating

ELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and Self-Heating ELEC 3908, Physical Electronics, Lecture 18 The Early Effect, Breakdown and Self-Heating Lecture Outline Previous 2 lectures analyzed fundamental static (dc) carrier transport in the bipolar transistor

More information

TCAD setup for an advanced SiGe HBT technology applied to the HS, MV and HV transistor versions

TCAD setup for an advanced SiGe HBT technology applied to the HS, MV and HV transistor versions TCAD setup for an advanced SiGe HBT technology applied to the HS, MV and HV transistor versions T. Rosenbaum 1,2,3, D. Céli 1, M. Schröter 2, C. Maneux 3 Bipolar ArbeitsKreis München, Germany, November

More information

TEMPERATURE DEPENDENCE SIMULATION OF THE EMISSION COEFFICIENT VIA EMITTER CAPACITANCE

TEMPERATURE DEPENDENCE SIMULATION OF THE EMISSION COEFFICIENT VIA EMITTER CAPACITANCE TEMPERATURE DEPENDENCE SIMULATION OF THE EMISSION COEFFICIENT VIA EMITTER CAPACITANCE R. AMADOR, A. NAGY, M. ALVAREZ, A. POLANCO CENTRO DE INVESTIGACIONES EN MICROELECTRÓNICA, CIUDAD HABANA 10800, CUBA,

More information

Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime

Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime Outline The Bipolar Junction Transistor (BJT): structure and basic operation I V characteristics in forward active regime Reading Assignment:

More information

Lecture 38 - Bipolar Junction Transistor (cont.) May 9, 2007

Lecture 38 - Bipolar Junction Transistor (cont.) May 9, 2007 6.72J/3.43J - Integrated Microelectronic Devices - Spring 27 Lecture 38-1 Lecture 38 - Bipolar Junction Transistor (cont.) May 9, 27 Contents: 1. Non-ideal effects in BJT in FAR Reading material: del Alamo,

More information

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M - 0 > V M - V Tn V SDp = V DD - V M = (V DD - V M ) V Tp Equate drain

More information

Electric Field--Definition. Brownian motion and drift velocity

Electric Field--Definition. Brownian motion and drift velocity Electric Field--Definition Definition of electrostatic (electrical) potential, energy diagram and how to remember (visualize) relationships E x Electrons roll downhill (this is a definition ) Holes are

More information

Chapter 2. - DC Biasing - BJTs

Chapter 2. - DC Biasing - BJTs Chapter 2. - DC Biasing - BJTs Objectives To Understand : Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented

More information

Spring Semester 2012 Final Exam

Spring Semester 2012 Final Exam Spring Semester 2012 Final Exam Note: Show your work, underline results, and always show units. Official exam time: 2.0 hours; an extension of at least 1.0 hour will be granted to anyone. Materials parameters

More information

Microelectronic Circuit Design Fourth Edition - Part I Solutions to Exercises

Microelectronic Circuit Design Fourth Edition - Part I Solutions to Exercises Page Microelectronic Circuit esign Fourth Edition - Part I Solutions to Exercises CHAPTER V LSB 5.V 0 bits 5.V 04bits 5.00 mv V 5.V MSB.560V 000000 9 + 8 + 4 + 0 785 0 V O 785 5.00mV or ) 5.V 3.95 V V

More information

LOW TEMPERATURE MODELING OF I V CHARACTERISTICS AND RF SMALL SIGNAL PARAMETERS OF SIGE HBTS

LOW TEMPERATURE MODELING OF I V CHARACTERISTICS AND RF SMALL SIGNAL PARAMETERS OF SIGE HBTS LOW TEMPERATURE MODELING OF I V CHARACTERISTICS AND RF SMALL SIGNAL PARAMETERS OF SIGE HBTS Except where reference is made to the work of others, the work described in this thesis is my own or was done

More information

Institute of Solid State Physics. Technische Universität Graz. Exam. Feb 2, 10:00-11:00 P2

Institute of Solid State Physics. Technische Universität Graz. Exam. Feb 2, 10:00-11:00 P2 Technische Universität Graz nstitute of Solid State Physics Exam Feb 2, 10:00-11:00 P2 Exam Four questions, two from the online list. Calculator is ok. No notes. Explain some concept: (tunnel contact,

More information

Semiconductor Device Modeling and Characterization EE5342, Lecture 16 -Sp 2002

Semiconductor Device Modeling and Characterization EE5342, Lecture 16 -Sp 2002 Semiconductor Device Modeling and Characterization EE5342, Lecture 16 -Sp 2002 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/ L16 07Mar02 1 Gummel-Poon Static npn Circuit Model C RC Intrinsic

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

Transistor Characteristics and A simple BJT Current Mirror

Transistor Characteristics and A simple BJT Current Mirror Transistor Characteristics and A simple BJT Current Mirror Current-oltage (I-) Characteristics Device Under Test DUT i v T T 1 R X R X T for test Independent variable on horizontal axis Could force current

More information

Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 -

Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 - 6.012 - Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 - Posted on Stellar. Due net Wednesday. Qualitative description - MOS in thermal equilibrium

More information

EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions

EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 pn Junction p-type semiconductor in

More information

Prof. Paolo Colantonio a.a

Prof. Paolo Colantonio a.a Prof. Paolo olantonio a.a. 2011 12 The D bias point is affected by thermal issue due to the active device parameter variations with temperature I 1 I I 0 I [ma] V R } I 5 } I 4 } I 3 Q 2 } I 2 Q 1 } I

More information

The Devices. Devices

The Devices. Devices The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors

More information

CHAPTER 4: P-N P N JUNCTION Part 2. M.N.A. Halif & S.N. Sabki

CHAPTER 4: P-N P N JUNCTION Part 2. M.N.A. Halif & S.N. Sabki CHAPTER 4: P-N P N JUNCTION Part 2 Part 2 Charge Storage & Transient Behavior Junction Breakdown Heterojunction CHARGE STORAGE & TRANSIENT BEHAVIOR Once injected across the junction, the minority carriers

More information

Chapter 2 - DC Biasing - BJTs

Chapter 2 - DC Biasing - BJTs Objectives Chapter 2 - DC Biasing - BJTs To Understand: Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented

More information

Schottky Rectifiers Zheng Yang (ERF 3017,

Schottky Rectifiers Zheng Yang (ERF 3017, ECE442 Power Semiconductor Devices and Integrated Circuits Schottky Rectifiers Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Power Schottky Rectifier Structure 2 Metal-Semiconductor Contact The work function

More information

For the following statements, mark ( ) for true statement and (X) for wrong statement and correct it.

For the following statements, mark ( ) for true statement and (X) for wrong statement and correct it. Benha University Faculty of Engineering Shoubra Electrical Engineering Department First Year communications. Answer all the following questions Illustrate your answers with sketches when necessary. The

More information

Tunnel Diodes (Esaki Diode)

Tunnel Diodes (Esaki Diode) Tunnel Diodes (Esaki Diode) Tunnel diode is the p-n junction device that exhibits negative resistance. That means when the voltage is increased the current through it decreases. Esaki diodes was named

More information

PCM- and Physics-Based Statistical BJT Modeling Using HICUM and TRADICA

PCM- and Physics-Based Statistical BJT Modeling Using HICUM and TRADICA PCM- and Physics-Based Statistical BJT Modeling Using HICUM and TRADICA Wolfgang Kraus Atmel Germany wolfgang.kraus@hno.atmel.com 6th HICUM Workshop, Heilbronn (Germany), June 2006 c WK Jun 12th, 2006

More information

Recitation 17: BJT-Basic Operation in FAR

Recitation 17: BJT-Basic Operation in FAR Recitation 17: BJT-Basic Operation in FAR BJT stands for Bipolar Junction Transistor 1. Can be thought of as two p-n junctions back to back, you can have pnp or npn. In analogy to MOSFET small current

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 105: Microelectronic Devices and Circuits Spring 2008 MIDTERM EXAMINATION #1 Time

More information

ELE46703 TEST #1 Take-Home Solutions Prof. Guvench...

ELE46703 TEST #1 Take-Home Solutions Prof. Guvench... ELE46703 TEST #1 Take-Home Solutions Prof. Guvench... Problem 1 : Light Emitting Diode (60 pts.) Consider a GaAs pn junction which has the following properties. N a 10 16 cm -3 (p-side), N d 10 19 cm -3

More information

Charge-Storage Elements: Base-Charging Capacitance C b

Charge-Storage Elements: Base-Charging Capacitance C b Charge-Storage Elements: Base-Charging Capacitance C b * Minority electrons are stored in the base -- this charge q NB is a function of the base-emitter voltage * base is still neutral... majority carriers

More information

Lecture 16 The pn Junction Diode (III)

Lecture 16 The pn Junction Diode (III) Lecture 16 The pn Junction iode (III) Outline I V Characteristics (Review) Small signal equivalent circuit model Carrier charge storage iffusion capacitance Reading Assignment: Howe and Sodini; Chapter

More information

Problem 9.20 Threshold bias for an n-channel MOSFET: In the text we used a criterion that the inversion of the MOSFET channel occurs when V s = ;2 F w

Problem 9.20 Threshold bias for an n-channel MOSFET: In the text we used a criterion that the inversion of the MOSFET channel occurs when V s = ;2 F w Prof. Jasprit Singh Fall 2001 EECS 320 Homework 11 The nals for this course are set for Friday December 14, 6:30 8:30 pm and Friday Dec. 21, 10:30 am 12:30 pm. Please choose one of these times and inform

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 9/18/2007 P Junctions Lecture 1 Reading: Chapter 5 Announcements For THIS WEEK OLY, Prof. Javey's office hours will be held on Tuesday, Sept 18 3:30-4:30

More information

ECE-305: Spring 2018 Final Exam Review

ECE-305: Spring 2018 Final Exam Review C-305: Spring 2018 Final xam Review Pierret, Semiconductor Device Fundamentals (SDF) Chapters 10 and 11 (pp. 371-385, 389-403) Professor Peter Bermel lectrical and Computer ngineering Purdue University,

More information

Session 6: Solid State Physics. Diode

Session 6: Solid State Physics. Diode Session 6: Solid State Physics Diode 1 Outline A B C D E F G H I J 2 Definitions / Assumptions Homojunction: the junction is between two regions of the same material Heterojunction: the junction is between

More information

Lecture 35 - Bipolar Junction Transistor (cont.) November 27, Current-voltage characteristics of ideal BJT (cont.)

Lecture 35 - Bipolar Junction Transistor (cont.) November 27, Current-voltage characteristics of ideal BJT (cont.) 6.720J/3.43J - Integrated Microelectronic Devices - Fall 2002 Lecture 35-1 Lecture 35 - Bipolar Junction Transistor (cont.) November 27, 2002 Contents: 1. Current-voltage characteristics of ideal BJT (cont.)

More information

Student Number: CARLETON UNIVERSITY SELECTED FINAL EXAMINATION QUESTIONS

Student Number: CARLETON UNIVERSITY SELECTED FINAL EXAMINATION QUESTIONS Name: CARLETON UNIVERSITY SELECTE FINAL EXAMINATION QUESTIONS URATION: 6 HOURS epartment Name & Course Number: ELEC 3908 Course Instructors: S. P. McGarry Authorized Memoranda: Non-programmable calculators

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 1 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.12 Electronic Devices and Circuits Exam No. 1 Wednesday, October 7, 29 7:3 to 9:3

More information

Semiconductor Device Simulation

Semiconductor Device Simulation motivation and target applications compact model development under conditions relevant for circuit design development of test structures and measurement methods (fast) predicting device performance and

More information

Ideal Diode Equation II + Intro to Solar Cells

Ideal Diode Equation II + Intro to Solar Cells ECE-35: Spring 15 Ideal Diode Equation II + Intro to Solar Cells Professor Mark Lundstrom Electrical and Computer Engineering Purdue University, West Lafayette, IN USA lundstro@purdue.edu Pierret, Semiconductor

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

CLASS 3&4. BJT currents, parameters and circuit configurations

CLASS 3&4. BJT currents, parameters and circuit configurations CLASS 3&4 BJT currents, parameters and circuit configurations I E =I Ep +I En I C =I Cp +I Cn I B =I BB +I En -I Cn I BB =I Ep -I Cp I E = I B + I C I En = current produced by the electrons injected from

More information

MICROELECTRONIC CIRCUIT DESIGN Second Edition

MICROELECTRONIC CIRCUIT DESIGN Second Edition MICROELECTRONIC CIRCUIT DESIGN Second Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 10/23/06 Chapter 1 1.3 1.52 years, 5.06 years 1.5 2.00 years, 6.65 years 1.8 113

More information

ELEC 3908, Physical Electronics, Lecture 13. Diode Small Signal Modeling

ELEC 3908, Physical Electronics, Lecture 13. Diode Small Signal Modeling ELEC 3908, Physical Electronics, Lecture 13 iode Small Signal Modeling Lecture Outline Last few lectures have dealt exclusively with modeling and important effects in static (dc) operation ifferent modeling

More information

BIPOLAR JUNCTION TRANSISTOR MODELING

BIPOLAR JUNCTION TRANSISTOR MODELING BIPOLAR JUNCTION TRANSISTOR MODELING Introduction Operating Modes of the Bipolar Transistor The Equivalent Schematic and the Formulas of the SPICE Gummel-Poon Model A Listing of the Gummel-Poon Parameters

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

Lecture 17. The Bipolar Junction Transistor (II) Regimes of Operation. Outline

Lecture 17. The Bipolar Junction Transistor (II) Regimes of Operation. Outline Lecture 17 The Bipolar Junction Transistor (II) Regimes of Operation Outline Regimes of operation Large-signal equivalent circuit model Output characteristics Reading Assignment: Howe and Sodini; Chapter

More information

55:041 Electronic Circuits The University of Iowa Fall Exam 2

55:041 Electronic Circuits The University of Iowa Fall Exam 2 Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.

More information

Novel Back-Biased UTBB Lateral SCR for FDSOI ESD Protections

Novel Back-Biased UTBB Lateral SCR for FDSOI ESD Protections Novel Back-Biased UTBB Lateral SCR for FDSOI ESD Protections Yohann Solaro 1,2,3, Pascal Fonteneau 1, Charles-Alexandre Legrand 1 Claire Fenouillet-Beranger 1,3, Philippe Ferrari 2, Sorin Cristoloveanu

More information

Plan Bipolar junction transistor Elements of small-signal analysis Transistor Principles: PETs and FETs Field effect transistor Discussion

Plan Bipolar junction transistor Elements of small-signal analysis Transistor Principles: PETs and FETs Field effect transistor Discussion Physics of silicon transistors - 1 - Plan Bipolar junction transistor homojunction and heterojunction Doping considerations Transport factor and current gain Frequency dependence of gain in a microwave

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

EECS 151/251A Homework 5

EECS 151/251A Homework 5 EECS 151/251A Homework 5 Due Monday, March 5 th, 2018 Problem 1: Timing The data-path shown below is used in a simple processor. clk rd1 rd2 0 wr regfile 1 0 ALU REG 1 The elements used in the design have

More information

Lecture 19 - p-n Junction (cont.) October 18, Ideal p-n junction out of equilibrium (cont.) 2. pn junction diode: parasitics, dynamics

Lecture 19 - p-n Junction (cont.) October 18, Ideal p-n junction out of equilibrium (cont.) 2. pn junction diode: parasitics, dynamics 6.720J/3.43J - Integrated Microelectronic Devices - Fall 2002 Lecture 19-1 Lecture 19 - p-n Junction (cont.) October 18, 2002 Contents: 1. Ideal p-n junction out of equilibrium (cont.) 2. pn junction diode:

More information

Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model. April 8, 2003

Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model. April 8, 2003 6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 16-1 Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model April 8, 2003 Contents: 1. I-V characteristics (cont.) 2. Small-signal

More information

COURSE OUTLINE. Introduction Signals and Noise Filtering Sensors: PD5 Avalanche PhotoDiodes. Sensors, Signals and Noise 1

COURSE OUTLINE. Introduction Signals and Noise Filtering Sensors: PD5 Avalanche PhotoDiodes. Sensors, Signals and Noise 1 Sensors, Signals and Noise 1 COURSE OUTLINE Introduction Signals and Noise Filtering Sensors: PD5 Avalanche PhotoDiodes Avalanche Photo-Diodes (APD) 2 Impact ionization in semiconductors Linear amplification

More information

Lecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010

Lecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010 EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD

More information

Metal-oxide-semiconductor field effect transistors (2 lectures)

Metal-oxide-semiconductor field effect transistors (2 lectures) Metal-ide-semiconductor field effect transistors ( lectures) MOS physics (brief in book) Current-voltage characteristics - pinch-off / channel length modulation - weak inversion - velocity saturation -

More information

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3

More information

248 Facta Universitatis ser.: Elect. and Energ. vol. 9,No.2 (1996) doping of donor (N D ) and acceptor (N A ), respectively. With the degenerate appro

248 Facta Universitatis ser.: Elect. and Energ. vol. 9,No.2 (1996) doping of donor (N D ) and acceptor (N A ), respectively. With the degenerate appro FACTA UNIVERSITATIS (NIS) Series: Electronics and Energetics vol. 9, No. 2 (1996), 247{254 NEW INVESTIGATION ON SILICON BIPOLAR TRANSISTOR AT LOW TEMPERATURES Xiao Zhixiong and Wei Tongli Abstract. The

More information

Lecture 15 - The pn Junction Diode (I) I-V Characteristics. November 1, 2005

Lecture 15 - The pn Junction Diode (I) I-V Characteristics. November 1, 2005 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 15-1 Lecture 15 - The pn Junction Diode (I) I-V Characteristics November 1, 2005 Contents: 1. pn junction under bias 2. I-V characteristics

More information

Getting J e (x), J h (x), E(x), and p'(x), knowing n'(x) Solving the diffusion equation for n'(x) (using p-type example)

Getting J e (x), J h (x), E(x), and p'(x), knowing n'(x) Solving the diffusion equation for n'(x) (using p-type example) 6.012 - Electronic Devices and Circuits Lecture 4 - Non-uniform Injection (Flow) Problems - Outline Announcements Handouts - 1. Lecture Outline and Summary; 2. Thermoelectrics Review Thermoelectricity:

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 21: Bipolar Junction Transistor Administrative Midterm Th 6:30-8pm in Sibley Auditorium Covering everything

More information

Tunneling transport. Courtesy Prof. S. Sawyer, RPI Also Davies Ch. 5

Tunneling transport. Courtesy Prof. S. Sawyer, RPI Also Davies Ch. 5 unneling transport Courtesy Prof. S. Sawyer, RPI Also Davies Ch. 5 Electron transport properties l e : electronic mean free path l φ : phase coherence length λ F : Fermi wavelength ecture Outline Important

More information

exp Compared to the values obtained in Example 2.1, we can see that the intrinsic carrier concentration in Ge at T = 300 K is 2.

exp Compared to the values obtained in Example 2.1, we can see that the intrinsic carrier concentration in Ge at T = 300 K is 2. .1 (a) k =8.617 10 5 ev/k n i (T = 300 K) = 1.66 10 15 (300 K) 3/ 66 ev exp (8.617 10 5 ev/k) (300 K) =.465 10 13 cm 3 n i (T = 600 K) = 1.66 10 15 (600 K) 3/ 66 ev exp (8.617 10 5 ev/k) (600 K) = 4.14

More information

SPICE SIMULATIONS OF CURRENT SOURCES BIASING OF LOW VOLTAGE

SPICE SIMULATIONS OF CURRENT SOURCES BIASING OF LOW VOLTAGE SPICE SIMULATIONS OF CURRENT SOURCES BIASING OF LOW VOLTAGE MONICA-ANCA CHITA, MIHAI IONESCU Key words: Bias circuits, Current mirrors, Current sources biasing of low voltage, SPICE simulations. In this

More information

Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two -

Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two - 6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Outline Announcements Exam Two Coming next week, Nov. 5, 7:309:30 p.m. Review Subthreshold operation of MOSFETs Review Large

More information