Power and Heat: The Big Picture

Transcription

1 Power Power Density (W/cm 2 ) Power Dissipation in Nanoscale CMOS and Carbon Nanotubes Eric Pop Dept. of Electrical & Computer Engineering E. Pop 1 Power and Heat: The Big Picture AMD Intel Power PC Trend Rocket Nozzle Nuclear Reactor 10 Hot Plate Sun surface? 6000 W/cm 2 E. Pop 2

2 Thermal Management Challenges IBM S/390 refrigeration Grid computing: power plants co-located near computer farms E. Pop 3 Power and Heat: The Tiny Picture Suspended On substrate Carbon nanotubes burn at high enough applied voltage (they also emit light when they get this hot) E. Pop 4

3 Power, Thermal Management Methods System Level Active Microchannel Cooling (Cooligy) Is there a bottom-up IBM approach? Circuit + Software Level active power management (turn parts of circuit on/off) From the device and materials level? E. Pop 5 Chip-Level Thermal Network C interconnect T interconnect Intel Itanium Top view Hottest spots > 300 W/cm 2 C transistor C chip R dielectric T transistors R spreading T chip Cross-section 8 metal levels + ILD Intel 65 nm C heat sink R chip T heat sink chip carrier Si chip heat spreader fin array heat sink R convection fan T coolant Transistor < 100 nm E. Pop 6

4 Thermal and Electrical Resistance P = I 2 R T = P R TH V = I R R = f( T) Fourier s Law (1822) Ohm s Law (1827) E. Pop 7 Device-Level Thermal Challenges Small geometry High power density (device-level hot spot) Higher surface-to-volume ratio, i.e. higher role of thermal interfaces between materials Lower thermal conductivity Lowering power (but can it ever be low enough?!) Device-level thermal design (phonon engineering) Device Level: Confined Geometries, Novel Materials Material Si Ge Silicides k (W/m/K) Si (10 nm) 13 SiO Source: E. Pop (Proc. IEEE 2006) E. Pop 8

5 RTH (K/mW) Thermal Resistance of a Single Device GST Phase-change Memory (PCM) Cu Cu Via Si Single-wall nanotube SWNT Bulk FET L (mm) High thermal resistances: SWNT due to small thermal conductance (very small d ~ 2 nm) Others due to low thermal conductivity, decreasing dimensions, increased role of interfaces Silicon-on- Insulator FET SiO 2 Power input also matters: L ~ channel length SWNT or via ~ diameter mw Others ~ mw Data: Mautry (1990), Bunyan (1992), Su (1994), Lee (1995), Jenkins (1995), Tenbroek (1996), Jin (2001), Reyboz (2004), Javey (2004), Seidel (2004), Pop (2004-6), Maune (2006). E. Pop 9 Modeling Device Thermal Resistance Steady-state models Lumped: Mautry (1990), Goodson-Su (1994-5), Pop (2004), Darwish (2005) Finite-Element models D RTH (K/mW) SOI FET 10 1 Bulk FET L (mm) L W t Si t BOX Bulk Si FET SOI FET R TH 1 1 2k D 4k LW Si Si R TH 1 t BOX 2W kbox ksitsi 1/ 2 E. Pop 10

6 Frequency ω (cm -1 ) A More Detailed Look 1. Monte Carlo heat generation in bulk and strained silicon Buried oxide Gate Silicon substrate 2. Self-heating in thin-body SOI and GOI devices 3. Self-heating and lessons from carbon nanotubes nanotube on substrate 2 μm suspended over trench E. Pop 11 Quick Recap of Phonons Graphene Phonons [100] CO 2 molecule vibrations 200 mev 160 mev transverse small k 100 mev transverse max k=2p/a silicon u( r, t) Aexp[ i( k r it)] 26 mev = 300 K Phonons = lattice vibration waves Phonons are responsible for heat transport in semiconductors Hot phonons = highly occupied modes above room temperature k E. Pop 12

7 Current E-field Mesh Freq (Hz) Details Picture of Joule Heating High Electric Field Note: optical phonon energy in CNTs (180 mev) about 3x higher than in Si (60 mev) E < 50 mev t ~ 0.1ps Hot Electrons (Energy E) Acoustic Phonons (v ac ~ 9000 m/s) Heat Conduction to Package t ~ 1 ms 1 s E > 50 mev t ~ 0.1ps (v op ~ 1000 m/s) Optical Phonons t ~ 5 ps optical acoustic Wave vector qa/2p Energy (mev) E. Pop 13 2D Thin-Body SOI Simulation E. Pop et al., Proc. IEEE, 2006 Study of device matching L G = 18 nm ITRS specs if W/L = 4 then N elec ~ 2500 total! Monte Carlo (MONET) Notice heat is dissipated in device drain E. Pop 14

8 Heat Generation in Quasi-Ballistic Devices E. Pop et al., SISPAD 2005 L=500 nm 100 nm 20 nm Heat Gen. (ev/cm 3 /s) Monte Carlo Medici DL Medici Monte Carlo source channel drain source channel drain source channel drain Error: DL/L = 0.10 DL/L = 0.38 DL/L = 0.80 Monte Carlo vs. Medici (drift-diffusion commercial code): Long (500 nm) device: same current, potential, nearly identical Importance of non-local transport in short devices Heat dissipation in DRAIN (optical, acoustic) of shortest devices E. Pop 15 Phonon Generation Spectrum in Silicon E. Pop et al., Appl. Phys. Lett. 86, (2005) Complete spectral information on phonon generation rates Note: effect of scattering selection rules (less f-scat in strained Si) Note: same heat generation at high-field in Si and strained Si E. Pop 16

9 k (W/m/K) What About Device Design? Monte Carlo Analysis Thermal Conductivity Design and Scaling E. Pop 17 Thin Film Thermal Conductivity E. Pop et al., Proc. IEDM Intel DST/SOI Transistor Bulk Si ~ 150, Ge ~ 60 W/m/K Thin Si Si NW Thin Ge SiGe NW d (nm) Phonon boundary scattering and confinement Strong decrease in thin film or nanowire thermal conductivity (k), up to x lower than bulk How does this affect nanometer scale devices? E. Pop 18

10 Boundary Thermal Resistance E. Pop et al., Proc. IEEE (2006) Intel DST/SOI Transistor Lyeo, Cahill (2006) Al/SiO 2/Si GST/ZnS/SiO 2 Thermal interface resistance at solid-solid material interfaces Caused by phonon dispersion mismatch b/w materials (~Cv/4), electronphonon energy conversion at boundary, roughness at boundary Approximately equivalent to ~ nm additional SiO 2 E. Pop 19 Self-Consistent Electro-Thermal Model E. Pop et al., Proc. IEDM 2004 P=VI R R R R xd ex Q sd co (R Q due to heat source position) C ln 1 L / t / p ex R 2 sw ex ox Geometry R T=PR P=VI I 1.4 T I ~ m V dd V t n C t=cv/i 0.7 mv/k E. Pop 20

11 Relative Leakage (T L ) T L in center of hotspot (K) Intrinsic Delay (ps) SOI/GOI Device Design Optimization E. Pop et al., Proc. IEDM 2004 CV/I t SD = nt film n = Gate Length L g (nm) t film L ex t SD Larger Source/Drain (S/D) volume will help heat spreading in drain BUT no improvement for S/D thickness t SD > 3-4 x t film = Effect of parasitic side-wall capacitance on Intrinsic Delay Optimized, well-behaved GOI devices 30% faster than optimized SOI E. Pop 21 Transient Device Thermal Modeling Z.-Y. Ong and E. Pop, submitted (2008) Silicon Silicon Dioxide 900 nm 100 nm 1633 nm 72 nm Heat Generation nm Fourier (t on =5.04ps) Temperature Swings TTM (t on =2.52ps) TTM (t on =5.04ps) Fourier (t 20 on =2.52ps) Time elapsed (ps) 8 ITRS 2014 device specs Time elapsed (ps) Compact thermal device model including: Non-equilibrium heat generation from Monte Carlo Phonon relaxation parameter-matched to Boltzmann Transport Eq. Capture spatial and temporal temperature excursions What is the effect on leakage & reliability? TTM (Steady) TTM (Pulsed) Fourier (Pulsed) Fourier (Steady) E. Pop 22

12 Onto Carbon Nanotubes Single-wall nanotube SWNT RTH (K/mW) Silicon-on- Insulator FET SiO L (mm) Data: Mautry (1990), Bunyan (1992), Su (1994), Lee (1995), Jenkins (1995), Tenbroek (1996), Jin (2001), Reyboz (2004), Javey (2004), Seidel (2004), Pop (2004-6), Maune (2006). E. Pop 23 Where Carbon Nanotubes Fit In Allotropes of Carbon: Graphite (pencil lead) Diamond Buckyball (C60) Amorphous (soot) Single-Walled Nanotube E. Pop 24

13 Carbon Nanotubes for Electronics Carbon nanotube = rolled up graphene sheet Great electrical properties Semiconducting Transistors Metallic Interconnects Electrical Conductivity σ 100 x σ Cu d ~ 1-3 nm Thermal Conductivity k k diamond 5 x k Cu Nanotube challenges: Reproducible growth Control of electrical and thermal properties Going from one to a billion S (Pd) HfO 2 top gate (Al) SiO 2 back gate (p++ Si) CNT D (Pd) E. Pop 25 Nanotube Back-of-the-Envelope Estimates Typical L ~ 2 mm, d ~ 2 nm DT On insulating solid substrate Pt Heat dissipated into substrate Moderate power ~ 10 mw/mm Peak DT ~ 60 K SiO 2 g Thermal conductivity k ~ 3000 W/m/K Freely suspended nanotube Heat dissipated along tube length Pt k DT Moderate power ~ 10 mw (10 1 V) Peak DT ~ 400 K! SiO 2 E. Pop 26

14 Phonon Temperature (K) Transport in Suspended Nanotubes E. Pop et al., Phys. Rev. Lett. 95, (2005) nanotube on substrate 2 μm suspended over trench nanotube Pt Si 3 N 4 Pt gate SiO 2 Observation: significant current degradation and negative differential conductance at high bias in suspended tubes Question: Why? Answer: Tube gets HOT (how?) E. Pop 27 Transport Model Including Hot Phonons I 2 (R-R c ) E. Pop et al., Phys. Rev. Lett. 95, (2005) R OP T OP Non-equilibrium OP: T T ( T T ) OP AC AC 0 R TH T AC = T L T 0 Heat transfer via AC: A kt I R R L 2 ( ) ( C ) / I 2 (R-R C ) T OP T AC = T L oxidation T Optical T OP Acoustic T AC V (V) Landauer electrical resistance h R( V, T) RC 2 4q Include OP absorption: eff AC OP, ems OP, abs L eff ( V, T) eff ( V, T) 1 E. Pop 28

15 γ (a.u.) γ (a.u.) Distance (mm) trench Extracting SWNT Thermal Conductivity E. Pop et al., Nano Letters 6, 96 (2006) Yu et al. (NL 05) This work Inverse numerical extraction of k from the high bias (V > 0.3 V) tail Comparison to data from K of UT Austin group (C. Yu, NL Sep 05) Result: first complete picture of SWNT thermal conductivity from K E. Pop 29 Light Emission from Metallic SWNTs D. Mann et al., Nature Nano 2, 33 (2007) Joule-heated tubes emit light: Comes from center, highly polarized Quasi-metallic = small band gaps Emitted photons at higher energy than applied bias (high energy tail) 3 2 Wavelength (nm) V ds = 1.4 V suspended 1 V ds = 7 V on substrate Energy (ev) S D S 2.2 Polarization 0 90 angle ~ σt 4 E. Pop source drain γ (a.u.)

16 Return to SWNTs On Substrates E. Pop et al., Proc IEDM 2005; Proc IEEE 2006 SWNT on insulating solid substrate Heat dissipated into substrate rather than along tube length Q: How do I model heat loss into substrate? [A: need some gauge of the tube temperature] Pt DT g SiO 2 E. Pop 31 Nanotube Temperature Gauge Pt SiO 2 g E. Pop 32

17 Nanotube Temperature Gauge Doesn t exist But oxidation (burning) temperature is known T BD ~ 600 o C O 2 Suspended Pt On substrate g SiO 2 E. Pop 33 Breakdown of SWNTs in Air (Oxygen) A( kt ) p' g( T T0 ) 0 At breakdown: p' IBD VBD / L BD BD T0 IBD V gl T / E. Pop, Proc. IEDM (2005) A. Javey, PRL 92, (2004) Data shows SWNTs exposed to air break down by oxidation at 500 < T BD < 700 o C ( K) Joule breakdown voltage data shows V BD scales with L in air Supports cooling mechanism along the length, into the substrate E. Pop 34

18 T (K) Electrical Breakdown of SWNTs E. Pop et al., J. Appl. Phys. 101, (2007) L d Pt g SiO 2 t OX V BD (a) Si t SI (b) SWNT exposed to air from the top Sweep voltage low to high Temperature peaks in the middle When T max = T BD V = V BD and P BD = I BD V BD E. Pop 35 Electrical Breakdown of SWNTs E. Pop et al., J. Appl. Phys. 101, (2007) T max V BD 500 ΔT C X (mm) SWNT exposed to air from the top Sweep voltage low to high Temperature peaks in the middle When T max = T BD V = V BD and P BD = I BD V BD E. Pop 36

19 P BD (mw) Breakdown Data from Literature E. Pop, DRC (2007) P BD gl T BD T 0 cosh( L / 2LH ) glhr T sinh( L / 2LH ) cosh( L / 2L ) gl R sinh( L / 2L ) 1 H H T H Stanford Caltech Infineon "short" "long" Zoom into L < 2 mm P BD = 88.8L R 2 = L (µm) L (µm) Short vs. long breakdown: Compared to thermal healing length ~ 0.2 µm Note: There is a minimum breakdown power ~ 0.05 mw We can learn a lot more about electrical and thermal properties E. Pop 37 SWNT Compact Model Up to Breakdown E. Pop et al., J. Appl. Phys. 101, (2007) Data Model Understanding transport in a 3 mm metallic SWNT up to breakdown: T max ~ 600 o C = 873 K V max ~ 15 V Thermal healing length along SWNT ~ 0.2 mm Current saturation ~ 20 ma in long tubes (> 1 mm) due to self-heating Self-heating not significant when p < 5 mw/mm (design goal?) More current in short nanotubes = less heating? E. Pop 38

20 Summary Small device dimensions, high local power densities RTH (K/mW) PCM Bulk FET SWNT SOI FET L (mm) Increased device thermal resistance with decreasing dimensions Physics-based models to capture: Size effects Phonon non-equilibrium Transient temperature effects Opportunity for bottom-up thermal device and materials design E. Pop 39