Thermal Resistance (measurements & simulations) In Electronic Devices

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1 Thermal Resistance (measurements & simulations) In Electronic Devices A short online course PART 3 Eric Pop Electrical Engineering, Stanford University 1

2 Topics 1) Basics of Joule Heating 2) Heating in Devices & Circuits 3) Thermal Resistance & Estimates 4) Device Thermometry 2

3 Thermal-Electrical Cheat Sheet 3

4 Device Thermal Resistance Data Single-wall nanotube SWNT High thermal resistances: SWNT due to small thermal conductance (very small d ~ 2 nm) Others due to low thermal RTH (K/mW) GST Phase-change Memory (PCM) conductivity, decreasing dimensions, increased role of interfaces Silicon-on- Insulator FET SiO Cu Cu Via Si Bulk FET L (m) Power input also matters: SWNT ~ mw Others ~ mw Data: Mautry (1990), Bunyan (1992), Su (1994), Lee (1995), Jenkins (1995), Tenbroek (1996), Jin (2001), Reyboz (2004), Javey (2004), Seidel (2004), Pop (2004-6), Maune (2006). 4

5 Approaches for Thermal Resistance Time scale: Steady-State (DC) Transient Geometric complexity: Lumped element (shape factors) Analytic Finite element (Fourier law) Via + Interconnect D L W t Si t BOX Bulk Si FET SOI FET 5

6 Modeling Device Thermal Resistance Steady-state (DC) models Lumped: Mautry (1990), Goodson-Su (1994-5), Pop (2004), Darwish (2005) Finite-Element D RTH (K/mW) Bulk FET SOI FET L (m) L W t Si t BOX Bulk Si FET SOI FET R TH 1 1 2k D 2k LW Si Si S R TH 1 t BOX 2W kbox ksitsi 1/2 6

7 Examples (1) D L W Bulk Si FET SOI FET R TH 1 1 2k D 2k LW Si Si S R TH 1 t BOX 2W kbox ksitsi 1/2 k Si ~ 100 Wm -1 K -1 (highly doped Si) and D = 1 µm then R TH ~ 5 K/mW so T = PR TH ~ 5 K with 1 mw power t Si = 10 nm, t BOX = 50 nm, W = 1 µm k Si ~ 10 Wm -1 K -1 (reduced in thin film) and k BOX ~ 1.4 Wm -1 K -1 then R TH ~ 130 K/mW so T = PR TH ~ 67 K with 0.5 mw power 7

8 Examples (2) R B T L W t BOX = 90 nm, L = W = 1 µm and k BOX ~ 1.4 W/m/K TBR = thermal boundary resistance ~ 10-8 m 2 K/W R SiO2 t BOX R Si T 0 2D FET R B = TBR / (WL) ~ 10 K/mW R SiO2 = t BOX / (k BOX * WL) ~ 60 K/mW R Si = 1 / [2 * k Si * (W + t BOX )] ~ 4.5 K/mW total R TH ~ 75 K/mW so T = PR TH ~ 30 K with 0.4 mw power note the SiO 2 layer dominates, but TBR also plays an important role 8

9 Shape Factors Sunderland, ASHRAE (1964), many others Heat flux: q = Sk(T 1 -T 0 ) Equivalent thermal resistance R TH = 1/Sk 9

10 Many Shape Factors (Compact Models) 10

11 Obtaining the Temperature Distribution So far we ve only looked at lumped thermal models Now we want temperature distribution T(x) Simplest case: Si layer on SiO 2 /Si substrate (SOI) Or interconnect on thermally insulating SiO 2 11

12 1-D Interconnect with Heat Generation W L x x+dx d Heat: dt QAk dx dv I AJ A F A dx Electrical: SiO 2 Si T 0 t ox Write energy balance equation for element dx pick units of J or W (= J/s) Energy In (here, Joule heat) = Energy Out (left, right, bottom) + Change in Internal Energy ka ka hwdxt T QAdx T x x T x x dx 0 C( Adx) T t divide by (Adx): W Q kth T T0 C A e.g. J E if non-uniform or I 2 R/(WLd) if uniform convection-like term, here h = k ox /t ox and W/A = 1/d W can be perimeter if heat loss in all directions T t 12

13 Ex: 1D Rectangular Nanowire 1/m is natural length scale thermal healing length L H k k sub td sub 13

14 Interconnect Heat Loss and Crosstalk 14

cylindrical heat spreading (shape factor!

15 Ex: Carbon Nanotube (Cylinder) L T d A( kt ) p' g( T T0 ) 0 Pt g SiO 2 t OX T p' cosh( x / L H ) x) T 1 g cosh( L / 2L ) H ( 0 (a) Si t SI (b) dr p' I I dx 2 2 h 1 q 2 4 eff L H ka g Role of cylindrical heat spreading (shape factor!) g ox kox 8tox ln d T max Role of thermal contact resistance et al. J. Appl. Phys. 101, (2007) T (K) ΔT C X (m) dt ka dx C T R C CTh, 15

Further Reading L. Su et al., Measurement and modeling of self-heating in SOI nmosfets, IEEE Trans. Elec. Dev. 41, 69 (1994), http://dx.doi.org/10.1109/16.259622 A. Liao et al.

16 Further Reading L. Su et al., Measurement and modeling of self-heating in SOI nmosfets, IEEE Trans. Elec. Dev. 41, 69 (1994), A. Liao et al., "Thermally-Limited Current Carrying Ability of Graphene Nanoribbons," Phys. Rev. Lett. 106, (2011), C. Durkan et al., Analysis of failure mechanisms in electrically stressed Au nanowires, J. Appl. Phys. 86, 1280 (1999), D. Chen et al., Interconnect Thermal Modeling for Accurate Simulation of Circuit Timing and Reliability, IEEE Trans. CAD 19, 197 (2000), T.-Y. Chiang et al., Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effect, IEEE EDL 23, 31 (2002), et al., Electrical and thermal transport in metallic single-wall carbon nanotubes on insulating substrates, J. Appl. Phys. 101, (2007), Energy Dissipation and Transport in Nanoscale Devices, Nano Research 3, 147 (2010), 16

Power and Heat: The Big Picture

Power Power Density (W/cm 2 ) Power Dissipation in Nanoscale CMOS and Carbon Nanotubes Eric Pop Dept. of Electrical & Computer Engineering http://poplab.ece.uiuc.edu E. Pop 1 Power and Heat: The Big Picture