Schottky-Barrier Engineering for Low-Resistance Contacts

Transcription

1 1 Schottky-Barrier Engineering for Low-Resistance Contacts Pankaj Kalra, Hideki Takeuchi, Tsu-Jae King Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA Oct 03, 2005

2 2 Outline Introduction Characterization Schemes Si 1- Ge Source/Drain Dopant Segregation Strain Summary

3 3 Parasitic Resistance Components Gate R sl Silicide sheet resistance R csd Contact Resistance R sd Silicon Sheet Resistance R ov Overlap resistance R sl R csd R sd R ov R ch Parasitic resistance must be <10% of total FET resistance CMOS scaling reduces channel resistance 1/L increases contact resistance Source: Prof. Jason Woo, UCLA

4 4 contact area Contact Resistance Scaling Al-Si Heavily doped Si SALICIDE contact area W Plug MSi reduction of contact area contact area W Plug MSi Change in contact scheme (adoption of SALICIDE) has etended the contact scaling Due to the reduction of active area, silicide/si contact resistance is now an issue

5 5 Int l Technology Roadmap for Semiconductors (2004 update) ρ c (ohm-cm 2 ) Target Ozturk et al., IEDM New materials and processes are needed

6 6 Impact of R c on FinFET H. Kam and T.-J. King, 2004 Silicon Nanoelectronics Workshop End Contact I ds L gate = 18 nm, L eff = 22 nm Wrapped Contact, ρ c = 0 Wrapped Contact End Contact Top Contact 16% reduction 34% reduction ρ c =10-8 Ω-cm 2 S O G D UR AT R A C E I E N Top Contact S O G D UR AT R A C E I E N Parasitic resistances dominate FinFET performance ρ C <10-8 Ω-cm 2 required V ds S O UR C E Wrapped Contact G AT E D R A I N

7 7 Specific Contact Resistivity Barrier Height and Active Dopant Concentration 4 ρ ep c R co εm h * = φ ρc A B N Dopant concentration, N c ρ c = Contact resistivty A c = Contact Area φ B Barrier height, φ B Fermi-level pinning results in: Metal Silicon Body Barrier height independent of metal work function

8 8 Approaches to Lowering ρ c Material engineering SiGe source/drain M. Ozturk et al, IEDM, 2002 smaller bandgap smaller Schottky barrier ρ c ~10-8 Ω-cm 2 for Ni germanosilicides on SiGe lower resistivity Barrier height tuning image force lowering by dopant segregation A. Kinoshita et al., Symp. VLSI Technology, 2004 strain-induced φ B reduction Fermi-level de-pinning by interface engineering insertion of insulator layer selenium passivation A. Yagishita et al., SSDM, 2003 D. Connelly et al., IEEE Trans. Nanotech., 2004 M. Tao et al., APL, 2003

9 9 Research Objective To understand the mechanisms for tuning the effective Schottky barrier height of a metallic electrode, to guide the engineering of contact-formation processes Low-φ B contacts for reduced parasitic resistance Demonstrate fully silicided source/drain UTB MOSFETs with improved I dsat by reducing ρ c (to <10-8 Ω-cm 2 ) for silicide-to-silicon contacts Gate SOI SiO 2 Silicon Substrate silicide T BOX Schematic Cross-section of Silicide S/D UTB MOSFET T Si

10 10 Outline Introduction Characterization Schemes Si 1- Ge Source/ Drain Dopant Segregation Strain Summary

11 11 Contact Resistance Measurement M. Ozturk et al, IEDM, 2002 Minimum measurable resistance is ~10 Ω Need very small contact holes to determine ρ c accurately below 10-8 Ω-cm -2

12 12 Test structures Fabrication of Kelvin structures Evaluation of contact resistance metal pad active area Fabrication of diode Measure schottky barrier height Kelvin Structure: Plan View metal SiO 2 lightly-doped Si Diode: Schematic Cross section

13 13 Fabrication of Sub-0.25µm Contacts Contacts were fabricated using DUV stepper ASML5500/90; Cymer KrF ecimer laser (l=248nm) 65mJ/cm 2 70mJ/cm 2 75mJ/cm 2 80mJ/cm 2 85mJ/cm 2 after litho: 188nm 247nm 261nm 268nm 275nm after etch: 171nm 211nm

14 14 Measure diode I-V characteristic at different temperatures φ B etraction 1E-6 1E-7 IF ln ln 2 T ( ** A A ) ( φ V ) e q kt Bn F J/T 2 1E-8 1E /T

15 15 Outline Introduction Characterization Schemes Si 1- Ge Source/ Drain Dopant Segregation Strain Summary (This work is sponsored by the project )

16 16 Dopant Behavior in Ultra-Thin SOI T Si =80nm T Si =10nm D. Ha et al., IEDM 2004 P-channel thin-body FETs ehibit higher series resistance Different behaviors of B and P in ultra-thin Si dopant segregation to interface(s), or into surrounding oide? F.-L. Yang et al., 2004 Symp. VLSI Technology

17 17 Epitaial Si 1- Ge Source/Drain Epitaial Si 1- Ge source/ drain regions for lowering R series and inducing compressive strain to enhance hole mobility Conventional approach for epitaial growth of Si 1- Ge is not possible for thin-body devices because there is not sufficient crystalline substrate after S/D etchback Si 1- Ge Source Gate SOI Si 1- Ge Drain SiO 2 Silicon Substrate

18 18 Approach Develop a process for selectively forming strained Si 1- Ge -in-soi by intermiing Ge & Si Study the intermiing of Ge with SOI films effects of anneal temperature, time, boron doping Investigate strain in the resultant Si 1- Ge alloy Characterize metal-to-si 1- Ge contact resistance Germano-silicidation of Si 1- Ge to achieve dopant pileup (to study φ B reduction)

19 19 Advantages of This Approach Selective deposition of Ge by conventional LPCVD GeH 4 gas, 320 o C, 200mT high process throughput (batch process) low cost XTEM of UTB MOSFET w/ raised Ge S/D Gate Ge Source Ge Drain SiO 2 Si T Si = 3 nm Y.-K. Choi et al., IEEE Electron Device Lett., Vol. 22, p. 447, 2001

20 20 Ge/Si Interface Preparation Selective Ge deposition in LPCVD furnace requires a clean silicon surface Interface preparation is critical Native oide removal methods in-situ HF vapor clean in-situ HF vapor clean and Hydrogen bake HF dip followed by Hydrogen bake in-situ cleaning by GeH 4 Si I/I after Ge deposition for breaking up any native oide at the Ge/Si interface

21 21 In-Situ GeH 4 Cleaning GeH 4 H 2 O H 2 GeO native oide Silicon Substrate Silicon Substrate Silicon Substrate Decreased GeH 4 flow to diffuse Ge on the surface M. Moslehi, Proceedings of SPIE-The international Society for Optical Engineering, vol. 1393, pp , Silicon Substrate Clean surface

22 22 Si Ion Implantation to Break Up Native Oide Si + implant has been used to break up the native oide barrier for Solid-Phase Epitay (SPE) Y. C. Yeo et al., IEEE Transactions on Electron Devices, Vol. 49, No. 2, pp , Si + Ge Ge Silicon Substrate Silicon Substrate

23 23 Starting wafers Test Sample Process Flow n-type, ρ=5-10 µω-cm Cross-sectional TEM pattern formation Silicon substrate CVD SiO 2 deposition (52nm) Lithography CVD SiO 2 Silicon substrate Oide etching (90% dry + 10% wet) SiO 2 SiO 2 Silicon substrate Top-down view through optical microscope

24 24 Process Flow (Cont d) Interface Preparation HF last / HF vapor Selective Ge deposition (22nm) 320 o C/200mTorr/100sccm Capping layer (25nm) Si Implant Si : 40keV, 1E15 cm -2 Doping B : 10keV, 2E15 cm -2 Recrystallization 500 o C, 1 hour Intermiing anneal 800 o C/ 850 o C, 1minute Si 1- Ge SiO Ge 2 Ge SiO 2 Ge Silicon substrate SiO 2 Ge SiO 2 Ge SiO 2 SiO 2 Silicon Substrate SiO 2 SiO 2 Silicon Substrate Ge

25 25 Eperimental Splits on wafer splits = 4 Si B Split Table: Si I/I + B I/I Si I/I none B I/I Wafer ID Cleaning HF Last HF vapor I/I splits Si I/I B I/I Si I/I + B I/I none Annealing 800 C 850 C

26 26 Determining Ge and B profiles (in collaboration with Prof. Haller s group) Characterization of vertical and lateral co-diffusion of Ge and B Available Options: Cross-sectional TEM with EDX nanoprobe Cross-sectional TEM with EELS Cross-sectional SEM with EDX nanoprobe

27 27 Summary and Future Goals Si 1- Ge Source/Drain Fabrication of first batch is finished Splits for Doped/ undoped Ge, interface preparation, annealing conditions etc. Results of this batch are awaited Future Work: Characterization of boron-doped Si 1- Ge -on-insulator resistance Characterization of metal-to-si 1- Ge contact resistance Germano-silicidation of Si 1- Ge to achieve dopant pile-up for Schottky barrier height (φ B ) reduction

28 28 Outline Introduction Characterization Schemes Si 1- Ge Source/ Drain Dopant Segregation (This work is sponsored in part by Intel Corp.) Strain Summary

29 29 φ B Reduction by Dopant Segregation φ B can be reduced by using an ultrathin (<10nm) heavily doped layer at the semiconductor surface J. Shannon, Applied Physics Letters, Vol. 24, pp , image force lowering ( φ) due to surface electric field q φ = ε si Na 4π N = dopant concentration in surface layer a = width of heavily doped surface layer Such a thin heavily doped layer can be formed by silicidation-induced dopant segregation: A. Kinoshita et al., 2004 Symp. VLSI Technology, Digest of Technical Papers, pp

30 30 Eperiment Goals: Confirm dopant segregation w/ NiSi Investigate dopant activation Process sequence: starting Si wafer (n-type/ p-type) deposit capping layer, CVD SiO 2 blanket implantation (B- 20KeV, cm -2 As- 80KeV, cm -2 ) spike annealing@1000c strip capping layer ecimer laser annealing Ni deposition silicidation strip unreacted Ni starting substrate Ni unreacted Ni NiSi

31 31 Results: SIMS Analyses Concentration (atoms/cm -3 ) 1E22 1E21 1E20 1E19 1E18 As Ni O Si 1 1E Depth (nm) Counts/sec Dopant pile-up at silicide/ Si interface is seen for both As and B doping (only As shown here)

32 32 Image Force Effect Schottky Barrier Lowering Induced charges at the interface Equivalent to an image charge Metal Semiconductor qφ BO q φ qφ B m m -qψ() = W q 16πε E S qv b E C E F qv PE( ) φ = 2 q = qe 16π ε q E 4π ε s s

33 33 Tailoring the Surface Electric Field φ depends on the surface electric field Lightly doped substrate: Low E, barrier-lowering is sensitive to reverse bias Heavily doped substrate: High E φ B is reduced, but reverse current increases tunneling Ohmic contact! To retain Schottky junction properties and to achieve φ that is insensitive to bias, a heavily doped surface layer that is fully depleted by the built-in potential is needed

34 34 Fully-Depleted Doped Surface Layer The required electric field has been shown to be > V/cm J. Shannon, Applied Physics Letters, Vol. 24, pp , Maimum surface field arising from implantation of a symmetrical distribution of charge about range R p : qφ BO q φ qφ B q φ higher carrier concentration qv b lower carrier concentration E qv s,ma b Vb Rp = qφ ( E E B 0 c f For a metal contacting a lightly doped substrate, built-in potential V b ~0.45V R p < 100A )

35 35 Φ B Reduction Model Maimum surface field, E s,ma E E q = ε [ N a+ N ( W )] a s, ma p B s,ma s q N ε q φ ε s s p a N p 4π a Epected barrier height lowering due to a thin highly doped surface layer: Barrier lowering, ev NiSi N p N B design space a=100a 0 NiSi a=50a active dopant conc. in surface layer (cm -3 ) a N p N B

36 36 Effect of Interface States Metal-induced gap states (MIGS) Penetration of wave function from the metal into the forbidden energy gap of Si Metal Semiconductor Electron potential energy including the contributions of image force and MIGS qφ BO E f K. Shenai et al., IEEE TED, Vol. ED-32, No. 4, pp , 1985 Metallic wave penetration in metal-semiconductor system PE( ) 2 q qqλ = qe e 16 π ε ε s s λ Q = magnitude of surface state charge λ = penetration depth of surface state charge

37 37 φ Inverse Modeling Approach Find the location of PE() minimum 2 d q ( PE( )) = 0 qe( = 2 d m 16πε s m Total barrier lowering is given by m qq ) + e ε s m λ = 0 λ m λ φ = ψ (0) ψ ( ) + e 0 0 m 16πε ε s m s Solve Poisson s equation to find Ψ 0 () 2 ρ( ) ψ ( ) = 0 ε s Etract Q and λ from measured forward I-V characteristics Predict total barrier lowering from the model N p, work-function difference, Q, and λ are input parameters q Q

38 38 Determining Active Dopant Concentration Spreading Resistance Probe (SRP): within 1/2 the probe spacing (~10µm) of the Si/ silicide interface, silicide starts affecting readings because of low resistance Need to remove NiSi selectively surface roughness increase difficult to find bevel edge NiSi Si

39 39 Summary and Future Work Dopant Segregation Ni silicidation induced dopant segregation phenomenon confirmed A quantitative inverse-modeling approach has been established for determining the amount of Schottkybarrier lowering Future Work: Fabrication and characterization of diode structures and Kelvin structures Application of dopant-segregation technique to improve FinFET performance by reducing S/D contact resistance

40 40 Outline Introduction Characterization Schemes Si 1- Ge Source/ Drain Dopant Segregation Strain Summary

41 41 φ B Reduction by Si Strain A. Yagishita et al., SSDM % bi-aial strain reduces φ B by 0.1eV (ErSi 1.7 S/D NMOSFET)

42 42 Eperimental Plan Use a bending apparatus apply uniaial or biaial bending stress to Si chips Study φ B reduction Fabricate Schottky diodes and contact test structures to measure effect of strain on ρ c K. Uchida et al., IEDM 2004

43 43 Outline Introduction Characterization Schemes Si 1- Ge Source/ Drain Dopant Segregation Strain Summary

44 44 Summary Source/drain contact resistance can limit the performance of nanoscale FETs ρ c ~10-9 Ω-cm 2 will be required Approaches for reducing ρ c include use of Si 1- Ge in the source/drain regions, dopant segregation, and strain Work in progress will clarify the mechanisms for lowering the effective Schottky barrier height φ B Application to nanoscale thin-body FETs

45 45 Acknowledgements Akira Hokazono (Toshiba Corporation) Dr. Chi On Chui (Intel Corporation) Research funding from UC Discovery Grant program and member companies of the Feature-Level Compensation and Control () project at UC-Berkeley Intel Corporation