Chapter 2. Review of Digital Systems Design
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1 x 2-4 = Chapter 2 Review of Digital Systems Design Numbering Systems Decimal number may be expressed as powers of 10. For example, consider a six digit decimal number , which can be represented as 9 x x x x x x 1 or more concisely as 9 x x x x x x 10 0 The numbers are 0, 1, 2 up to 9 since in a decimal system, the base is 10. This representation can be easily extended to fractional values as well. For example, the decimal number can be represented as 9 x x x x 10-2 In general, a number may be represented in any numbering system as b -n-2 d n-1 b n-1 + d n-2 b n d 1 b 1 + d 0 b 0 + d_ 1 b -1 + d -2 b d - n-1 b-n-1 + d - n-2 Consider the binary number , whose decimal equivalent is 1 x x x x x x x x x decimal number can be converted to a binary number by repeated division by 2 for the integer part and by repeated multiplication by 2 for the part after the decimal point. Quotient Remainder
2 42 /2 21 / /2 1 5 /2 0 2 /2 1 1 / = Integer answer. 2x x x Fraction =.101 The final answer is got by putting the integer and fraction answers together as Conversion of Numbers from one System to nother Decimal Number (ase 10) inary Number (ase 2) Octal Number (ase 8) Hexadecimal Number (ase 16) C D E F
3 The following is an example of a hexadecimal number converted to a decimal number. (FEDC) 16 = 15 x X x X x = ( ) 10 Twos Complement ddition/subtraction Twos complement of a binary number may be evaluated by adding one to the ones complement (which is just performing bit-wise inversion) of the number. inary number : Ones complement : Twos complement : Consider the numbers = and = in twos complement notation. Evaluate: (a) (b) (c) (d) (e) = = (a) + = Sum = Twos complement of Sum = = Twos complement of = (b) - = Sum =
4 = Twos complement of = (c) - = Sum = Twos complement of Sum = = Twos complement of = = (d) - = Sum = Twos complement of = Twos complement of = (e) -- = Sum = Codes inary and CD codes Decimal Number inary Code 8421 CD Code
5 Gray Code Four-bit Gray Code Sequence Gray Code Sequence Decimal Equivalent SCII Code
6
7 Extended SCII Code
8 Error Detection Code 1.The parity of the data is odd since there are 7 numbers of '1' bits in the data. The parity bit will be 1, giving the codeword The parity of the data is even as there are 8 numbers of '1' bits. The parity bit will be 0, giving the codeword The parity of the data is even (zero being an even number). The parity bit will be 0, giving the codeword null or non-existent bitstream also has zero '1' bits and, therefore, it would get the parity bit 0 in an even parity scheme. oolean lgebra 1. Commutative laws for addition and multiplication: + = + = (for addition) (for multiplication) where and are two single bit variables. 2. ssociative laws for addition and multiplication: ( + ) + C= + ( + C) ( C) = ( ) C where, and C are single bit variables.
9 3. Distributive laws both for multiplication over addition and for addition over multiplication: ( + C) = ( ) + ( C) + ( C) = ( + ) ( + C) The following laws are also satisfied: 4. (+) = 5. () = ( ) = 7. ( + ) = 8. + ( ) = 1 9. ( ) = = 0; = 1; = 1; = 1; 0 0 = 0; 0 1 = 0; 1 0 = 0; 1 1 = 1 Verification of Commutative, ssociative and Distributive laws
10 C ( ) + C + ( + C) + ( C) ( + ) ( + C) + ( ) ( + ) oolean Functions using Minterms and Maxterms ny oolean function can be expressed as a sum of minterms or as a product of maxterms. For example, consider the function F1 formed by the sum of products of variables, and C: F1 = C + C + C + C + C = m 0 + m 2 + m 4 + m 6 + m 7 F1 may also be expressed in a short form as F1 = Σ (0, 2, 4, 6, 7) where Σ implies sum (rather OR) of minterms.
11 Minterms and Maxterms for inary Variables Minterms Maxterms C Term Symbol Term Symbol C m C M C m C M C m C M C m C M C m C M C m C M C m C M C m C M 7 Truth Table of a Function to be Realized Using Minterms C F Truth Table of a Function to be Realized Using Maxterms C F
12 Let us now consider the function F2 formed by active low product of sums of variables, and C: F2 = ( + + C ) ( + + C ) ( + + C ) = M 1 M 3 M 5 where M 1, M 3, M 5 are called Max terms. In short, the function may be expressed as follows: F2 = Π (1, 3, 5) The product symbol, Π, denotes the NDing of maxterms. It may be noted that the function F2 is just the complement of F1. The final result is F2, the complement of F2 and the same as F1. Thus, one may use either the minterms or the maxterms to evaluate a function, whichever is simpler. Logic Gates GTE SYMOL FUNCTION uffer F1 F1 = Inverter F2 F2 = ND F3 F3 = OR F4 F4 = + NND F5 F5 = () NOR F6 F6 = (+)
13 Symbols and Functions of the Common Types of Gates The Karnaugh MP Method of Optimization of Logic Circuits m 0 m 1 1 m 2 m 3 K Map for Two Signals and C 0 m 0 m 1 m 3 m 2 1 m 4 m 5 m 7 m 6 K Map for Three Signals, and C
14 CD 00 m 0 m 1 m 3 m m 4 m 5 m 7 m 6 m 12 m 13 m 15 m 14 m 8 m 9 m 11 m 10 K Map for Four Signals,, C and D F1 = + K Map Reduction for Two Signals using Minterms C C C C F2 = Σ (0, 2, 3, 5) F2 = C + C + C
15 K Map Reduction for Three Signals using Minterms CD D Vertical (Horizontal) F3 = + D = + D D for the four corners K Map Reduction for Four Signals using Minterms CD D Vertical (Horizontal) F4 = + D +D for the four corners K Map Reduction for Four Signals using Maxterms
16 Combination Circuits Multiplexers S 0 S 1 I 0 S 1 S 1 I 1 S 1 S 0 S 0 S 0 S 1 S 0 I 2 F S 1 I 3 S 0 a Logic diagram S 1 S 0 F 0 0 I I I I 3 b Function table Inputs I0 I1 I2 I3 4-1 MUX S 1 S 0 Select Pins c lock diagram F Four Input Multiplexer Demultiplexer Input 1-4 Demultiplexer S 1 D 0 D 1 D D 1 S 0 D 3 S 1 S 0 Input 0 0 D D D 3 Select Pins a lock Diagram b Function Table
17 Four Output Demultiplexer Decoder CD Inputs D 0 D 1 3 D 2 D 3 2 CD to D 4 Decimal D 5 1 Decoder D 6 D 7 ctive low Decimal Outputs 0 D 8 D 9 CD to Decimal Decoder Decoder Truth Table of CD to Decimal Inputs Intermediate Outputs D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D
18 3 3 ' 0 3 ' 2 ' 1 ' 0 ' D 0 = 3 ' 2 ' 1 ' 0 ' 2 2 ' 1 3 ' 2 ' 1 ' 0 D 1 = 3 ' 2 ' 1 ' ' 0 0 ' ' 1 ' 0 D 9 = 3 2 ' 1 ' 0 Logic Diagram of CD to Decimal Decoder Magnitude Comparator 4-bit Magnitude Comparator ( < ) ( = ) ( > ) lock Diagram of a 4-bit Magnitude Comparator 3 3 E E 2 E 3 u E 1 E 3 E 2 u 1 u 3 ( < ) 0 0 E 0 E 3 E 2 E 1
19 Logic Circuit Diagram of a 4-bit Magnitude Comparator dder/subtractor Circuits Half dder Sum_H = + = Truth Table of a Half dder Sum_H
20 Sum_H = Logic of a Half dder Full dder Truth Table of a Full dder C C_F S_F C C C S_F = C C F = +C+C
21 Logic Realization of a Full dder The sum and carry outputs are respectively S_F = C C_F = +C+C Half Subtractor Truth Table of a Half Subtractor S_HS S_HS = + =. S_HS = Logic of a Half dder
22 Full Subtractor Truth Table of a Full Subtractor C _FS S_FS _FS = + C + C S_FS = C + C + C + C C C FS = + C + C C C C C S FS = C + C + C + C
23 Logic Gate Realization of a Full Subtractor rithmetic Logic Unit Function Controls S 0 S 1 S 2 S 3 G P For Look-head Carry M = Carry Inputs Data Inputs C_in LU F 0 F 1 F 2 F 3 C-out Outputs Carry-out LU Logic Symbol (Courtesy of Texas Instruments Inc.) 74xx181, LU function table (Courtesy of Texas Instruments Inc.) Selection S 3 S 2 S 1 S 0 ctive high data M = L: rithmetic operations M =H Logic functions C n = H (no carry) C n = L (with carry) L L L L F = F = F = plus 1 L L L H F = + F = + F = + plus 1
24 Programmable Logic Devices Inputs ND rray Programmable Connects Programmable OR rray Outputs a Programmable read-only memory (PROM/EPROM/Flash ROM)
25 Inputs Programmable Connects Programmable ND rray Programmable Connects Programmable OR rray Outputs b Programmable Logic array (PL) Programmable Connects Inputs Programmable ND rray OR rray Outputs c Programmable array Logic (PL) Programmable Logic Devices, ROM, PL, PL Read-Only Memory N inputs N N x W ROM D W-1 D 0 W Outputs lock Diagram of ROM Each bit (b) in a word may be regarded as a oolean function. Usually, the ROMs come with large memory sizes such as 4 K, 8 K, up to over 512 K. Therefore,
26 ROMs are usually overkill for realizing oolean functions. However, they are quite cheap and, therefore, may be cost-effective. Programmable Logic rray (PL) L L X X X X X X F 1 = L + X X X X F 8 = + L X PL with twelve inputs and eight outputs Programmable rray Logic (PL) X X X X Graphic symbol of ND inputs of PL
27 L L X X X F 1 = L + X X F 8 = + L X X PL with twelve inputs and eight outputs Sequential Circuits Inputs Combinational circuits Outputs Next State Value(s) Clock Register(s) lock diagram of a sequential circuit
28 RS Flip-Flop R Q S R Q Q S Q (after S =1, R = 0) (after S =0, R = 1) a Logic Circuit b Truth table RS flip-flop circuit using NOR gates S Q S R Q Q R Q (after S =1, R = 0) (after S =0, R = 1) a Logic diagram b Truth table RS flip-flop circuit using NND gates S Q Clk R Q a Logic Diagram
29 S R Q(n) Q(n+1) Indeterminate Indeterminate Q 0 1 SR X X 1 R Q Q(n+1) = S+R Q SR = 0 S S Clk R Q Q b Characteristic Table c Characteristic Equation d Symbol Clocked RS flip-flop JK Flip-Flop J Q CP K R D Q Q Q R D
30 Clocked JK Flip-flop Truth table of JK Flip-Flop OPERTING MODE INPUTS OUTPUTS J K Q R D CP Q synchronous Reset (Clear) L X X X L H Toggle H h h q q Load 0 (Reset) H l h L H Load 1 (Set) H h l H L Hold no change H l l q q H = HIGH voltage level steady state. L = LOW voltage level steady state. h = HIGH voltage level one setup time prior to the HIGH-to-LOW Clock transition. l = LOW voltage level one setup time prior to the HIGH-to-LOW Clock transition. X = Don t care.
31 q = Lower case letters indicate the state of the referenced output prior to the HIGHto-LOW Clock transition. = Positive Clock pulse. D Flip-Flop D S D Q CP R D Q S D R D Q Clk Q D D Flip-Flop
32 Truth table of D Flip-Flop OPERTING MODE INPUTS OUTPUTS CP D Q S D R D Q synchronous Set L H X X H L synchronous Reset (Clear) H L X X L H Undetermined L L X X H H Load 1 (Set) H H h H L Load 0 (Reset) H H l L H H = HIGH voltage level steady state. L = LOW voltage level steady state. h = HIGH voltage level one setup time prior to the LOW-to-HIGH Clock transition. l = LOW voltage level one setup time prior to the LOW-to-HIGH Clock transition. X = Don t care. T Flip-Flop T Q Clk Q a Logic Diagram
33 T Q(n) Q(n+1) b Characteristic Table Q(n) T Q(n+1) = TQ(n) +T Q(n) c Characteristic Equation T Flip-Flop S Q J Q D Q T Q CLK CLK CLK CLK R Q K Q Q Q RS FF JK FF D FF T FF Symbols for Flip-Flops Characteristic Tables of Flip-Flops RS Flip-Flop S R Q(n+ 1) Condition 0 0 Q(n) No change Reset Set 1 1? Unpredictable JK Flip-Flop J K Q(n + 1) Condition 0 0 Q(n) No change Reset Set 1 1 Q (n) Complement
34 D Flip-Flop T Flip-Flop D Q(n + 1) Condition T Q(n + 1) Condition 0 0 Reset 0 Q(n) No change 1 1 Set 1 Q (n) Complement Excitation Tables of Flip-Flops Q(n) Q(n+1) S R X X 0 RS FF Q(n) Q(n+1) D D FF Q(n) Q(n+1) J K X X 1 0 X X 0 JK FF Q(n) Q(n+1) T T FF Serial Input D0 Q0 D1 Q1 D N-1 Q N-1 Serial Output Clk N-bit Shift Register
35 Random ccess Memory (RM) DW-1 D0 N-1 0 R W CS RM 2 N x D QW-1 Q0 lock diagram of a RM Clock Parameters and Skew 90 % T 100 % 50 % T ON T OFF 10 % 0 % t r t f Clock Waveform
36 Interconnect Delay 1 CLK 1 CLK CLOCK Interconnect Delay N CLK N CLK 1 CLK N Clock skew Setup, Hold and Propagation Delay Times in a Register Clock Data input Data can change here Data must be stable here Data can change here t S t H Setup and Hold Times in a Flip-flop D Input Clock Q Output Q Output t phl t plh t plh t phl
37 Propagation Delay Time in a D Flip-flop The maximum clock frequency may be expressed as: F max = 1/ T clk or F max = 1/(t pmax + t Cmax + t S ) Hold time is satisfied if: t pmin + t Cmin t H Digital System Design using SSI/MSI Components Outputs Inputs Combination Circuits Registers lock Diagram of a Digital System Two-bit inary Counter using JK Flip-flops 00 INPUT I =
38 State Diagram for a Controlled Counter State Table for the Controlled 2-bits inary Counter External Input Flip-Flops Flip-Flops Flip-Flops Present State Next State Inputs I + + J K J K X 0 X X X X 0 0 X X 0 X X 0 X X X X 0 1 X X 1 X 1 I X X I X X X X 1 X X 1 0 J = I K = I
39 I X X 0 I X 0 0 X 1 0 X X 1 1 X 1 1 X J = I K = I K Maps for JK Flip-flops inputs I J / K J CLK K J Q K Q I J J CLK I = K J Q K Q Logic Circuit Diagram of the Controlled 2-bits inary Counter Design of a 3-it Counter Using T and D Flip-flops
40 State diagram of a 3-bit binary counter State Table for a 3-it Counter Using T and D Flip-flops Present State Next State T Flip-Flops Inputs D Flip-Flops Inputs C + + C + T T T C D D D C C C C T = C T = C T C = 1 K Maps for a 3-bit binary counter Using T Flip-flops
41 T T Q CLK Q C T C = T CLK T Q Q V CC = T C T Q C CLK Q Logic Circuit Diagram of the 3-bit binary counter Using T Flip-flops 0 C C C D = C+ +C D = C+C D C = C K Maps for the 3-bit binary counter Using D Flip-flops D Q D C CLK Q D D D Q C CLK Q C D C = D C D Q C CLK Q C
42 Logic Circuit Diagram of the 3-bit binary counter Using D Flip-flops Controlled Three-bit inary Counter using ROM and Registers State Table for ROM based Counter Implementation ROM ddress ROM Content D 3 D 2 D 1 D 0 Input Present State Next State I C + + C + OUT
43 Registers + I 3 D 3 + D x 4 ROM C + C C C 1 D 1 0 D 0 OUT CLK Digital System Design Using Registers and a ROM lgorithmic State Machine State Name Code Outputs or Operations INITILIZE LOD, Z = a Format b n Example State ox of an SM Chart From State ox From Decision ox 0 or F Condition 1 or T To Conditional Output or State ox Outputs or Operations To Next State ox
44 a Decision ox b Conditional Output Decision ox and Conditional Output of an SM Chart S CS 0 LD 1 SR = 0 SR = S S n Example of Combined Decision oxes and Conditional Outputs Digital System Design Using SM Chart and PL Processor Status Control Signals External inputs CLK Control Logic Input Data CLK Data Processor Output Data
45 lock Diagram of a Digital System Viewed as Control and Data Processors Single Pulser Using SM Chart DETECT 0 Synch_P 0 1 Single Pulse DELY 1 Synch_P 1 0 SM Chart of the Single Pulser SM Table of Single Pulser State Name Qualifier Present State Next State Single_Pulse Detect Synch_P Synch_P 0 1 1
46 Delay Synch_P Synch_P Data Synchronizer State Register Synch_P Deb_P D Q D CLK CLK Q Single_Pulse Circuit Diagram of the Single Pulser Design of a Vending Machine using PL + Vcc + Vcc (Typ. for all outputs) 100 K 2HZ CLK RDY To ready lamp O 10 μf 4 Dec. Weights RES s 2 s 1 s 0 PL CONTROLLER OS1 OS2 OS3 OS4 To Output Solenoids of the can dispensing mechanism CD SWITCH C CC OS5 s 2 s 1 s 0 C COIN CCEPTOR CLER
47 Usage 1. Wait for RDY lamp to switch ON. 2. Set CD switch to the desired value. 3. Insert the correct coin and collect the desired can. Circuit Diagram of a Vending Machine using PL One-hot State ssignment s = s 2 s 1 s 0 => CD switch to select the desired item S S C = Coin ccepted S RDY = System is Ready to accept coin S RES = Power On reset signal S CC = Clear Coin ccept S C=0 S 0 RDY=1 C=1 s= s 2 s 1 s 0 = 0/5/8 S 1 OS1=1 CC=1 C=1 s=1/6/9 S 2 OS2=1 CC=1 C=1 s=2/7 S 3 OS3=1 CC=1 C=1 s=3 C=1 s=4 S 4 OS4=1 CC=1 S 5 OS5=1 CC=1
48 State Graph for Vending Machine State Table for Vending Machine Present state Inputs Next state Outputs R C O O O O O C D E C s 2 s C + D + E + F + D C S S S S S F s 0 Y S x x x S S S S S S S S S S x x x x S S x x x x S x x x x S x x x x S x x x x = C D E F. C + CC+ RES,
49 + = G.( s 2 s 1 s 0 + s 2 s 1 s 0 ), where G = C D E F. C. RES C + = G.(s 2 s 1 s 0 + s 2 s 1 s 0 ) D + = G.(s 2 s 1 s 0 + s 2 s 1 s 0 ) E + = G.s 2 s 1 s 0 F + = G.s 2 s 1 s 0 RDY =. RES, OS1 =. RES, OS2 = C. RES, OS3 = D. RES, OS4 = E. RES, OS5 = F. RES, CC = ( + C + D + E + F). RES Medium 20 Series, 16R6* PL Logic Diagram CLK 1 G G C C D D E E F F RES C s 2 s 1 s 0 NC C + D + E + D Q Q D Q Q D Q Q D Q Q D Q Q C D E G RDY OS1 OS2 OS3 OS4
50 * Device of Monolithic Memories Realization of the Vending Machine Controller using PL CLK 1.4 S 0.5 S RES C RDY OS1 For S = 0 OS2 - OS5 High asic Timing Diagram of the Vending Machine Controller
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