Prasanna U R, Member IEEE and Akshay K. Rathore, Senior Member, IEEE

Transcription

1 1 Extended Range ZVS Active-Clamped Current- Fed Full-Bridge slated Dc/Dc Cnverter fr Fuel Cell Applicats: Analysis, Design and Experimental Results Prasanna U R, Member EEE and Akshay K. Rathre, Senir Member, EEE Abstract This paper presents analysis and design f zervltage switchg (ZVS) active-clamped current-fed full-bridge islated dc/dc cnverter fr fuel cells applicats. The designed cnverter matas ZVS f all switches frm full-lad dwn t very light lad cndit ver wide put vltage variat. Detailed perat, analysis, design, simulat and experimental results fr the prpsed design are presented. The addital auxiliary active clampg circuit absrbs the turn-ff vltage spike limitg the vltage acrss the devices allwg the select and use f lw vltage devices with lw n-state resistance. n addit, it als assists achievg ZVS f semicnductr devices. The cnverter utilizes the energy stred the transfrmer leakage ductance aided by its magnetizg ductance t mata ZVS. ZVS range depends upn the design, particular the rati f leakage and magnetizg ductances f the transfrmer. Rectifier dides perate with zer-current switchg. An experimental cnverter prttype rated at 500W has been designed, built and tested the labratry t verify the analysis, design and perfrmance fr wide variats put vltage and lad. ndex Terms Fuel Cells, High-frequency DC/DC Cnverter, Zer vltage switchg (ZVS), Renewable energy systems C. NTRODUCTON LEAN and green energy fr distributed generat and mdern/future transprtat system has been f creasg terest t the academic and dustrial researchers r cmmunity fr sustaable and smart livg. Pwer cnverter is an essential terface fr the cnvers f nncnvental energy surces t useful and regulated electrical ac r dc frm. Pwer cnverter is a weak and its efficiency determes the utilizat f the surce and cntrls the pwer utput. ts cst, vlume, and weight are the Manuscript received December 6, 011. Accepted fr publicat March, 01. Cpyright (c) 01 EEE. Persnal use f this material is permitted. Hwever, permiss t use this material fr any ther purpses must be btaed frm the EEE by sendg a request t pubs-permisss@ieee.rg. Prasanna U R and A. K. Rathre are with the Department f Electrical and Cmputer Engeerg, Natal University f Sgapre, Sgapre (PH: ; fax: ; s: elepur@nus.edu.sg, eleakr@nus.edu.sg). decidg factrs fr the verall cst and vlume f the stallat system. Therefre, the design and develpment f lw cst, high-efficient and small size pwer cnvers systems is still an attent f researchers [1-]. Even thugh renewable energy surces like slar and wd energy are available free f cst, their utput is nt secure due t their termittent nature. Fuel cells utput is secure and cntuus all seasns as lng as the cntuity f fuel supply is mataed and prduce heat as byprduct that can be used fr c-generat/heatg and thus creases the verall efficiency f the system. Distributed generat fr standalne and gridtied applicats fr residential and remte pwer systems are imprtant applicats. Tw-stage verter, i.e. highfrequency (HF) transfrmer islated dc/dc cnverter fllwed by an verter has been adpted by dustries and has been prpsed with different cnfigurats and mdulats literature t achieve the given bjectives. HF transfrmer islated dc/dc cnverter [-19] translates the lw fuel cell stack vltage t higher than the f the utility le r verter utput vltage specificat with necessary islat. Sft-switchg is necessary t perate the cnverter at HF and t realize small size, light weight and lw cst cnverter. t reduces the thermal stress n the cmpnents, switchg lsses, and imprves the efficiency, particularly at light lad where the switchg and cnduct lsses are cmparable r switchg lsses dmate the cnduct lsses. Many dc/dc cnverter tplgies have been presented fr this applicat [-35] but mst f them are nt able t mata sftswitchg ver the wide pwer variat and entire peratg range f fuel-cell vltage. Cnverter presented [5] is hardswitched and tw devices are cnnected parallel t imprve the efficiency and switchg frequency is 50 khz. nterleaved current-fed full-bridge cnverter reprted [6] is a hardswitched cnverter and therefre perated at 10 khz, which creases the size f magnetics/filters and therefre, f the cnverter. Full-bridge vltage-fed cnverter has several prblems: rectifier dide rgg, duty cycle lss, snubber acrss secndary, pulsatg current at put creases filter size and has limited zer-vltage switchg (ZVS) range [14]. Many addital cmpnents are used t achieve ZVS [8] which is nt a simpler slut and exhibits lwer efficiency.

2 A tplgy similar t [4] is presented [9], but secndary side switches lse ZVS at light lad and higher put vltage, the ZVS range is calculated [14]. A nn-islated bidirectal cnverter with active-clampg has been prpsed [30] fr ZVS up t 40% lad but perat with wide put vltage variat is nt reprted. A slut t achieve ZVS ver 1: surce vltage variat usg several extra cmpnents is given [31] withut discussg ZVS fr variat lad. A cmparisn f sft-switched dc/dc cnverters fr fuel cells t utility terface is given [14] and it was shwn that a tw-ductr half-bridge current-fed islated dc/dc cnverter with active-clamp [, 13, 15, 17, 34-35] is suitable fr such applicats. Active-clamp snubs the vltage turn-ff spike and aids ZVS f HF switches but cannt mata ZVS fr the wide peratg range f lad and put vltage. Als, it has pwer limitat and is nt mdular. Full-bridge currentfed tplgy is mdular nature and is easy t be terleaved due t sgle ductr tplgy with less sensr requirements and less state variable and is suitable fr high pwer. This tplgy has been discussed [0-]. t shuld be nted that the magnetizg ductance makes the transfrmer leakage ductance current cntuus and als creases the number f state variables [1]. Therefre, the perat, analysis and design get mdified due t the third state variable and this was cmpletely neglected the earlier analysis and design [0, ]. Hwever, the analysis and design fr full range ZVS is nt mented. T achieve ZVS fr wide variat put vltage and lad while matag high efficiency has been a challenge, especially fr lw vltage higher current put applicats. This paper trduces a design as a slut t cver ZVS fr wide peratg range. Hard-switchg tplgy fr lw switchg frequency perat is discussed [3-4]. n this paper, an active-clamped current-fed full-bridge dcdc cnverter shwn Fig. 1 with wide/extended range ZVS design and analysis is prpsed. This paper prpses a design withut vlvg extra active and/r passive cmpnents. The prpsed cnverter design matas sft-switchg fr this wide peratg range and matas higher efficiency. The authrs d nt claim n the tplgy. t has been discussed [0-]. The analysis cludg magnetizg ductance effect is studied [1]. Hwever, the authrs claim n the mdified analysis (explag mde by mde perat) alng with the new design with ptimum ductance rati t mata sftswitchg ver wide put vltage and utput pwer. Analytical equats have been reprted t calculate the cmpnents ratg and the perfrmance f the cnverter. The bjectives f this paper are t present the detailed perat, steady-state analysis, design, simulat and experimental results f this cnverter with extended ZVS range. Steady state perat and analysis durg different tervals f perat f the cnverter cludg the effect f magnetizg ductance/current are given Sect. A cmplete design prcedure fr extended range sft-switchg illustrated by design example is presented Sect. Simulat results usg PSM are presented Sect V t verify the analysis and design. An experimental cnverter prttype rated at 500W was built and tested the labratry t validate the design and t test the perat f the cnverter fr wide variats put vltage and lad. Experimental results btaed are presented Sect V. Fig. 1. Active-clamped ZVS current-fed full-bridge DC-DC cnverter.. OPERATON AND ANALYSS OF THE CONVERTER The Steady-state perat and analysis f the prpsed design cludg the effect f magnetizg ductance/current is presented this Sect. The fllwg assumpts are made t study and understand the perat and analysis f the cnverter: 1) nput ductr L is large s that the current thrugh it is cnsidered cnstant. ) Clamp capacitr C a is large t mata cnstant vltage acrss it. 3) All cmpnents cludg devices and dides are ideal. Steady-state peratg wavefrms are shwn Fig.. Switches S 1 and S 4 are perated by identical gatg signals, and S and S 3 are perated by the cmmn gatg signals. Gatg signals f switch pair S, S 3 are shifted phase by 180 with gatg signals f switch pair S 1, S 4 with an verlap. The verlap varies with duty cycle, which varies with put vltage variat. Fixed frequency duty cycle mdulat is used fr cntrl. The duty cycle f the ma switches is always kept greater than 50% t prevent creased circulatg current thrugh the auxiliary active-clamp circuit. Operat f cnverter with duty rati belw 50% results unwanted cnduct lsses causg lwer cnverter efficiency, particularly at partial lad as the auxiliary circuit lss becmes cmparable t the lss the ma switches. The switchg frequency f auxiliary switch S ax is duble f that f ma switches. t is cntrlled by gatg signal cmplementary t the ma switches gatg signals. S, the duty cycle f the auxiliary switch is always less than 50%. The perat f the cnverter durg different tervals a HF half cycle is explaed usg the equivalent circuits shwn Fig. 3. nterval 1 (Fig. 3a; t < t < t 1 ): n this terval, all fur ma switches S 1 ~ S 4 are n. Auxiliary switch S ax is ff. nput ductr L is strg energy. Pwer is transferred t the lad by the energy stred the utput filter capacitr C. Transfrmer magnetizg current circulates thrugh its leakage ductance, given by i = i' Lm = - Lm, (1) where i is transfrmer put r leakage ductance current, i' Lm is magnetizg current reflected t primary side and Lm, is the value f magnetizg current, given by

3 3 n V0 TDR Lm, () Lm where, L and L m are the leakage ductance and magnetizg ductance f the transfrmer referred t primary. T DR is rectifier dide cnduct time. ltage acrss the auxiliary capacitr C a is V V (3) (1 D) ltage acrss the auxiliary switch is V V (4) (1 D) Duty rati f ma switches D = T n /T s ; T n = cnduct time f ma switch and T s = switchg time perid. nterval (Fig. 3b; t 1 < t < t ): At t = t 1, ma switches S and S 3 are turned ff. Current the put bst ductr ( ) is diverted t the auxiliary circuit path causg zer current thrugh all ma switches. The magnetizg current flws thrugh leakage ductance L, anti-parallel dides D 1, D 4 f ma switches S 1 and S 4. Therefre, switch currents thrugh S 1 and S 4 quickly dips t negative, which is equivalent t value f the reflected magnetizg current. Device capacitances C and C 3 f ma switches S and S 3 start chargg and auxiliary switch snubber capacitr C ax starts dischargg learly. On secndary side, rectifier dides are reverse biased and pwer is still transferred t the lad by the utput filter capacitr. The cnstant current ( Lm, ) cntues t flw thrugh magnetizg ductance. At the end f this terval, vltages acrss the ma switch S and auxiliary switch S ax reach V S (t ) = V S3 (t ) = V /n and V (t ) = V -V /n, respectively. nterval 3 (Fig. 3c; t < t < t 3 ): This terval is very shrt. Snubber capacitrs which are partially charged terval, are still gg thrugh chargg and dischargg. The ma switch vltages v S and v S3 crease frm V /n t V. A psitive vltage equal t (V C V /n) appears acrss the transfrmer leakage ductance and current thrugh it, i rises learly. Output vltage V appears acrss the magnetizg ductance L m and current thrugh it starts creasg learly. Rectifier dides DR 1 and DR 4 are frward biased and start cnductg when the leakage ductance current i rises abve i' Lm and pwer is transferred t the lad. The leakage ductance current i is given by vs V / n i Lm,. ( t t) (5) The magnetizg ductance current i Lm is given by ilm Lm,. t-t (6) Lm Lm,p is the current thrugh magnetizg ductance (n secndary side). Current thrugh the switch S 1 is given by vs V / n is1 Lm,. t t (7) L The auxiliary clamp capacitr current i decreases learly and the balance i is transferred t transfrmer thrugh the switches S 1 and S 4 and thus t the lad. At the end f this terval, the auxiliary switch snubber capacitr C ax is discharged cmpletely t zer and C and C 3 are charged t its full vltage, equal t V. Fal values are: vx( t3) v( t3) 0; vs ( t3) vc ( t3) vs3( t3) vc 3( t3) V (1 D) nterval 4 (Fig. 3d; t 3 < t < t 4 ): n this terval, the antiparallel bdy dide D ax f the auxiliary switch S ax starts cnductg and S ax can be gated fr ZVS turn n. Leakage ductance current i is creasg with the slpe f [(V - V /n)/l ]. n this terval, switch current (thrugh S 1 and S 4 ) changes direct t psitive magnitude. Current thrugh the magnetizg ductance is creasg with the same slpe. Transfrmer leakage ductance current i is given by V V / n i i ( t3). t t3 (8) Current thrugh the switch S 1 is given by V V / n is1 is1( t3). t t3 (9) Magnetizg ductance current is given by ilm ilm ( t3). t-t3 (10) Lm Current thrugh auxiliary capacitr durg this terval decreases and is given by V i n,. (t-t3 ) (11) At the end f this terval, i.e., t = t 4, i reaches zer, i reaches and als switch current i S1 reaches. Fal values are: i (t 4 ) = ; i (t 4 ) = 0; i S1 (t 4 ) = i S4 (t 4 ) =. nterval 5 (Fig. 3e; t 4 < t < t 5 ): n this terval, the auxiliary switch S ax is turned n with ZVS. Current i rises abve with the same slpe as terval 4 and current i falls learly belw zer. Magnetizg current i Lm is creasg with the same slpe as terval 4. The equats fr this terval are V n i. t-t 4 (1) L S i i (13) 1 V n i i. t-t 4 (14) Peak value f the switch current is given by: n S1,. 1 D fs L m (15) At the end f this terval, current i rises t negative f ( + Lm, ) and therefre the currents i and i S1 reaches their value. Fal values: i (t 5 ) = -,, ; i (t 5 ) =, ; i S1 (t 5 ) = S1,.

4 4 (c) (d) (e) C L i x is1 S1 A D1 C1 S3 i D3 C3 Lm DR1 ilm DR3 C + RL + i - S D vab C B S4 D4 C4 1:n HF Tr DR DR4 - V (1 D) (f) (1 D) n V (1 D) V n C L i - x + + i - is1 S1 A S D1 D C1 S3 i vab B C S4 D3 C3 D4 C4 Lm DR1 ilm 1:n HF Tr DR DR3 DR4 C + RL - (1 D) n (g) V n Fig.. Steady state peratg wavefrms f current-fed full-bridge DC-DC cnverter with active-clamp. (h) C L i x is1 S1 A D1 C1 S3 i D3 C3 Lm DR1 ilm DR3 C + RL i S D vab C B D4 S4 C4 1:n HF Tr DR DR4 - (i) Fig. 3. Equivalent circuits durg different tervals f perat f the cnverter fr the wavefrms shwn Fig..

5 5 nterval 6 (Fig. 3f; t 5 < t < t 6 ): The auxiliary switch S ax is turned ff at t = t 5. Current i charges C ax and discharges C and C 3. The leakage ductance L resnates with snubber capacitrs C ax and C +C 3. This time terval is very shrt and the leakage ductance current i drps by a small value. The resnant frequency is given by 1 ω r (16) C C3 x ltage acrss the capacitr C r switch S is given by vs V - v (17) where the vltage acrss the switch S ax (r capacitr C ax ) is given by v, s( ωr ( t t5)) (18) ( C C C ) 3 i, cs( ωr ( t t5)) (19) Ma switch current is given by is1 S1, cs( ωr ( t t5 )) (0) At the end f this terval, C and C 3 discharge t V /n and C ax charges t (V - V /n). Fal values are: v (t 6 ) = V - V /n; v S (t 6 ) = V /n; ax nterval 7 (Fig. 3g; t 6 < t < t 7 ): Current i is still chargg C ax and dischargg C and C 3 a resnant fash. t is shrt terval t and the current i decreases a very little this terval. At the end f this terval, the capacitrs C and C 3 discharges cmpletely t zer and capacitr C ax charges t its itial value. Fal values are: v S (t 7 ) = 0; v (t 7 ) = V. nterval 8 (Fig. 3h; t 7 < t < t 8 ): n this terval, anti-parallel bdy dides D and D 3 f ma switches S and S 3 respectively start cnductg and nw S and S 3 can be gated fr ZVS turn n. Current i decreases with a negative slpe f [V /(n L )]. i ( t7). ( t t7) (1) n i D = i () This terval ends when current i =. Fal values are: i D (t 6 ) = 0; i (t 6 ) =. nterval 9 (Fig. 3i; t 8 < t < t 9 ): n this terval, switches S and S 3 are turned n with ZVS. Currents i S and i S3 start creasg and the current i is decreasg with the same slpe. Current i is transferred t the switches S and S 3. The terval ends when current i equals t the current i Lm. Switch S and S 3 current reaches t /- Lm, and S 1 and S 4 current reaches t /+ Lm,. i. (t-t8 ) (3) n L i i. ( t 8) (4) n L S t. (t-t ) (5) n L S1 8 Fal values: i S (t 9 ) = /- Lm, ; i S1 (t 9 ) = /+ Lm, ; i (t 9 ) = i Lm (t 9 ) = Lm,. Fr the next half cycle, the tervals are repeated the same sequence with ther symmetrical devices cnductg t cmplete the full HF cycle. The analysis is dne t bta the design equats t design and select the cmpnents as well as t evaluate the cnverter s perfrmance theretically. Based n this analysis, the design equats were derived and presented next Sect.. EXTENDED RANGE SOFT-SWTCHNG DESGN OF THE CONVERTER n this Sect, cnverter design prcedure fr extended ZVS range is illustrated by a design example fr the fllwg specificats: nput vltage V = t 41 V, utput vltage V = 350 V, utput pwer P = 500W, mimum lad = 10% (50 W), switchg frequency fr H-bridge devices f s = 100 khz and fr auxiliary clamp switch is 00 khz. (1) Average put current is = P /(V ). Assumg an ideal efficiency f 100%, =.7 A. () D max is selected at mimum put vltage, i.e., V = V and full lad which decides the maximum switch vltage ratg V SW(max) usg V V (6) sw,max (1 Dmax) Fr D max = 0.8, V SW(max) = 55 V. (3) nductr values L and L m : Select f leakage ductance L and parallel ductance L m is perfrmed at mimum put vltage and full lad cndit usg (7) btaed frm i and i Lm wavefrms. R L ( / ) ( / ) (1-Dmax ) L (7) ' f s 4(1 / Lm ) n Selectg the ductance values fr a certa rated pwer P and switchg frequency f s depends upn the transfrmer turns rati n, ductr rati L' m /L and the maximum duty cycle D max at full lad calculated earlier. Here L' m refers t equivalent magnetizg ductance referred t primary. Nw the transfrmer turns rati n = N s /N p, is selected t mata D > 0.5, i.e., vltage regulat with lad and fuel cell stack vltage variat given by n V ( / ) f s D 1 (8) 4(1 / Lm ') RL and realizable value f L cludg transfrmer leakage (which is an issue maly fr pwer ratg abve 1 kw) given by (7). Als, n shuld be such that L is psitive, usg (7) n 1 -Dmax 1 / Lm ' (9) Therefre, mimum value f n = 6.4 fr L m = (large value f magnetizg ductance) r n = 7 fr L m /L = 10. Fig. 4 shws the calculated values f L with respect t ductance rati L m /L fr three values f turns rati n.

6 6 nductance rati L m /L is selected based n the ZVS range, and ma switch RMS current given by (30), which shuld be lw fr high efficiency. RMS current thrugh the ma switch is given by 3 D T DR D 4TDR TDR sw, rms Lm, Lm, D 1 4 3T s 3 3 3T s 3T s (30) Here T DR is rectifier dide cnduct time given by nv (31) TDR L V fs 1 L' m Durg derivat, snubber chargg/dischargg tervals (t 1 - t 3, t 5 -t 7, t 10 -t 1, t 14 -t 16 ) f shrt durat are neglected. Fig. 4 shws the calculated values f switch RMS current with respect t L m /L fr fur values f turns rati n. Smaller value f L m /L will achieve ZVS at light lad but crease and rms currents thrugh the switches, leadg t lw efficiency f the cnverter. Fr smaller turns rati, i.e., n = 7, value f L is lw (Fig. 4) and it reduces ZVS range as seen (30). Fr higher transfrmer turns rati, i.e., n = 10, value f L is high (Fig. 4) and creases ZVS range. Chsg a design (at V, full lad) with smaller value f D, say 0.6 fr example (stead f 0.8), will result smaller value f leakage ductance L, which will nt be able t stre sufficient energy t mata ZVS fr the wider put vltage range and light lad cndits. Als, chsg a design (at V, full lad) accrdg t Fig. 4 fr turns rati n > 8, fr example n = 9 r 10, will require higher transfrmer turns rati, resultg auxiliary switch duty cycle D = (1-D) >= 1, which is nt pssible and is the limitat f this cnverter. Therefre, n = 8 with D > 0.5 is chsen. Turns rati n = 8 gives realizable value f L, matas vltage regulat at light lad fr given wide put vltage variat. Therefre, transfrmer turns rati n = 8 is selected. Fig. 4 dicates that fr a given value f n, switch rms current decreases as the rati L m /L creases. Fr the selected value f n = 8, reduct rms current is negligible fr L m /L > 5. Therefre, an ductance rati f L m /L = 5 is selected. Frm the abve discusss, usg D max = 0.8, n = 8 and L m /L = 5, calculated values f ductances are L = 0.4 H and L m = 0.64 mh. (4) Values f put bst ductr is given by L = (V )(D-0.5)/[( )(f s )] (3) where is the bst ductr ripple current. Fr = 0.5 A, L 13H. Maximum vltage acrss the ductr = V = 55 V, given by (3). (5) nductrs ratgs: The RMS current thrugh the leakage and magnetizg ductances are 8T DR 4D 1 8 4T DR rms Lm Lm D1 (33),,, 3T s Ts Fig. 4. Variat f value f leakage ductance L (H), and switch RMS current (A), with respect t ductance rati L m /L fr varius transfrmer turns rati n fr the design example. 4T Lm, DR Lm, rms 1 (34) n 3T s Usg (), Lm, = 5.9 A. Lm,rms is calculated t be 0.55A. Peak magnetizg ductance current = Lm, /n = 0.66A. Usg (31) and (33),,rms = 0.11A. Peak current thrugh L is,, = + Lm, = 50.7 A. Maximum vltage acrss L = V /n = V. Maximum vltage acrss L m = V = 350 V. (6) Switch current ratgs: RMS current thrugh the ma switches sw,rms can be calculated by (30). RMS current thrugh the auxiliary switch is given by auxsw, rms Lm, 1 D/ 3 (35) The values f sw,rms and aux,rms are calculated t be 15A and 10. A respectively. Peak currents thrugh ma switches sw, = + Lm, = 50.7 A and auxiliary switch aux, = + Lm, = 8 A. Average current thrugh auxiliary switch as well as antiparallel dides is given by (1 D),, (36) auxsw av Lm 4 Here, auxsw,av = 1.4A. Average current thrugh the ma switches sw,av = / = A. (7) Auxiliary capacitr: Substitutg (3), V = V and D = 0.8, V = 55 V. The value f auxiliary capacitr C a is, 1 D / 3 (37) 4 f V s

7 7 Peak current thrugh C a is, = + Lm, = 8A. Fr a ripple vltage f V = V, C a 4 F. RMS current thrugh auxiliary capacitr is rms 1 D (38),, 3 Here,,rms = 10. A. Auxiliary capacitr carries a current f 00 khz (twice the switchg frequency). (8) Output rectifier dides: Average rectifier dide current is given by DR,avg = P /(V ) (39) Here, DR,avg 0.7 A. ltage ratg f rectifier dides, V DR = V = 350 V. (9) Output capacitr: Value f utput filter capacitr C is C 0 Ts T V DR (40) ΔV = Allwable ripple utput vltage. C = 4.9 μf fr ΔV = 0.75 V. ts vltage ratg is equal t V = 350 V. (10) Snubber design: The equat fr the calculat f snubber capacitrs is given by t f (41) Lm, C1 C4 C eff 1 D Here, t f = fall time f the switches durg turn-ff. C 1 = C 4 = C ss,s1 ; C a1 = (C 1 + C 4 +C sax ) eff C ss,s1. Fr the selected ma and auxiliary switches PP06CN10NG (V ds = 100 V, D = 100 A, R dsn = 6. mω, C ss = 1 nf, t f = 10 ns), the calculated value f snubber capacitr acrss the auxiliary switch is C a1 =.1 nf. Snubber capacitrs vltage ratg is equal t switch vltage, given by (4) and is 55 V. (11) ZVS Cndits: (A) T achieve ZVS f auxiliary switch, terval, the dead-gap between the ma switch gatg signal G S and auxiliary switch gatg signal G shuld be f sufficient durat t allw chargg f the snubber capacitrs acrss the ma switches C and C 3 and dischargg f snubber capacitr acrss the auxiliary switch C ax, by the bst ductr current. The time required is given by T dg1 ( C C3 x ) 1 D (4) (B) Fr ZVS f ma switches, terval 5 the chargg f the snubber capacitr C ax and dischargg f C and C 3 shuld be dne by the leakage ductance current a quarter f the resnant perid and is equal t the dead-gap between the auxiliary switch gatg signal G and ma switch gatg signal G S and is given by T L C C C (43) dg 3 T dg1 = 1 ns and T dg = 65 ns. dentical dead-gaps T dg1 = T dg = 65 ns is prvided between ma and auxiliary gatg signal. ax The designed values are summarized Table 1. Table. 1. Values f the parameters btaed frm design equats. V -41 V V 350V P 500 W f s 100 khz L 13 H C 4.9 F L 0.4 H L m 0.64 mh n 8 C a 4 F V. SMULATON AND EXPERMENTAL RESULTS The designed cnverter rated at 500W was first simulated usg PSM and then built the labratry t verify the analysis, design and perfrmance f the cnverter. Simulat results fr tw extreme peratg cndits f V = V, full lad and V = 41 V, 10% lad are presented Fig. 5 and Fig. 6, respectively. The cmpnents values btaed frm design and given Table 1 are used as simulat parameters. Simulat wavefrms ccide with the theretical peratg wavefrms shwn Fig.. When bth the ma switches are n, v AB = 0, i Lm is flwg thrugh i and are cnstant. Whenever, ne ma switch is ff, v AB appears acrss the transfrmer and the current i and i Lm change direct. At higher vltage and light lad cndit (Fig. 6), the duty cycle is lw and therefre v AB appears fr lnger time. t makes the currents i and i Lm t be cnstant fr a very small durat and their appearance like triangular shape with higher value cmpared t full lad cndit. Figs. 5-6 shw that the anti-parallel dides f the switches (ma and auxiliary) cnduct prir t the cnduct f crrespndg switches causg zer vltage turn-n. Fig. 5. Simulat wavefrms at V = V and full lad: vltage v AB, leakage ductance current i, and magnetizg ductance current i Lm ma switches currents i S1 and i S, auxiliary switch s current i and vltage acrss auxiliary capacitr V.

8 This article has been accepted fr publicat a future issue f this jurnal, but has nt been fully edited. Cntent may change prir t fal publicat. 8 Fig. 6. Simulat wavefrms at = 41 V and 10% lad: vltage vab, leakage ductance current i, and magnetizg ductance current ilm ma switches currents is1 and is, auxiliary switch s current i and vltage acrss auxiliary capacitr V. t is clear that the leakage ductance current i is cntuus due t the circulat f magnetizg current when all the H-bridge switches are n. t shuld be nticed that with crease put vltage and/r reduct lad current, the duty cycle f ma switches reduces, which results crease value f magnetizg ductance current. t adds t leakage ductance current t achieve ZVS f ma switches even at such a wide variat put vltage and lad. At light lad cndit, anti-parallel bdy dide cnduct time is creased due t magnetizg current assurg ZVS. T bta the simulat results fr given put vltage (V Fig. 5 and 41 V Fig. 6) and fr given lad cndit (45Ω at full lad Fig. 5 and 450Ω at 10% lad Fig. 6) simulat is run fr several HF cycles until the state variables reach a steady-state. deal cmpnents/devices were used. Experimental prttype, as shwn Fig. 7, was built fr the specificats and design given Sect. The details are as fllws: PP06CN10NG (ma and auxiliary switches); RUR-860 (rectifier dides); HF transfrmer: PC40ETD44-Z ferrite cre, primary turns = 9, secndary turns = 7, (primary side) = 0.4 µh, Lm (secndary side) = 33mH; parallel ductr: T106-6, 83 turns, Lp = 0.641mH; bst ductr: MPP Pwder cre, T50-40, 3 turns, L = 00 μh. Due t imperfect rati f /Lm than the desired design value (given the design sect), an extra small size ductr Lp is added ur experimental cnverter used fr verificat f analysis ur lab. n a practical dustrial cnverter, ne can cntrl the magnetizg ductance value clse t the required magnetizg ductance t avid the use f external ductance. Als, slight changes this value shuld nt affect the perfrmance t much. Gatg signals fr the switches have been generated usg Cypress PSC 5 (Prgrammable system-n-chip) bard. R181 driver Cs are used fr gatg the MOSFETs. Variable resistrs (rhestats) are used as lad fr testg. The develped cnverter prttype has been tested at full lad and 10% lad fr = 41 V, and at full lad and 0% lad fr = V. The experimental results are shwn Figs Parts t (e) f Figs clearly cnfirm the ZVS f ma and auxiliary switch ver wide variat fuel cell vltage and lad. n wavefrms shwn part f Figs. 8-11, gatg signals (vgs) are applied t ma switches after vltage acrss them (vds) reaches zer. The ZVS turn n f ma switches is als cnfirmed by part (d) f Figs sce anti-parallel dide is cnductg befre the switch starts cnductg. Similarly, part (e) f Figs. 8-11, anti-parallel dide f the auxiliary switch is cnductg first causg ZVS turn-n f the auxiliary switch. This can be bserved gatg signal (vgs) and vltage acrss the auxiliary switch (vds) as shwn part (c) f Figs ltage acrss the transfrmer vab and the leakage ductance current i cnfirm ZCS f rectifier dides (negligible rgg), as shwn part f Figs t is bserved frm these curves that the experimental values ccide with the calculated values. The experimental wavefrms (Figs. 8-11) illustrate that the cnverter matas ZVS fr all switches ver the cmplete range f lad variat fr wide put vltage range ( t 41V). The designed cnverter matas ZVS dwn t 0% lad at = V and dwn t 5% lad at = 41V. Fig. 7. Experimental labratry prttype f 500 W current-fed full-bridge islated dc/dc cnverter.

9 9 v AB i (c) (c) i S,ma (d) (d) (e) (e) (f) Fig. 8. Experimental wavefrms at V = V and full lad: ltage v AB (100V/div) and leakage ductance current i (50A/div), ma switch vltage v DS (50V/div) and gate vltage v GS (10V/div), (c) auxiliary switch vltage v DS (50V/div) and gate vltage v GS (0V/div), (d) ma switch current i S1 (0A/div), (e) auxiliary switch current i (0A/div) and (f) magnetizg ductance current i Lm (0.5A/div). (f) Fig. 9. Experimental wavefrms at V = 41V and full lad: ltage v AB (50V/div) and leakage ductance current i (50A/div), ma switch vltage v DS (50V/div) and gate vltage v GS (10V/div), (c) auxiliary switch vltage v DS (50V/div) and gate vltage v GS (0V/div), (d) ma switch current i S1 (0 A/div), (e) auxiliary switch current i (10A/div) and (f) magnetizg ductance current i Lm (1A/div).

10 10 (c) (c) (d) (d) (e) (e) Fig. 10. Experimental wavefrms at V = V and 0% lad: ltage v AB (50V/div) and leakage ductance current i (10A/div), ma switch vltage v DS (50V/div), gate vltage v GS (0V/div) and current i S1 (10A/div), (c) auxiliary switch vltage v DS (50V/div) and gate vltage v GS (10V/div), (d) auxiliary switch current i (5A/div) and (e) magnetizg ductance current i Lm (0.5A/div). (f) Fig. 11. Experimental wavefrms at V = 41 V and 10% lad: ltage v AB (50V/div) and leakage ductance current i (10A/div), ma switch vltage v DS (50V/div) and gate vltage v GS (10V/div), (c) auxiliary switch vltage v DS (50V/div) and gate vltage v GS (10V/div), (d) ma switch current i S1 (10A/div), (e) auxiliary switch current i (5A/div) and (f) magnetizg ductance current i Lm (1A/div).

11 11 V. SUMMARY AND CONCLUSONS T achieve ZVS fr wide surce vltage variat and varyg utput pwer/lad while matag high efficiency has been a challenge, especially fr lw vltage higher current put applicats. A ZVS active-clamped current-fed full-bridge islated cnverter has been re-studied this paper. The magnetizg ductance creases the leakage ductance current value at light lad and therefre, the energy stred leakage ductance t mata ZVS f ma switches as well as auxiliary switch. Detailed steady-state perat and analysis f current-fed full-bridge cnverter have been presented. Design t atta sft-switchg ver an extended range f put vltage and lad i.e. utput pwer has been presented. Simulat results usg PSM have been presented. An experimental prttype f the cnverter rated at 500W has been designed, built and tested fr variats put vltage and lad rder t validate the analysis. Experimental results verify the accuracy f the analysis and shw that the prpsed cnfigurat is able t mata ZVS f all switches ver a wide range f lad and put vltage variat due t the variat fuel flw and stack temperature. Theretically, the cnverter is able t mata ZVS till 0% lad at V and 5% lad 41 V. n a practical fuel cell applicat, when the lad current drps due t reduced fuel flw, the light r reduced pwer belw rated pwer is transferred at higher fuel cell vltage. t can be clearly seen and understd als frm the fuel cell V- characteristic. f the lad current r pwer is arund 10% f the rated pwer, then the fuel cell stack vltage creases nearly t 41 V. Hence, the pssibility f the cndit V = V at 10% lad is nly durg transit perid when lad is suddenly changed frm full lad t 10% due t fuel flw adjustment. Hence it is justifiable t have ZVS range f 0% lad at lw put vltage and belw 10% at higher put vltage will cver the peratg range at steady-state. Rated cnverter efficiency f 94% is btaed fr the develped lab prttype rated at 500 W. The cnverter has limitat that duty cycle f the ma switch shuld be greater than 50%. REFERENCES [1] S. Ja, and V. Agarwal, An tegrated hybrid pwer supply fr distributed generat applicats fed by nncnvental energy surces, EEE Transacts n Energy Cnvers, vl. 3, n., June 008, pp [] Y. Lembeye, V. D. Bang, G. Lefevre, and J. P. Ferrieux, Nvel halfbridge ductive DC-DC islated cnverters fr fuel cell applicats, EEE Transacts n Energy Cnvers, vl. 4, 009, pp [3] J. Mazumdar,. Batarseh, N. Kutkut and O. Demirci, High frequency lw cst DC-AC verter design with fuel cell surce hme applicats, Prc. EEE AS Annual Meetg, vl., Oct. 00, pp [4] J. Wang, F. Z. Peng, J. Andersn, A. Jseph and R. Buffenbarger, Lw cst fuel cell cnverter system fr residential pwer generat, EEE Trans. n Pwer Electrnics, vl. 19, n. 5, Sept. 004, pp [5] R. Gpath, S. Kim, J-H. Hahn, P. N. Enjeti, M. B. Yeary and J. W. Hwze, Develpment f a lw cst fuel cell verter system with DSP cntrl, EEE Trans. n Pwer Electrnics, vl. 19, Sept. 004, pp [6] J-T. Kim, B-K Lee, T-W. Lee, S-J. Jang, S-S. Kim, and C-Y. Wn, An active clampg current-fed half-bridge cnverter fr fuel-cell generat systems, Prc. EEE PESC, 004, pp [7] S. K. Mazumder, R. K. Burra, R. Huang, M. Tahir, and K. Acharya, A universal grid-cnnected fuel cell verter fr residential applicat, EEE Trans. n ndustrial Electrnics, vl. 57, 010, pp [8] M. H. Tdrvic, L. Palma and P. Enjeti, Design f a wide put range DC-DC cnverter with a rbust pwer cntrl scheme suitable fr fuel cell pwer cnvers, EEE Trans n ndustrial Electrnics, vl. 55, 008, pp [9] N. Mynand and M. A. E. Andersen, High-efficiency islated bst dcdc cnverter fr high-pwer lw-vltage fuel cell applicats, EEE Transacts n ndustrial Electrnics, vl. 57, 010, pp [10] R. J. Wai, High-efficiency pwer cnvers fr lw pwer fuel cell generat system, EEE Trans. n Pwer Electrnics, vl. 0, n. 4, July 005, pp [11] R. Sharma and H. Ga, A new DC-DC cnverter fr fuel cell pwered distributed residential pwer generat systems, Prc. EEE APEC, March 006, pp [1] J. Lee, J. J, S. Chi and S. B. Han, A 10-kW SOFC lw vltage battery hybrid pwer cnditg system fr residential use, EEE Trans. n Energy Cnvers, vl. 1, n., June 006, pp [13] S. Han, H. Yn, G. Mn, M. Yun, Y. Kim, and K. Lee, A new active clampg zer-vltage switchg PWM current-fed half bridge cnverter, EEE Trans. n Pwer Electrnics, vl. 0, 006, pp [14] A. K. Rathre, A. K. S. Bhat, and R. Oruganti, A cmparisn f sftswitched DC-DC cnverters fr fuel cell t utility terface applicat, EEJ Transacts n ndustry Applicats, vl. 18, N. 4, 008, pp [15] S. J. Jang, C. Y. Wn, B. K. Lee and J. Hur, Fuel cell generat system with a new active clampg current-fed half-bridge cnverter, EEE Trans. n Energy Cnvers, vl., June 007, pp [16] K. J and X. Ruan, Hybrid full-bridge three-level LLC resnant cnverter-a nvel dc-dc cnverter suitable fr fuel-cell pwer system, EEE Trans. n ndustrial Electrnics, vl. 53, 006, pp [17] A. K. Rathre, A. K. S. Bhat, and R. Oruganti, Analysis and design f active-clamped ZVS current-fed DC-DC cnverter fr fuel cells t utility terface applicat, Prc. EEE nternatal Cnf. n ndustrial and nfrmat Systems, Sri Lanka, 007, pp [18] Y. Lembeye, V. D. Bang, G. Lefevre, and J. P. Ferrieux, Nvel halfbridge ductive DC-DC islated cnverters fr fuel cell applicats, EEE Transacts n Energy Cnvers, vl. 4, 009, pp [19] A. K. Rathre, A. K. S. Bhat, and R. Oruganti, Analysis, design, and experimental results f wide range ZVS active-clamped L-L type current-fed DC/DC cnverter fr fuel cells t utility terface, EEE Transacts n ndustrial Electrnics, vl. 59, 01, pp [0] R. Watsn and F. C. Lee, A sft-switched, full-bridge bst cnverter emplyg an active-clamp circuit, Prc. EEE Pwer Electrnics Specialists Cnference 1996, pp [1] V. Yakushev, V. Meleshim, and S. Fraidl, Full bridge islated current fed cnverter with active-clamp, Prc. EEE Applied Pwer Electrnics Cnference and Expsit, 1999, pp [] E. S. Park, S. J. Chi, J. M. Lee, and B. H. Ch, A sft-switchg active-clamp scheme fr islated full-bridge bst cnverter, Prc. EEE Applied Pwer Electrnics Cnference and Expsit, 004, pp [3] M. Mhr and F. W. Fuchs, Clampg fr current-fed de/dc cnverters with recvery f clampg energy fuel cell verter systems, Prc. Eurpean Cnference n Pwer Electrnics and Applicats (EPE), 007 pp [4] A. Averberg, K. R. Meyer, and A. Mertens, Current-fed full-bridge cnverter fr fuel cell systems, Prc. EEE Pwer Electrnics Specialists Cnference, 008, pp [5] J-M. Kwn, and B-H. Kwn, High step-up active-clamp cnverter with put-current dubler and utput-vltage dubler fr fuel cell pwer systems, EEE Transacts n Pwer Electrnics, vl. 4, Jan. 009, pp [6] X. Kng, and A. M. Khambadkne, Analysis and implementat f a high efficiency, terleaved current-fed full bridge cnverter fr fuel cell system, EEE Transacts n Pwer Electrnics, vl., March 007, pp

12 1 [7] S. Jung, Y. Bae, S. Chi, and H. Kim, A lw cst utility teractive verter fr residential fuel cell generat, EEE Transacts n Pwer Electrnics, l., Nv. 007, pp [8] A. J. Masn, D. J. Tschirhart, and P. K. Ja, New ZVS phase shift mdulated full-bridge cnverter tplgies with adaptive energy strage fr SOFC applicat, EEE Transacts n Pwer Electrnics, vl. 3, Jan. 008, pp [9] H. Ta, A. Ktspuls, J. L. Duarte, and M. A. M. Hendrix, Transfrmer-cupled multiprt ZVS bidirectal DC DC Cnverter with wide put range, EEE Transacts n Pwer Electrnics, vl. 3, March 008, pp [30] P. Das, B. Laan, S. A. Musavi, and G. Mschpuls, A nn-islated bidirectal ZVS-PWM active clamped DC DC cnverter, EEE Transacts n Pwer Electrnics, vl. 4, Feb. 009, pp [31] W. Sng, and B. Lehman, Current-fed dual-bridge DC DC cnverter, EEE Transacts n Pwer Electrnics, vl., March 007, pp [3] J. M. Kwn, E. H. Kim, B. H. Kwn, and K. H. Nam High-efficiency fuel cell pwer cnditg system with put current ripple reduct, EEE Trans. n ndustrial Electrnics, vl. 56, 009, pp [33] Q. Li and P. Wlfs, A leakage-ductance-based ZVS tw-ductr bst cnverter with tegrated magnetics, EEE Pwer Electrnics Letters, vl. 3, n., 005, pp [34] F. J. Nme, and. Barbi, A ZVS clampg mde-current-fed push pull DC-DC cnverter, Prc. EEE SE, 1998, pp [35] T.-F. Wu, J.-C. Hung, J.-T. Tsai, C.-T. Tsai, and Y.-M. Chen, An active-clamp push-pull cnverter fr battery surcg applicats, EEE Transacts n ndustry Applicats, vl. 44, 008, pp Dr. Rathre has been listed Marquis Wh s Wh Science and Engeerg 006, Wh s Wh the Wrld, and Wh s Wh America 008. He is a reviewer f EEE Transacts, ET and Elsevier jurnals. Prasanna U R (M 11) received the B.E. degree electrical and electrnics engeerg frm Natal nstitute f Technlgy Karnataka, Surathkal, ndia 006 and the Ph.D. degree pwer electrnics and alternate energy cnvers frm ndian nstitute f Science, Bangalre, ndia March, 011. Currently he is wrkg Electrical and Cmputer Engeerg, Natal University f Sgapre as a Pst-Dctral Research Fellw. His research terests maly clude high frequency sft switchg pwer cnverter, hybrid energy management the field f alternate energy surces, hybrid electric vehicles and mdelg f multi-disciplary energy systems usg bndgraph technique. He is a reviewer f EEE transacts, Elsevier, Jurnal f Frankl nstitute and nderscience. Akshay K Rathre (M 05-SM 1) received his B.E. Electrical Engeerg frm Maharana Pratap University f Agriculture and Technlgy, Udaipur, ndia 001, M.Tech. Electrical Maches and Drives frm nstitute f Technlgy, Banaras Hdu University (T-BHU), Varanasi, ndia 003, and PhD Pwer Electrnics frm University f Victria, BC, nada 008. He wrked as a Lecturer frm Feb, 003-Aug. 004 ndia at Cllege f Technlgy and Engeerg Udaipur and Mdy nstitute f Technlgy and Science, Lakshamangarh. He has been a Sessal Lecturer Department f Electrical and Cmputer Engeerg at University f Victria, BC, nada frm May-Dec 007. He was a pstdctral research fellw at Electrical Maches and Drives Lab, University f Wuppertal, Germany frm Sept. 008-Aug 009. Subsequently, he wrked as a pstdctral research assciate at University f llis at Chicag, USA frm Sep 010 Sept 011. Presently, he is an Assistant Prfessr at Electrical and Cmputer Engeerg, Natal University f Sgapre sce Nv 011. His research terests clude sft-switchg cnverters, high-frequency pwer cnvers, distribut generat, renewable energy surces, clean transprtat, mdulat techniques, and cntrl f mtr drives.