A Non-Insulated Resonant Boost Converter

Transcription

1 A Nn-Insulated Resnant Bst Cnverter Peng Shuai, Yales R. De Nvaes, Francisc Canales and Iv Barbi ISEA-Institute fr Pwer Electrnics and Electrical Drives, RWTH-Aachen University, Aachen, Germany ABB Crprate Research, Dättwil, Switzerland {yales.de-nvaes, INEP-Pwer Electrnics Institute, UFSC-Federal University f Santa Catarina, Flrianóplis, SC, Brazil Abstract In this paper, a resnant bst cnverter is analyzed and verified thrugh experimentatin. Switching lsses are reduced since the cnverter perates at ZCS (Zer Current Switching). The analysis presented here cvers its peratin with variable switching frequency but nly belw the resnant frequency. The range f its vltage gain ges frm 1 t 2 and the energy cnversin efficiency (including filtering at input) is arund 97% fr the lwest input vltage. Its envisined that it culd be applied as a frnt-end cnverter when a backend inverter is needed, fr instance with batteries, phtvltaic cnverters r fuel cells, perfrm partial utput vltage regulatin nly. I. INTRODUCTION Nwadays, resnant techniques have widely been utilized in pwer electrnics cnverters. Cmpared with the cnventinal PWM cnverters, the switching lsses f the resnant cnverters are significantly reduced due t the sft-switching prperties. This allws fr increasing the switching frequency t levels as high as 1 MHz and drastically increasing the pwer density cmpared t hard switched cnverters. Electrmagnetic interference is usually less critical fr resnant cnverters since there are n spikes during cmmutatins (r they are reduced). Althugh resnant cmmutatins have been utilized lng time ag with thyristr semicnductrs, the resnant cnversin evluted frm resnant cnverters t quasi-resnant cnverters and multi-resnant cnverters [1] [2] [3]. Resnant cnverters cntain resnant L-C netwrks and the vltage and current f this netwrks vary sinusidally in ne r mre cmmutatin intervals [4]. The cmmutatin f the switches is usually with zer-vltage switching (ZVS) r zer current switching (ZCS). In this paper, a tw-switch nn-insulated DC-DC bst cnverter using resnant technique is prpsed, investigated and validated at 1 kw and maximum switching frequency f 100 khz. The nly switching lsses f this cnverter ccur because f the energy stred in the parasitic capacitance f the active switch. The riginal dcument where this tplgy is prpsed amng ther resnant and PWM cnverter is [6]. But by cincidence, the cmmutatin cell f this cnverter can be extracted frm the PWM multilevel cnverter presented by [16], hwever the capacitr has a different functinality since in the resnant cnverter it is cmpletely charged and discharged during peratin. This tplgy can als be seen in [9] where a snubber fr the NPC inverter is presented. It becmes mre clear if ne lks at half f the mdulatin cycle f the inverter perating with n lad. In this wrk, the analysis is carried in detail by describing every tplgical stage and its equivalent equatins. The equatin f the static characteristic is btained describing the vltage gain as functin f the lad current and switching frequency. The vltage gain f this cnverter can be cntrlled by cntrlling the switching frequency, the minimum value is 1 and the maximum is 2. Since the maximum gain is limited, it is envisined that this cnverter culd be a gd ptin if the primary energy surce wuld be a battery r phtvltaic string and the utput f this cnverter wuld be cnnected t an inverter. By ding s, assuming a variating input vltage, the resnant cnverter culd regulate the utput vltage partially, limit the lwest value seen by the inverter. This is depicted in Fig. 1, where the resnant cnverter regulates the vltage frm 1 t 2 pu, and the inverter accepts the variatin frm 2 t 2.5 pu withut cmprmising its utput vltage and current quality. In an applicatin, fr instance, ideally the input vltage culd variate frm 200 V t 500V, and the resnant cnverter bsts and regulates its utput vltage t 400V while the input vltage is lwer than 400V. When the input vltage is higher than 400V, then the cnverter culd be by-passed. Fig. 1: Input vltage variatin and regulatin range. II. CONVERTER OPERATION PRINCIPLE The cnverter tplgy investigated in this paper is shwn in Fig. 2. The resnant tank f this nn-insulated cnverter /10/$ IEEE 550

2 is cmpsed f the resnant inductr and the resnant capacitr C r. Tw switches and tw dides are represented as ideal devices. In additin, it is assumed that the utput capacitr C is large enugh, s that the utput vltage V is kept cnstant during ne switching cycle. The cntrl signals D s2 i C r Fig. 2: Cnverter Tplgy. V C f the tw switches are tw cmplementary signals with 50% duty cycle. Each switch turns n fr a half f the switching cycle and in each half cycle there are three switching stages accrding t the peratin f the resnant tank. The peratin stages f the cnverter in a switching cycle are illustrated in Fig. 3. D s2 D s2 V C r i C r V C C R R L r D C V s2 r Stage 1 Stage 2 R D C V s2 r Stage 4 Stage 5 Fig. 3: Representatin f the main tplgical stages. A. Switching Stage 1 [t 0,t 1 ] At t 0, is turned ff and is switched n, dide D s2 is cnducting. During this stage, the resnant capacitr C r is charged by the surce t the vltage level f the utput vltage V. Due t the resnance, the current thrugh the resnant inductr increases sinusidally frm 0 t a certain value, which is suppsed t be I 1. This stage can be described with the fllwing tw equatins: = d dt (t) =C r dv Cr (t) dt i i C C + v Cr (t) (1) (2) R R By assuming that the initial cnditin fr this stage is: { (t 0 )=0 v Cr (t 0 )=0 After mathematical transfrmatin and calculatin, ne can btain the fllwing equatins: (t) = sin (ω 0 t) (3) ω 0 v Cr (t) = [1 cs(ω 0 t)] (4) Where ω 0 =1/ C r is the resnant angular frequency. The inductr current can be parameterized as a functin f the input vltage and the resnant circuit impedance (Z r = /C r ), and the resnant capacitr vltage can be parameterized as a functin f the input vltage, as fllws: (t) = (t) (5) /Z r v Cr (t) = v Cr(t) (6) S, fr this tplgical stage, by applying (5) and (6) t (3) and (4), the parameterized inductr current and capacitr vltage f the resnant tank are: (t) =sin(ω 0 t) (7) v Cr (t) =1 cs(ω 0 t) (8) At the end f this stage, at the time instant t 1, the fllwing equatins are valid: (t 1 )=I 1 (9) v Cr (t 1 )=1 cs(ω 0 t 1 ) (10) where I 1 is defined as the final cnditin f the inductr current at t 1 (I 1 is parameterized). At this time instant, the resnant capacitr vltage is equal t the utput vltage V, therefre: v Cr (t 1 )=G (11) Where G = V / is als the vltage gain f the cnverter. Frm (10) and (11) the duratin f this tplgical stage can be calculated as: ω 0 Δt 10 = π arccs(g 1) (12) Where Δt 10 = t 1 t 0. As usually dne in resnant cnverter analysis [10], a vectr z can be defined as per (13). z = v Cr (t)+j (t) (13) The real part f the vectr z stands fr the vltage n the resnant capacitr while the imaginary part represents the current thrugh the resnant inductr. S the first stage can be described by the fllwing vectr: z 1 =1 cs(ω 0 t)+j sin(ω 0 t)=1 e jω0t (14) This vectr shall be utilized in a next sectin t build a stateplane. 551

3 B. Switching Stage 2 [t 1,t 2 ] At t 1, the resnant capacitr vltage v Cr is equal t the utput vltage V, the dide turns n. S in this stage v Cr is clamped as V, while the current thrugh the inductr drps lineally t zer, since the utput vltage is higher than the input vltage, a negative vltage is applied acrss. By similar mathematical calculatin, the vectr in a state-plane can be derived as: z 2 = G + j[i 1 (G 1)ω 0 (t t 1 )] (15) The duratin f this stage can be calculated as fllwing: C. Stage 3 [t 2,t 3 ] ω 0 Δt 21 = I 1 G 1 (16) As the current becmes 0 at the end f the secnd stage, D s2 blcks, s there is n current thrugh, and the vltage acrss C r remains at V as in stage 2. In this stage, n current is circulating in the circuit. The vectr t describe this stage is then quite simple: z 3 = G (17) F. Stage6[t 5,t 6 ] At the end f stage 5, the current drps t 0 and there is n vltage acrss the resnant capacitr. Thus, in this last stage there is n current thrugh and n vltage acrss C r. Therefre, the vectr f this stage is equal t zer: And the duratin is: z 6 =0 (23) ω 0 Δt 65 = π ω 0 Δt 43 ω 0 Δt 54 (24) G. Summary f the switching behavir The main wavefrms f vltages and currents f the cmpnents are shwn in Fig. 4. The wavefrms f the tw switches v Cr Gate signal fr Gate signal fr S2 The end f this switching stage is half f the whle switching cycle, which means ω 0 t 3 = π. S: D. Stage 4 [t 3,t 4 ] ω 0 Δt 32 = π ω 0 Δt 10 ω 0 Δt 21 (18) v i At the beginning f this stage, is turned-n and starts t cnduct the resnant current. D s2 remains blcked. The resnant capacitr is discharged, s the vltage acrss it drps frm V t 0. At the same time, the current thrugh the inductr increases frm 0 t I 1. The peratin f the cnverter is similar as in the first stage. One can btain similar vectr as fr the first stage: i v z 4 = G 1 cs(ω 0 t) j sin(ω 0 t)=g 1 e jω0t (19) This stage has the same duratin f the first stage: ω 0 Δt 43 = π arccs(g 1) (20) i Ds1 v Ds2 v Ds1 E. Stage 5 [t 4,t 5 ] The peratin f the cnverter in this stage is quite similar as in stage 2, difference is that the resnant capacitr vltage keeps at zer. The vectr related t this stage is: z 5 = j[i 1 (G 1)ω 0 (t t 4 )] (21) i Ds2 t t 0 1 t t 2 3 t4 5 t t6 ( ) T s Fig. 4: Cnverter wavefrms based n analysis with ideal cmpnents. t The duratin f stage 5 is als the same as stage 2, s: ω 0 Δt 54 = I 1 G 1 (22) and tw dides are cmplementary with each ther in each switching cycle. The ZCS (Zer Current Switching) can be clearly seen when lking t the instantaneus values f the vltages and currents f the active switches. In regarding the 552

4 resnant circuit, the vltage acrss the resnant capacitr v Cr is charged t V and then clamped at this value during the first half switching cycle. Then in the secnd half switching cycle the resnant capacitr is discharged and then v Cr becmes zer. The frequency f the current thrugh the resnant inductr is twice f the switching frequency. The average value f the current thrugh Ds 1 dide is dependent n the switching frequency, then the utput vltage can be regulated by the rati between the switching frequency and the resnant frequency. Based n the analysis abve, the cmplete state-plane graph fr the vectr z in a switching cycle can be depicted. The real axis is the parameterized resnant capacitr vltage v Cr, while the imaginary axis is the resnant inductr current, see Fig. 5. Fllwing the directin f the arrws the variatins f the current and vltage during the switching cycle can be seen. The maximum value f the inductr current can be fund 1 characteristic f the cnverter and is depicted in Fig. 6 fr several values f μ 0. The ideal gain is limited between 1 and 2 fr the full range f frequency variatin. This means that the utput vltage cannt be lwer than the input vltage (there wuld be frward cnductin f bth dides), and cannt be higher the twice the input vltage. i AVG increases I G ( t) z 5 z 1 z 4 z 2 Fig. 6: Cnverter gain as a functin f the average utput current, having the frequency rati as parameter z 6 0 G 1 vcr ( 0t) Fig. 5: State-Plane Graph. in the graph as: (ω 0 t) max =1, when v Cr (ω 0 t)=1r v Cr (ω 0 t)=g 1. III. CONVERTER EXTERNAL CHARACTERISTIC Based n the switching behavir f the cnverter, the parameterized average utput current can be calculated by the fllwing equatins: i AV G = f s (( + t5 t 4 t2 (t)dt + t 1 ) (t)dt t4 z 3 t 3 (t)dt + (25) where f s is the switching frequency f the cnverter. (26) f s = 1 T s (27) G i AV G = μ 0 (28) 2π(G 1) In this equatin μ 0 =2πf s /ω 0, which is the rati between the switching frequency f s and the resnant frequency f 0. The time instants can be btained by the switching stage duratin calculated previusly. This equatin describes the external It is imprtant t highlight that in this study it is assumed that the switching frequency is always lwer than the resnant frequency, i.e. f s f 0 r 0 < μ 0 1. By using the resnant impedance Z r t parameterize the lad resistance, the fllwing rati can be intrduced: r = R /Z r (29) With this rati, the fllwing equatin can be derived: G = r i AV G (30) By substituting (28) and (29) int (30), (31) can be btained. G = μ 0 2π r +1 (31) The relatinship described by (31) is shwn in Fig. 7. It can be r 0.1 r r r 5 r 2 G r r 20 r r Fig. 7: Dependence f Gain G n frequency rati and gain. seen that, fr a cnstant lad and cnstant input vltage, the 553

5 utput vltage changes linearly with μ 0. This means the utput vltage can be easily t cntrl. Nw, if it is necessary t perate the cnverter ver the full range f gain variatin, the relatin (32) has t be respected. If a wide range f frequency variatin is required, then r shuld be equal t 2π. r 2π (32) IV. EXPERIMENTAL VALIDATION In rder t verify the theretical analysis and t verify the cncepts, a prttype rated at the fllwing specificatins has been built and tested: Output pwer: P =1kW Regulated utput vltage: V = 400V Input vltage: 200V 400V r =2π Z r = R /r =25.46Ω Resnant inductr and capacitr: = 39.69μH, C r = 61.2nF Resnant frequency: f 0 = 102.1kHz Output capacitr: C = 110μF Anther cnstrain added t the specificatin is that the cnverter shuld be able t withstand an input vltage f 500 V. In this case, abve 400V there will nt be regulatin f the utput vltage and this cnverter culd be bypassed by an additinal dide r a mechanical switch. A suppsed applicatin where this makes sense wuld be a tw stages cnverter where the secnd stage culd be an inverter able t regulate its AC variables while having its input vltage variating frm 400 t 500V maximum. The utilized silicn semicnductr devices were rated at 600 V as breakdwn vltage. Fig. 8 shws the resnant inductr current, resnant capacitr vltage v Cr and the input and utput vltage fr peratin at maximum pwer and minimum input vltage. As expected, since this frequency is almst the resnant frequency, the wavefrms f the resnant tank are sinusidal. The input vltage is 200V while the utput vltage is 400V, the maximum gain G=2 is reached. The peak f v Cr is equal t the utput vltage while the peak f is apprximately 7.8A as calculated frm /Zr. V ( 2) V( 3) i ( 1) (1 & 4) vcr ( 4) Fig. 8:, v Cr, and f s = 100kHz, P =1kW. Fig 9 is shwing the active switch cmmutatins. The turnn is depicted in Fig. 9 (a). Frm this figure it can be seen that there are reduced switching lsses since the current increases sinusidally frm zer. The nly switching lsses ccur due t the intrinsic capacitance f the active switch, in this case MOSFET. The turn-ff behavir is shwn in Fig. 9 (b). As the instantaneus values f current and vltage are nt verlapping the turn-ff lsses can be neglected. (2 & 3) (2 & 3) Turn-n Gate Signal(4) i ( 2) Gate Signal(4) (a) Turn-n Turn-ff (b) Turn-ff i ( 2) Fig. 9: Cmmutatin f the switching devices at f s = 100kHz. The wavefrms f the dide current and reverse vltage are shwn in Fig. 10. The reverse recvery f the dide can hardly be fund frm the wavefrm, s almst n lss is prduced by the reverse recvery current. Fig. 11 illustrates the behavirs f the current and vltage f MOSFET at f s =50kHz. The scillatins in the MOS- FET vltage and current wavefrms are due t the parasitic capacitance. In rder t verify the peratin at high input vltage, the cnverter has been tested at f s = 5kHz and full pwer, the wavefrms can be fund in Fig. 12. At this switching frequency, the input vltage is quite clse t the utput vltage. As the designed specificatin, the input vltage can vary frm 200V t 400V, while keeping the utput vltage at 400V and the utput pwer at 1kW. The efficiency curve f this cnverter, cnsidering the 554

6 vcr ( 4) ( 1) V ( 2) V( 3) i (1 & 4) Ds1 Turn-n i ( 2) Ds1 Turn-ff vcr ( 4) ( 1) (2 & 3) (1 & 4) Fig. 10: Dide reverse vltage and f s = 100kHz, P =1kW. Fig. 12:, v Cr, and f s =5kHz, P =1kW i ( 2) (2 & 3) Turn-n v ( 4) i ( 1) Cr Lr Turn-ff [ W ] Output Pwer Fig. 13: Efficiency curve f 1kW prttype by pwer variatin. (1 & 4) Fig. 11: MOSFET current and vltage f s = 50kHz, P =1kW. variatin f the utput pwer while keeping the input and utput vltage cnstants and gain equal t 2 is depicted in Fig. 13. At nminal pwer the efficiency is abut 97 %. The highest efficiency ver the lad range is at arund 60% f the full lad, which is abut 97.8%. The efficiency curve has als been btained cnsidering input vltage variatin, while keeping the uput vltage cnstant at 400V and utput pwer at 1 kw. The results are presented in Fig. 14. As expected fr this cnverter, fr higher input vltage the efficiency is higher. V. CONCLUSION A tw-switches bst resnant cnverter capable f stepping-up the input vltage by 2 times has been analyzed and prpsed in this paper. The utilized mechanism t cntrl the pwer flw is implemented by variating the switching frequency, while keeping it belw the resnant frequency. Bth active switch cmmutatins are sft and the nly switching lsses ccur due t the energy stred in the parasitic capacitance f the active switch. Detailed analysis and experimentatin shwn that this cnverter has ptential fr applicatin where high efficiency and simplicity are needed while its limited gain wuld nt be a drawback. With an apprpriate dimensining f the resnant Trend line 10k 20k 30k 40k 50k 60k 70k 80k 90k 100k f s [ Hz] Fig. 14: Efficiency as a functin f switching frequency (r input vltage) with cnstant utput pwer and vltage. cmpnents, the cnverter reactive energy circulatin culd be kept at lw values, nt cmprmising the efficiency. An efficiency arund 97 % was btained by utilizing 600 V MOSFETs (80 mω ). Due t its reduced switching lsses, this cnverter has ptential fr applicatins where high pwer density is required. REFERENCES [1] F.C. Lee, High-Frequency Quasi-Resnant and Multi-Resnant Cnverter Technlgies, Prceedings f the Internatinal Cnference n Industrial Electrnics, Singapre, Octber 24-28,1988, pp [2] W.A. Tabisz and M.M. Jvanvić and F.C. Lee, High-Frequency Multi- Resnant Cnverter Technlgy and Its Applicatins, Prceedings f the Internatinal Cnference n Pwer Electrnics and Variable Speed Drives, Lndn, England, July 17-19,1990, pp.1-8. [3] G. Hua and F.C. Lee, An Overview f Sf-Switching Techniques fr PWM Cnverters, Prceedings f the Internatinal Cnference n Pwer 555

7 Electrnics and Mtin Cntrl, Beijing, ina, June 27-30,1994, pp [4] Rbert W. Ericksn and Dragan Maksimvić, Fundamentals f Pwer Electrnics, 2nd ed. New Yrk, Bstn, Drdrecht, Lndn, Mscw: Kluwer Academic Publishers, [5] Muhammad H. Rashid, Pwer Electrnics Handbk, San Dieg, San Francisc, New Yrk, Bstn, Lndn, Sydney, Tky: Academic Press, [6] Barbi, I. and Tmaselli, L. C. and Guedes, J. A. M., Buck, Bst and Buck-Bst resnant cnverters with sft switching and clamped capacitr vltage, Internal Reprt, INEP/UFSC, [7] T.M. Undeland, Snubbers fr Pulse Width Mdulated Bridge Cnverters With Pwer Transistrs r GTOs, Prceedings f IPEC, vl.1, Tky, 1983, pp [8] Péres, Adrian and Barbi, Iv, Experimental results f the new ZVS PWM vltage surce inverter with active vltage clamping and cmparisn with classical structures, Prceedings f Telecmmunicatins Energy Cnference, Phenix, AZ, 2000, pp [9] De Nvaes, Y. R. and Barbi, Iv, Analysis, Design and Experimentatin f a Snubber fr the Three-level Neutral Clamped Inverter, Prceedings f Cngress brasileir de eletrônica de ptência, Flrianóplia, [10] M.M. Jvanvić and K.H. Liu and R. Qruganti and F.C. Lee, State- Plane Analysis f Quasi-Resnant Cnverters, IEEE Transactins n Pwer Electrnics, vl. 2, pp.56-73, January, [11] K.D.T. Ng, Generalizatin f Resnant Switches and Quasi-Resnant DC-DC Cnverters, Prceedings f IEEE Pwer Electrnics Specialists Cnference, Blaksburg, Va, 1987, pp [12] Jai P. Agrawal, Pwer Electrnic Systems: Thery and Design, Upper Saddle River, NJ: Prentice Hall, [13] Seri Lee, Optimum Design and Selectin f Heat Sinks, IEEE Transactins n Cmpnents, Packaging, and Manufacturing Technlgy, Part A, vl. 18, pp , December, [14] Rn Lenk, Practical Design f Pwer Supplies, Muntain View, Califrnia: Wiley-IEEE Press, [15] Mark J.Nave, Multi-level cnversin: high vltage chppers and vltage-surce inverters, New Yrk: Van Nstrand Reinhld, [16] Meynard, T.A. and Fch, H., Pwer Line Filter Design fr Switched- Mde Pwer Supplies, Pwer Electrnics Specialists Cnference, PESC92, 1992, vl.1, pg