Multi Level Reinjection ac/dc Converters for HVDC

Transcription

1 Multi Level Reinjectin ac/dc Cnverters fr HVDC Lasantha Bernard Perera A thesis presented fr the degree f Dctr f Philsphy in Electrical and Cmputer Engineering at the University f Canterbury, Christchurch, New Zealand. February 26

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3 ABSTRACT A new cncept, the multi level vltage/current reinjectin ac/dc cnversin, is described in this thesis. Nvel vltage and current surce cnverter cnfiguratins, based n vltage and current reinjectin cncepts are prpsed. These cnverter cnfiguratins are thrughly analyzed in their ac and dc system sides. The fundamentals f the reinjectin cncept is discussed briefly, which lead t the derivatin f the ideal reinjectin wavefrm fr cmplete harmnic cancellatin and apprximatins fr practical implementatin. The cncept f multi level vltage reinjectin VSC is demnstrated thrugh tw types f cnfiguratins, based n standard 12-pulse parallel and series cnnected VSC mdified with reinjectin bridges and transfrmers. Firing cntrl strategies and steady state wavefrm analysis are presented and verified by EMTDC simulatins. The multi level current reinjectin CSC is als described using tw cnfiguratins based n standard 12-pulse parallel and series cnnected CSC mdified with assciated reinjectin circuitry. Firing cntrl strategies and steady state wavefrm analysis are presented and verified by EMTDC simulatins. Taking the advantage f zer current switching in the main bridge valves, achieved thrugh multi level current reinjectin, an advanced multi level current reinjectin scheme, cnsisting thyristr main bridges and self-cmmutated reinjectin circuitry is prpsed. This hybrid scheme effectively incrprates self-cmmutated capability int a cnventinal thyristr cnverter. The ability f the main bridge valves t cmmutate withut the assistance f a turn-ff pulse r line cmmutating vltage under the zer current cnditin is explained and verified by EMTDC simulatins. Finally, the applicatins f the MLCR-CSC are discussed in terms f a back t back HVDC link and a lng distance HVDC transmissin system. The pwer and cntrl structures and clsed lp cntrl strategies are presented. Dynamic simulatin is carried ut n PSCAD/EMTDC t demnstrate the tw systems ability t respnd t varying active and reactive pwer perating cnditins.

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5 ACKNOWLEDGEMENTS There are number f peple whm I wish t express my heartfelt gratitude fr their invlvement in achieving smething which I have dreamt frm the day I entered the university t d my undergraduate studies. First and fremst I wuld like t thank my supervisrs, Assciate Prfessr Neville Watsn and Emeritus Prfessr Js Arrillaga fr their cntinuus guidance, supprt and encuragement thrughut the curse f this research. Their patience, understanding and kindness have helped me a lt mre than they have realized, especially during the times I failed t prgress. Thank yu bth fr pening me the drs f fascinating wrld f research. I am particularly grateful t Dr. Ynghe Liu fr his guidance and help thrughut the initial stages f my research. Withut his patience t have lengthy discussin sessins and brader knwledge n subject, cmpletin f my wrk wuld have taken much mre time than this. I am als grateful t New Zealand Cmmnwealth Schlarship and Fellwship Plan fr granting me a Cmmnwealth Schlarship enabling my study in New Zealand. Special thanks must g t the staff and pstgraduates in this department, wh all cntribute t make this a friendly and stimulating envirnment in which t wrk; especially t pwer systems pstgraduate clleagues past and present, fr their help, supprt and friendship. Special mentin must g t Dr. David Hume, Dave Rentul, Suman Pudel, Zaid Mhamed, Jhn Schönberger, Kent Yu, Chris Cllins, Geff Lve, Xin Liu, Jiak San Tan, Simn Bell and Nikki Newham.

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7 CONTENTS ABSTRACT ACKNOWLEDGEMENTS GLOSSARY LIST OF FIGURES LIST OF TABLES iii v xvii xx xx CHAPTER 1 INTRODUCTION Multi level and sft switching cncepts fr high pwer cnversin Harmnic eliminatin by reinjectin cnversin Thesis bjective Thesis utline 8 CHAPTER 2 FUNDAMENTALS OF THE REINJECTION CONCEPT Intrductin Cnditins fr cmplete harmnic eliminatin Harmnic eliminatin in 12-pulse CSC Harmnic eliminatin in 12-pulse VSC Reinjectin wavefrms Ideal reinjectin wavefrm Symmetrical reinjectin wavefrms Synthesis f reinjectin wavefrms Cnclusins 21 CHAPTER 3 MULTI LEVEL VOLTAGE REINJECTION VSC Intrductin Parallel cnnected cnfiguratin Analysis f the vltage wavefrms Analysis f utput current Analysis f reinjectin currents Cmpnent ratings 35

8 viii CONTENTS Transfrmer ratings 35 Switching devices 38 DC side capacitance PSCAD/EMTDC verificatin Series cnnected cnfiguratin Analysis f the vltage wavefrms Analysis f utput current wavefrms Analysis f reinjectin currents Cmpnent ratings 53 Transfrmer ratings 54 Switching devices 56 DC side capacitance PSCAD/EMTDC verificatin Cnclusins 63 CHAPTER 4 MULTI LEVEL CURRENT REINJECTION CSC Intrductin Parallel cnnected cnfiguratin Operating principle Analysis f the utput current wavefrms Analysis f dc side vltage wavefrms Magnetizatin current calculatin in the multi-tapped reactr Cmpnent ratings 78 Interface transfrmer 78 Multi-tapped reactr 79 Switching devices PSCAD/EMTDC verificatin Series cnnected cnfiguratin Operating principle Analysis f the utput current wavefrms Analysis f dc side vltage wavefrms Magnetizatin current calculatin in reinjectin transfrmers DC blcking capacitrs Effect f capacitr ripple vltage n the dc utput vltage Cmpnent ratings 99 Interface transfrmer 1 Reinjectin transfrmers 11 Switching devices 11 Blcking capacitrs PSCAD/EMTDC verificatin Cnclusins 13

9 CONTENTS ix CHAPTER 5 MLCR-CSC WITH THYRISTOR-BASED MAIN BRIDGES Intrductin Series cnfiguratin with thyristr main bridges Operating principle Output current and dc side vltage wavefrms PSCAD/EMTDC verificatin Cnclusins 112 CHAPTER 6 MLCR-CSC IN HVDC SYSTEMS Intrductin MLCR-CSC back t back HVDC link Pwer and cntrl structure Simulated perfrmance 121 Respnse t active pwer changes 121 Respnse t reactive pwer changes MLCR-CSC lng distance HVDC transmissin system Pwer and cntrl structure Simulated perfrmance under nrmal peratin 125 Respnse t active pwer changes 125 Respnse t reactive pwer changes Simulated perfrmance fllwing disturbances 134 Respnse t an ac system fault 134 Respnse t a dc system fault Summary f the simulatin studies MLCR-CSC back t back HVDC link MLCR-CSC lng distance HVDC transmissin system 14 CHAPTER 7 GENERAL CONCLUSIONS AND FURTHER WORK General cnclusins Multi level reinjectin wavefrms Multi level vltage reinjectin VSC Multi level current reinjectin CSC Further wrk MLVR-VSC lng distance HVDC transmissin Multi terminal HVDC transmissin Independent reactive pwer cntrl f MLCR-CSC HVDC systems MLCR-CSC in supercnducting magnetic energy strage systems 145 APPENDIX A MULTI LEVEL LINEAR REINJECTION WAVEFORMS 147

10 x CONTENTS APPENDIX B MULTI LEVEL ESEDS REINJECTION WAVEFORMS 149 APPENDIX C PUBLICATIONS 151 REFERENCES 153

11 LIST OF FIGURES 2.1 The 12-pulse CSC cnfiguratin Firing sequence f 12-pulse CSC Ideal reinjectin wavefrms fr 12-pulse CSC The 12-pulse VSC cnfiguratin Firing sequence f 12-pulse VSC Vltage wavefrms f 12-pulse VSC with ideal reinjectin The ideal reinjectin wavefrms Current wavefrms f 12-pulse CSC with ESEDS reinjectin Current wavefrms f 12-pulse CSC with linear reinjectin Parallel MLVR-VSC cnfiguratin Parallel MLVR-VSC vltage wavefrms VSC system mdel Output current wavefrms f parallel MLVR-VSC Spectrum f utput currents Current wavefrms f the parallel MLVR-VSC Variatin f reinjectin bridge GTO and dide RMS currents with pwer angle Variatin f reinjectin bridge GTO and dide RMS currents with pwer angle Simulated vltage wavefrms f parallel MLVR-VSC Simulated utput current wavefrm f parallel MLVR-VSC Series MLVR-VSC cnfiguratin Series MLVR-VSC vltage wavefrms Current wavefrms f the series MLVR-VSC Reinjectin current i j fr different θ DC side current wavefrms f the series MLVR-VSC 54

12 xii LIST OF FIGURES 3.16 RMS current thrugh GTOs f reinjectin bridge cnnected t Y -cnnected main bridge RMS current thrugh dides f reinjectin bridge cnnected t Y -cnnected main bridge RMS current thrugh GTOs f reinjectin bridge cnnected t -cnnected main bridge RMS current thrugh dides f reinjectin bridge cnnected t -cnnected main bridge Simulated wavefrms and spectra f MLVR-VSC MLCR-CSC parallel cnfiguratin Firing sequence f the MLCR-CSC level current reinjectin CSC cnfiguratin Current wavefrms f the MLCR-CSC DC side vltage wavefrms f MLCR-CSC DC side vltage harmnics and spectrum Multi-tapped reactr RMS vltage versus α Path f the magnetizatin current Magnetizatin current in the multi-tapped reactr Current in the first winding f the multi-tapped reactr Simulated current wavefrms f MLCR-CSC Simulated dc vltage wavefrm f MLCR-CSC MLCR-CSC series cnfiguratin Firing sequence f the MLCR-CSC level current reinjectin CSC cnfiguratin Current wavefrms f the MLCR-CSC DC side vltage wavefrms f MLCR-CSC DC side vltage harmnics and spectrum Reinjectin transfrmer primary RMS vltage versus α Paths f the magnetizatin current Magnetizatin current in reinjectin transfrmers Variatin f negative peak f the magnetizatin current with α DC blcking capacitr ripple vltages DC side vltage harmnics variatin with ripple vltage Simulated current wavefrms f MLCR-CSC Simulated dc vltage wavefrm f MLCR-CSC 15

13 LIST OF FIGURES xiii 5.1 MLCR-CSC series cnfiguratin with thyristr main bridges Current wavefrms f the MLCR-CSC DC side vltage wavefrms f the MLCR-CSC Spectrum f the dc lad vltage f the MLCR-CSC Simulated current wavefrms f the MLCR-CSC Simulated dc vltage wavefrm f the MLCR-CSC level current reinjectin parallel hybrid CSC cnfiguratin MLCR-CSC BTB link mdel Cnnectin f dual MLCR-CSC cnverters in BTB link MLCR-CSC BTB link cntrl blck diagram fr active and reactive pwer cntrl MLCR-CSC BTB link cntrl blck diagram fr real and imaginary current cntrl Operating regins f the tw cnverters The MLCR-CSC BTB link cntrl structure Real and reactive pwer respnse t a real pwer rder Respnse f MLCR-CSC BTB link t a real pwer rder Real and reactive pwer respnse t a reactive pwer rder Respnse f MLCR-CSC BTB link t a reactive pwer rder Cnnectin f dual MLCR-CSC cnverters in HVDC transmissin system Real and reactive pwer respnse t a real pwer rder Respnse f MLCR-CSC HVDC link t a real pwer rder Real and reactive pwer respnse t a reactive pwer rder Respnse f MLCR-CSC HVDC link t a reactive pwer rder The effect f OLTC n terminal vltage Respnse f MLCR-CSC HVDC system t an ac fault Expanded vltage and current wavefrms f MLCR-CSC HVDC system Respnse f MLCR-CSC HVDC system t a dc fault 139

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15 LIST OF TABLES level reinjectin vltage and switching cmbinatins Interface transfrmer ratings Reinjectin transfrmer ratings level reinjectin vltage and switching cmbinatins level reinjectin vltage and switching cmbinatins Reinjectin transfrmer ratings Reinjectin switching cmbinatins and multi-level reinjectin current Reinjectin switching cmbinatins and multi-level reinjectin current Reinjectin switching cmbinatins and 5-level reinjectin current 19

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17 GLOSSARY Abbreviatins ac BTB CC CSC dc ESEDS FACTS GTO HVDC IGBT IGCT MLCR MLCR-CSC MLVR MLVR-VSC MTDC NPC OLTC pu PI PWM PWM-VSC RCD RMS SCR SMES STATCOM THD VSC Alternating Current Back T Back Cmmn Cathde Current Surce Cnverter Direct Current Errr Square Errr Derivative Square Flexible AC Transmissin System Gate Turn Off Thyristr High Vltage Direct Current Insulated Gate Biplar Junctin Transistr Integrated Gate Cmmutated Thyristr Multi Level Current Reinjectin Multi Level Current Reinjectin Current Surce Cnverter Multi Level Vltage Reinjectin Multi Level Vltage Reinjectin Vltage Surce Cnverter Multi Terminal Direct Current Neutral Pint Clamped On Lad Tap Change per unit Prprtin and Integratin Pulse Width Mdulatin Pulse Width Mdulatin Vltage Surce Cnverter Resistr Capacitr Dide Rt Mean Square Shrt Circuit Rati Supercnducting Magnetic Energy Strage Static Synchrnus Cmpensatr Ttal Harmnic Distrtin Vltage Surce Cnverter

18 xviii GLOSSARY ZCS ZVS Zer Current Switching Zer Vltage Switching Symbls α ω φ θ F reinj F surce H Li H Si i dc i dc i Y dc I a I ay I ay n I A1 I An I ARMS I B I BY I ca I ca n I CR I dc I Im I jgdrms I Re I SR I A I k j k n k s L m Delay firing angle f the main bridge switches f the reinjectin CSC Angular frequency f the surce Phase displacement between ac surce and VSC utput vltages Phase displacement between the cnverter system utput current and vltage Reinjectin transfrmer perating frequency Surce frequency i th level height f an m-level linear reinjectin wavefrm i th level height f an m-level ESEDS reinjectin wavefrm DC side current f the cnnected bridge Current thrugh the dc capacitr bank DC side current f the Y cnnected bridge Output line current f the cnnected bridge Output line current f the Y cnnected bridge n th harmnic cmpnent f the line current f the Y cnnected bridge Fundamental cmpnent f the cnverter system utput current n th harmnic cmpnent f the cnverter system utput current RMS value f the cnverter system utput line current DC side utput current f the cnnected bridge DC side utput current f the Y cnnected bridge Phase current f the cnnected bridge n th harmnic cmpnent f the phase current f the cnnected bridge Rated RMS current rating f the dc blcking capacitr DC side current f the reinjectin CSC Imaginary current cmpnent RMS current rating f the reinjectin bridge switches f the reinjectin VSC Real current cmpnent Cnverter system rated current Output line current f the cnverter system Three phase utput current vectr f the reinjectin VSC Turns rati f the reinjectin transfrmer Turns rati f the interface transfrmer Nminal leakage reactance f the interface transfrmer Inductance f the dc link

19 GLOSSARY xix P Active pwer P ref Q Q ref R S THD I THD V U CR U dc v dcr V a V A1 V An V ARMS V CR V dc V dcy V ppr Active pwer reference rder Reactive pwer Reactive pwer reference rder Resistance f the dc link Cnverter system nminal apparent pwer Ttal harmnic distrtin f the cnverter system utput current Ttal harmnic distrtin f the cnverter system utput vltage Rated vltage f the capacitr bank Vltage acrss the dc capacitr bank Ripple vltage f the dc capacitr Output phase vltage f the cnnected bridge Fundamental cmpnent f the utput phase vltage f the cnverter system n th harmnic cmpnent f the utput phase vltage f the cnverter system RMS value f the cnverter phase utput vltage Rated vltage acrss the dc blcking capacitr DC side vltage acrss the cnnected bridge DC side vltage acrss the Y cnnected bridge Peak t peak ripple vltage f the dc side capacitr f the reinjectin VSC V ppr12 Peak t peak ripple vltage f the dc side capacitr f a standard 12- pulse VSC V SR V Y V Y a V Y Y V A V V s X s Cnverter system rated vltage DC side vltage applied acrss the cnnected bridge Output phase vltage f the Y cnnected bridge DC side vltage applied acrss the Y cnnected bridge Output phase vltage f the cnverter system Three phase utput vltage vectr f the reinjectin VSC Three phase vltage vectr f the ac surce Leakage reactance f the interface transfrmer

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21 Chapter 1 INTRODUCTION In recent years, the high pwer self-cmmutated ac/dc cnverters have becme an intrinsic cnstituent in many industry and pwer system applicatins, mainly due t their superir features ver cnventinal line cmmutated thyristr based cnverters, such as the flexibility f cntrlling reactive pwer frm lead t lag and the ability f supplying active pwer t weak r even passive netwrks. The need t maintain high efficiency, frced these cnverters t be cnnected t high vltages, typically few hundreds f kil vlts. Fllwing the intrductin f the gate turn ff (GTO) thyristr in the 7 s, there has been a remarkable imprvement in high pwer self-cmmutated switching devices. Many new devices based n bth thyristr and transistr technlgies have becme available with higher ratings and enhanced switching characteristics. This has resulted in the GTO, being increasingly replaced by insulated gate biplar transistr (IGBT) and integrated gate cmmutated thyristr (IGCT) [1 4], in applicatins such as adjustable speed drives and railway interties, mainly due t its requirements f cstly snubber circuits t suppress nnhmgeneus turn-n and turn-ff transients and bulky gate drives. Bth type f devices have ptential t decrease the csts and increase the pwer density; the IGCT is further advantaged with prven thyristr technlgy. Cmmercially available ratings f these devices are 3.3 kv/1.2 ka (Eupec), 4.5 kv/2 ka (Fuji), 5.2 kv/2 ka (ABB) fr IGBT and 5.5 kv/2.3 ka (ABB), 6 kv/6 ka (Mitsubishi) fr IGCT. There has been significant amunt f research carried ut int imprving the vltage rating f IGCT [5,6], where wrld s first 1 kv IGCT [7] is nt very far frm being a reality. Mrever, the press pack mdules [8, 9] f these high pwer switching devices, are fabricated in such a way, that they behave as shrt circuits upn failure. This enables, series cnnectin f devices in stack, t frm high vltage rating valves with redundancy fr individual device failure, securing a high availability f the system and minimizing the need fr peridic maintenance. Many flexible ac transmissin systems (FACTS) [1 16], based n self-cmmutated ac/dc cnverters are currently in peratin, which became practically pssible thrugh

22 2 CHAPTER 1 INTRODUCTION the wide spectrum f cmmercially available devices with higher ratings. High pwer cnverter design has gained much attentin in research during the last tw decades in respnse t the ever grwing demand frm the industry. Increased pwer rating, enhanced perfrmance, reduced harmnic cntent, imprved dynamic respnse and reduced pwer lsses had been the key areas f interest. Many nvel designs and cncepts such as multi level cnverter tplgies and sft switching have evlved, accmplishing mst f the gals afresaid. 1.1 MULTI LEVEL AND SOFT SWITCHING CONCEPTS FOR HIGH POWER CONVERSION Taking the present day self-cmmutated device ratings int cnsideratin, a six pulse bridge cnverter with ne pwer switch per psitin can nly reach a maximum pwer rating f abut 1 MVA. This indicates that, high pwer applicatins need either bridge r device cmbinatins in series and parallel t achieve the necessary pwer ratings. The practical current ratings f pwer cmpnents such as cables and transfrmers (typically 1.5 ka) have restricted the maximum pwer rating f lw vltage ac/dc selfcmmutated cnverters belw 2 MVA. Therefre, especially fr pwer ratings beynd 5 MVA, medium and high vltage cnverters are preferred, due t the fact that they can achieve significant savings and imprved thermal perfrmance f pwer cmpnents. In rder t achieve these high vltages, switching devices need t be cnnected in series. These series switching devices can be fired either synchrnusly r asynchrnusly. The synchrnus cntrl f direct series cnnectin f switching devices presents prblems f static balancing, dynamic balancing and high dv/dt, which makes it unsuitable fr high pwer and high vltage applicatins. Attempts t slve these prblems have resulted in the develpment f the multi level cncept, which enables asynchrnus firing cntrl f the direct series cnnected switching devices. Researchers have cme up with varius multi level vltage surce cnverter (VSC) cnfiguratins [17 22] and assciated cntrl strategies especially fr high pwer applicatins. These cnfiguratins can be identified in three distinctive types: dide r neutral pint clamped (NPC) VSC [17, 18]; flying r flating capacitr clamped VSC [23, 24]; and cascaded multi-cell (cascaded H-bridge) VSC [25,26]. The first multi level cnverter cnfiguratin t appear was the cascaded H-bridge cnfiguratin frmed by cascading full-bridge cells with separate pwer surces. This was fllwed by the dide clamped multi level cnverter, which was first intrduced as a three level cnfiguratin [27], better knwn as the neutral pint clamped (NPC) cnverter, and later extended t its general high level cnfiguratin [28]. The latest additin t the multi level cnverter family is the capacitr clamped tplgy which was intrduced in early 9 s.

23 1.1 MULTI LEVEL AND SOFT SWITCHING CONCEPTS FOR HIGH POWER CONVERSION 3 All the multi level cnverters mentined abve, share the cmmn characteristics f generating better step utput wavefrms with very lw harmnic distrtin, lwer dv/dt, steady and dynamic equal vltage sharing f the series cnnected switching devices and reduced switching lsses wing t the lwer switching frequencies. In additin t these cmmn features, the dide clamped VSC in particular when functining as a back t back intercnnectr, under apprpriate cntrl can share the dc capacitr bank as the dc vltage divider fr bth sides. The disadvantage f this cnfiguratin is, nt being able t cntrl real pwer flw between ac and dc sides n its wn. This is due t the fact that, the capacitrs are charged and discharged equally (which is necessary t maintain capacitr vltage balance) nly when the pwer angle is ±9 [29]. Other disadvantage is the difficulty t add redundant switches, due t the clamping nature f the tplgy. On the ther hand, capacitr clamped VSC, has the advantage f redundancy in the switching cmbinatin fr generating an utput level, thus prviding flexible cntrl f the clamping capacitr current t keep its vltage at the required level. This feature makes the capacitr clamped cnverter equally applicable t bth active and reactive pwer cntrl withut any capacitr balancing prblems. Nevertheless, having the lad current passing thrugh the clamping capacitrs has smewhat limited its applicatin in high pwer due t the need f higher current rating clamping capacitrs. With the prvisin f three pssible utput levels frm an H-bridge cell, cascaded H- bridge VSC can achieve high level numbers by using fewer cells. But, the need f islated dc surces when it cmes t real pwer cnversin has smewhat limited the applicatin f cascaded H-bridge in high vltage applicatins. T meet the strictest harmnic standards, these multi level cnverters need t be cnstructed in high level numbers. But, with all present multi level schemes, the cnverter cmplexity increases sharply with the level number; the dide clamped tplgy needs a large number f clamping dides and the capacitr clamped tplgy needs high capacity clamping capacitrs when the level number is large in high vltage applicatins. Mrever, capacitr vltage imbalance is f majr cncern in dide clamped multi level cnfiguratin with large level numbers. These cmplexities in the tplgical structures and ther assciated difficulties in peratin have in practice limited the level numbers f these cnverters t a relative lw value. Further suppressin f harmnics is achieved thrugh PWM techniques. Thus, further research is needed in multi level cnverter cnfiguratins applying t very high vltage applicatins. In recent years, the interest f sft switching cncept t pwer electrnics has been increasing mainly due t its ability t reduce switching lsses in high frequency cnverters. There have been several lw pwer dc/ac/dc cnverters reprted using sft switching techniques tgether with PWM techniques [3 34]. The main fcus f these

24 4 CHAPTER 1 INTRODUCTION cnverters is t perate at increased switching frequency and reduce the switching pwer lsses, s as t reduce the size and weight f the cnverters. Hwever, the applicatin f sft switching cncept t ac/dc cnverters is nt simple as in dc/ac/dc cnverters due t its bidirectinal pwer flw and wide range f lad cnditins. In ther wrds, each switch f the cnverter must be prvided with zer vltage switching (ZVS) r zer current switching (ZCS) cnditins fr different lad current (frm zer t peak) and utput frequencies. In spite f these difficulties, a series f new resnant and quasi resnant sft switching tplgies [35 39] have been reprted fr ac/dc pwer cnversin, bth frm the industry and academic research. The sft switching netwrks f these tplgies adpt either passive r active sft switching, which is achieved by inductrs, capacitrs and self-cmmutated pwer switches as applied t hard switching cnverters. Zer vltage switching (ZVS) and/r zer current switching (ZCS) cnditins in these sft switching schemes are accmplished thrugh the principle f LC resnance. In ther wrds, resnance is used t frce the current in and/r vltage acrss a pwer switch t be clse t zer, at the beginning and during the switching prcess, thereby reducing the turning n di/dt and the turning ff dv/dt, the switching device is subjected t. The main cncern, when it cmes t sft switching techniques fr ac/dc cnverters is, whether the sft switching circuitry is a part f the main pwer flw path r nt, because this has a great influence n the cmpnent ratings f the sft switching circuitry. Hence, if the sft switching resnant circuit is cnnected in the main pwer transfer path, such sft switching cnverters are nt ecnmically feasible fr high pwer ac/dc cnversin. Amng the available resnant sft switching techniques, the transitin resnant ple cnverter is favured fr high pwer ac/dc cnversin, ver the ther tw types, lad resnant and resnant dc link cnverters, mainly due t its sft switching cmpnents nt being assciated with the main pwer flw path. The desired features f sft switching techniques fr high pwer cnverters are: The extra cmpnents added t achieve sft switching cnditins shuld be activated nly when the switching transitins are taking place. The circulating energy in the sft switching circuitry shuld be as lw as pssible and cmpletely decupled frm the main pwer transfer t the lad. The parasitic capacitance f the devices and the stray inductance f the sft switching circuitry shuld be part f the resnant scheme. The changes t the vltage and current wavefrms f the main switch devices, which are caused by circulatin f energy during the sft switching prcess, need t be insignificant, s that the riginal ratings f the main switch devices are unchanged.

25 1.2 HARMONIC ELIMINATION BY REINJECTION CONVERSION 5 The latest develpment in sft switching techniques is its applicatin t multi level ac/dc cnversin. Several vltage surce multi level cnverter tplgies accmpanied by sft switching netwrks have been prpsed [4 46] using the transitin resnant sft switching principle. These multi level sft switching cnverters, despite being able t achieve lw switching pwer lsses and lw harmnic distrtin, becme rather cmplicated even fr a relatively lw level number. An alternative methd fr achieving sft switching, in multi level high pwer vltage surce cnverters is prpsed in [47 49]. Here, the sft switching is nt based n the pwer device switching transitin taking place under resnant cnditin. Instead, the zer vltage cnditins are achieved thrugh frced clamping f the pwer switches. Furthermre, the ZVS cnditins prpsed, are f cntrllable duratin and als synchrnized with the firing cntrl f the main switches. This ensures, the zer vltage cnditins t be established befre the switching transitin takes place and terminated after the switching dynamic prcess finishes. Having this type f ZVS, enabled the main bridge valves f the prpsed VSC t be frmed by direct series cnnectin f pwer switches and cntrlled synchrnusly withut dynamic vltage sharing prblems. One f the main advantages f this scheme is that the cmpnents added t prvide the ZVS cnditin are nt part f the main pwer transferring paths, which permits their current ratings t be lw. The snubber circuits can be very simple and inexpensive, due t the fact that the energy stred in them including the parasitic capacitrs is recvered withut lsses. Similar type f principle fr achieving zer current switching (ZCS) in self-cmmutated current surce cnversin is prpsed in [5] and als discussed in this thesis. In this scheme, the main switch devices are prvided with the zer current cnditins, by frced blcking, realized thrugh the switching actins f the added pwer switching devices which are f lw vltage ratings. In that respect, this scheme is cmpletely different frm the present sft switching techniques. Mrever, the prpsed ZCS, returns the energy stred in the inductive cmpnents gradually back int the system, thus making the interface between the cnverter and the ac pwer system much mre simple. 1.2 HARMONIC ELIMINATION BY REINJECTION CONVERSION The use f harmnic injectin in pwer cnverters has a histry f mre than half a century. But its applicatin as a methd f harmnic reductin in pwer cnverters was first prpsed by B. M. Bird et al. [51] in In this paper, a third harmnic is used t mdify the rectifier current wavefrm in rder t reduce the ac side current harmnic cntent. The harmnic reductin by triple harmnic injectin was further generalized by A. Ametani [52] in He extended the technique t a variety f six pulse current surce type rectifier cnfiguratins. He als demnstrated the effects caused by ther

26 6 CHAPTER 1 INTRODUCTION harmnic (5, 7, 9) injectins; and cncluded that fr general purpse reinjectin, the third harmnic is the mst suitable while the ninth harmnic is the mst apprpriate fr the reductin f harmnics higher than the ninth. The practical applicatin f the harmnic injectin cncept suffered frm the fllwing prblems. The need f a triple harmnic current surce and its synchrnizatin t the supply main frequency. The difficulty f adjusting the amplitude and phase f the injected harmnic current t suit each particular perating cnditin. The inability t mdify mre than ne harmnic rder at any perating cnditin. The pr efficiency due t the ineffective dissipatin f harmnic pwer injected. Practical implementatin f the cncept turned ut t be difficult due t the requirements in frequency, amplitude and phase cntrllability f the harmnic surce. These difficulties has prevented the harmnic injectin cncept being further develped till 198 s. Nearly a decade f n further develpments in the cncept was brken in 198 by J. F. Baird and J. Arrillaga [53], with the develpment f the cncept t a practically applicable stage. In their scheme, the required harmnic current injectin is apprximated by a step wavefrm which is generated with the help f an auxiliary circuit cnsisting f pwer switches, feedback transfrmers and dc blcking capacitrs. This auxiliary reinjectin circuit injects a vltage cmpnent n the dc side and a current cmpnent n the ac side f the cnverter bridge thereby effectively causing the pulse number t be dubled. This new cncept termed as the dc ripple reinjectin, surmunts mst f the difficulties mentined abve. The majr prblem f building a fully cntrllable current surce supply is eliminated here. A fixed prtin f the dc current is used t frm the reinjectin current which permits the amplitude f the reinjectin current t be adjusted autmatically t suit any perating cnditin. Mrever, the dc ripple cntrlled natural cmmutatin f the auxiliary pwer switches enable synchrnizatin f the reinjectin current with the main pwer supply frequency and phase. The riginal dc ripple reinjectin cncept was further generalized by J. Arrillaga and M. Villablanca in early 9 s t achieve pulse multiplicatin using several reinjectin transfrmers r multi tapped transfrmer secndaries and a crrespndingly increased number f reinjectin pwer switches. Fixed reinjectin transfrmer turns ratis ensure the amplitude f the multi level reinjectin current matches the particular perating cnditin and thus the ptimum harmnic reductin is accmplished fr all perating

27 1.3 THESIS OBJECTIVE 7 cnditins. Several high pulse line cmmutated cnverter cnfiguratins have been prpsed [54 59], demnstrating the effectiveness f pulse multiplicatin technique. K. Oguchi has taken an alternative apprach [6,61] t reduce the harmnic distrtin applicable bth t vltage and current surce cnverters. His methd invlved sme extra switches and harmnic cancellatin reactrs thereby prducing high step vltage and current wavefrms at the utput terminals. Several cnfiguratins [62 65] fr different multi step numbers (18, 36, 6, 48/72) have been prpsed. Very recently, Y. H. Liu revisited the reinjectin cncept and went further t apply it t vltage surce cnversin. He prpsed the nvel cncept f dc vltage reinjectin [66,67] and fund that a reinjectin vltage f six times the fundamental frequency is necessary fr harmnic cancellatin in 12-pulse vltage surce cnverter. In these references, a very systematic apprach is emplyed t find the amplitude f the reinjectin vltage wavefrm fr minimum Ttal Harmnic Distrtin. He generalized this idea by using a rigrus mathematical analysis and fund the ideal reinjectin wavefrm fr cmplete harmnic eliminatin in ac utput vltage wavefrm f a standard 12-pulse VSC [68]. The practical implementatin f this idea has resulted in the new cncept, multi level vltage reinjectin [47 49]. 1.3 THESIS OBJECTIVE The majr riginal idea presented in this thesis is the hybrid MLCR-CSC scheme which effectively adds self-cmmutating capability int the cnventinal thyristr cnverter. Fr this purpse, the zer current duratins prpsed fr the MLCR-CSC are designed in such a way that they are sufficient enugh t permit the ff-ging thyristr t reestablish its vltage blcking ability. This is equally applicable fr inductive as well as capacitive peratin. The idea was t impart the main bridge thyristrs, the ability t cmmutate withut the assistance f a turn-ff pulse r the line-cmmutating vltage. The final utcme f this exercise is the advanced MLCR-CSC scheme, cnsisting thyristr main bridges and self-cmmutated reinjectin circuitry. In rder t explit the advantages ffered by this nvel cnverter scheme, this thesis further discusses its applicatin in HVDC transmissin. A nvel cntrl strategy which wrks under the fundamental switching restrictin f the main bridges is presented t cntrl these cnverters in tw terminal HVDC schemes. The prpsed cntrl system is based n ne end f the link cntrlling real pwer and the ther end cntrlling the reactive pwer. These HVDC schemes with the prpsed cntrl strategy have been shwn t prvide fast dynamic respnse. Additinally, they have shwn n signs f cmmutatin failure in the main bridge thyristrs fr the perating cnditins that they have been tested fr.

28 8 CHAPTER 1 INTRODUCTION The prpsed HVDC schemes d nt permit cmpletely independent cntrl f the reactive pwer at bth ends f the link as in present PWM cntrlled VSC based HVDC schemes. The independent reactive pwer cntrl f these HVDC schemes is nt discussed in this thesis and will be a subject fr further research. 1.4 THESIS OUTLINE This thesis cntains 7 chapters. Chapter 1 briefly reviews the present state f the art technlgy f self-cmmutated devices and their applicatins in high pwer and high vltage systems, alng with a discussin n multi level and sft switching cncepts. This is fllwed by a review f past research carried ut n reinjectin cncept and latest cntributins n multi level vltage reinjectin cnversin. Chapter 2 discusses the fundamentals f the reinjectin cncept, with respect t 12- pulse current and vltage surce cnversin, which includes the derivatin f the ideal reinjectin and tw apprximatins, ESEDS and linear reinjectin wavefrms. The synthesis f reinjectin wavefrms fr practical implementatin is als briefly discussed. Chapter 3 presents the multi level vltage reinjectin VSC, based n reinjectin transfrmers and auxiliary reinjectin bridges. Tw cnfiguratins derived frm parallel and series bridge arrangements are analyzed fllwed by verificatin by means f PSCAD/EMTDC simulatin. Chapter 4 intrduces the multi level current reinjectin cncept. The parallel and series cnnected cnfiguratins based n 12-pulse bridges are presented and thrughly analyzed. Step apprximatins fr linear and ESEDS wavefrms are adpted as reinjectin wavefrms, respectively fr the parallel and series cnfiguratins. Each cnfiguratin is verified fr its steady state vltage and current wavefrms, using PSCAD/EMTDC simulatin. Chapter 5 is a brief ne and describes the multi level current reinjectin CSC cnfiguratin with thyristr based main bridges and self-cmmutated reinjectin circuitry. The ability f the main bridge thyristrs t cmmutate withut the assistance f the line vltage is explained and then verified thrugh PSCAD/EMTDC simulatin studies, by selecting a negative firing angle. Chapter 6 discusses the applicatin f the MLCR-CSC t HVDC transmissin systems. The peratin f a back t back (BTB) link and a lng distance HVDC transmissin link are described, fllwed by verificatin by PSCAD/EMTDC dynamic simulatin. Chapter 7 summarizes the general cnclusins reached in this research and gives suggestins fr pssible future wrk.

29 Chapter 2 FUNDAMENTALS OF THE REINJECTION CONCEPT 2.1 INTRODUCTION The cnfiguratins that have been develped fr the purpse f cnverting electrical pwer frm ac t dc r frm dc t ac can be categrized int Vltage Surce Cnverters (VSC) and Current Surce Cnverters (CSC) based n their dc side characteristics. Fr VSC peratin, the dc side vltage is unidirectinal and maintained nearly cnstant, whereas fr CSC peratin, the dc side current is unidirectinal and maintained nearly cnstant. In these cnverters, a pwer reversal frm dc t ac r frm ac t dc can nly be achieved by changing the directin f dc current in case f VSC and by changing the directin f dc vltage in case f CSC. These characteristics necessarily frce the VSC t be built with switches f bidirectinal current passing and unidirectinal vltage blcking capability such as the IGBT, while the CSC requires switches f unidirectinal current passing and bidirectinal vltage blcking capability such as the GTO and IGCT. Depending n the current and the vltage requirements f the specific high pwer applicatin, parallel r series cmbinatins f the three phase bridges are cmmnly used. In these cnfiguratins, the switching actin cnverts the cnstant dc vltage r dc current int ac vltage r ac current wavefrms which are heavily distrted with lwer rder harmnics. Unlike in the cnventinal VSC and CSC peratin, the reinjectin cncept makes the vltage applied acrss a VSC bridge r the current supplied t a CSC bridge t vary peridically, instead being cnstant; yet by keeping the cnverter system dc vltage r current cnstant. These peridically varying wavefrms can shape the ac vltage r current f the cnverter system int specified wavefrms. An apprpriate selectin f these peridically varying wavefrms when applied t the 12-pulse cnfiguratin, the mstly used cnfiguratin in high pwer applicatins, is shwn t prduce perfectly sinusidal wavefrms at the cnverter system utput terminals.

30 1 CHAPTER 2 FUNDAMENTALS OF THE REINJECTION CONCEPT The ideal reinjectin wavefrms required t prduce pure sinusidal wavefrms in 12- pulse cnverter cnfiguratin is first derived. It is then apprximated by ESEDS (Errr Square and Errr Derivative Square) and linear reinjectin wavefrms simplifying the requirement f a special dc surce. 2.2 CONDITIONS FOR COMPLETE HARMONIC ELIMINATION In the fllwing analysis, the cnditins fr cmplete eliminatin f harmnics in fundamental switched 12-pulse CSC and VSC are investigated. T facilitate understanding, the switches and interface transfrmers f the cnverter systems are assumed t be ideal thrughut the analysis Harmnic eliminatin in 12-pulse CSC Figure 2.1 shws a 12-pulse current surce cnverter, supplied with time varying dc current surces, I BY (ωt) and I B (ωt). The interface transfrmer turns ratis are arranged as k n : 1 (primary t secndary) fr the Y cnnectin and k n : 3 fr the cnnectin as fr a standard 12-pulse cnverter. Each switch in the tw 6-pulse bridges is turned n fr a duratin f ne third f the fundamental perid (12 ) as shwn in Figure 2.2. Therefre, the time dmain cmpnents f the phase A current, I ay f the Y -cnnected secndary and the crrespnding winding current I ca f the -cnnected secndary f the interface transfrmer are < ωt < π/6 I BY (ωt) π/6 < ωt < 5π/5 I ay (ωt) = 5π/6 < ωt < 7π/6 (2.1) I BY (ωt) 7π/6 < ωt < 11π/6 11π/6 < ωt < 2π I B (ωt)/3 < ωt < π/3 I ca (ωt) = 2I B (ωt)/3 π/3 < ωt < 2π/3 I B (ωt)/3 2π/3 < ωt < π I B (ωt)/3 π < ωt < 4π/3 (2.2) 2I B (ωt)/3 4π/3 < ωt < 5π/3 I B (ωt)/3 5π/3 < ωt < 2π The cnverter system phase A current, I A (ωt) is I A (ωt) = 1 k n [I ay (ωt) + 3I ca (ωt)] (2.3) Let us first assume that the cnverter system prduces pure sinusidal wavefrms as shwn in Figure 2.3(a). The slid prtins f these wavefrms are directly cntributed

31 2.2 CONDITIONS FOR COMPLETE HARMONIC ELIMINATION 11 S Y 1 S Y 3 S Y 5 I A I B I C I ay I BY (ωt) S Y 4 S Y 6 S Y 2 S 1 S 3 S 5 I a I B (ωt) S 4 S 6 S 2 Figure 2.1 The 12-pulse CSC cnfiguratin frm the crrespnding currents f the -cnnected bridge. Therefre the reinjectin wavefrm, I B (ωt) must take the shape f a rectified versin f the wavefrm given by the slid lines. This wavefrm shwn in Figure 2.3(b), when nrmalized t its average value is I B (ωt) = π 3(2 3) sin(ωt) < ωt < π 6 (2.4) Frm the relatinship in (2.3), I ay (ωt) is fund t be as shwn in Figure 2.3(d). The reinjectin wavefrm I BY (ωt), shwn in Figure 2.3(e), fr the the Y -cnnected bridge is fund frm the current wavefrms I ay (ωt), I by (ωt), I cy (ωt) Harmnic eliminatin in 12-pulse VSC Figure 2.4 shws a 12-pulse vltage surce cnverter, supplied with time varying dc vltage surces, V Y Y (ωt) and V Y (ωt). The interface transfrmer turns ratis are arranged as k n : 1 (primary t secndary) fr the Y/Y cnnected transfrmer and

32 S Y 3 12 CHAPTER 2 FUNDAMENTALS OF THE REINJECTION CONCEPT 6 S 2 S 1 S S 3 S 1 S 5 3 S Y 5 SY 6 33 SY 4 S Y 1 S Y 6 S Y 5 SY 3 S Y 2 SY 1 SY 4 15 SY 2 21 S 2 18 S 4 S 6 27 S S 4 S 5 Figure 2.2 Firing sequence f 12-pulse CSC k n : 3 fr the Y/ cnnected transfrmer as fr a standard 12-pulse cnverter. Each switch in the tw 6-pulse bridges is turned n fr a duratin f half f the fundamental perid (18 ) as shwn in Figure 2.5. Therefre, the phase A vltages, V Y a (ωt) and V a (ωt) n the secndary windings (bridge side) f the Y/Y cnnected and Y/ cnnected interface transfrmers have the fllwing time dmain cmpnents V Y a (ωt) = V a (ωt) = V Y Y (ωt)/3 < ωt < π/3 2V Y Y (ωt)/3 π/3 < ωt < 2π/3 V Y Y (ωt)/3 2π/3 < ωt < π V Y Y (ωt)/3 π < ωt < 4π/3 (2.5) 2V Y Y (ωt)/3 4π/3 < ωt < 5π/3 V Y Y (ωt)/3 5π/3 < ωt < 2π < ωt < π/6 V Y (ωt) π/6 < ωt < 5π/6 5π/6 < ωt < 7π/6 (2.6) V Y (ωt) 7π/6 < ωt < 11π/6 11π/6 < ωt < 2π

33 2.2 CONDITIONS FOR COMPLETE HARMONIC ELIMINATION 13 1 I A I B I C (a). I A I B I C (b). I B (c). I ca (d). I ay (e). I BY Figure 2.3 Ideal reinjectin wavefrms fr 12-pulse CSC

34 14 CHAPTER 2 FUNDAMENTALS OF THE REINJECTION CONCEPT I A I B I C S 1 S 3 S 5 V Y (ωt) S 4 S 6 S 2 V A S Y 1 S Y 3 S Y 5 V Y Y (ωt) S Y 4 S Y 6 S Y 2 V Y A Figure 2.4 The 12-pulse VSC cnfiguratin The cnverter system phase A vltage, V A (ωt) is V A (ωt) = k n [V Y a (ωt) V a (ωt)] (2.7) Fllwing the same prcedure as in the previus sectin, the ideal reinjectin wavefrms V Y Y (ωt) and V Y (ωt) fr cmplete harmnic eliminatin in the cnverter system utput vltage, are shwn in Figures 2.6(a) and (b).

35 S Y REINJECTION WAVEFORMS 15 6 S 2 S 1 S 6 S 5 S Y 6 S Y 5 S Y 2 S Y 1 12 S 3 S 6 S Y 1 9 SY 6 S 2 S 1 S 4 S Y 4 SY 5 SY SY 2 S 1 18 S 4 S 5 SY 3 SY 4 SY 1 S 3 S 6 SY 4 SY 3 S Y 5 S Y 2 S 2 S 3 S S 5 Figure 2.5 Firing sequence f 12-pulse VSC 2.3 REINJECTION WAVEFORMS Ideal reinjectin wavefrm The ideal reinjectin wavefrms, shwn in Figures 2.7(a) and (b), are quasi-triangular and symmetrical arund vertical axis but nt symmetrical arund their average value. Figure 2.7(c) shws that these tw wavefrms cmbine int a dc current with ripple. Thus fr cmplete harmnic eliminatin, the tw bridges must be supplied with a dc current surce f cntrllable ripple, which is nt a practical prpsitin Symmetrical reinjectin wavefrms Due t the practical difficulty f prviding a dc surce f cntrllable ripple as required by the asymmetry f the ideal reinjectin wavefrm arund its average value, the fllwing tw types f wavefrms are derived. 1. A wavefrm that minimizes the integratin f the errr square and the errr derivative square (ESEDS); this is the ptimum apprximatin fr the ideal reinjectin wavefrm under the symmetry restrictin. 2. A linearly rising and linearly falling wavefrm, which prvides linear vltage r current increment and decrement; this is a simpler alternative fr practical

36 16 CHAPTER 2 FUNDAMENTALS OF THE REINJECTION CONCEPT 2 Vltage Wavefrms f 12 pulse VSC with Ideal Reinjectin (a). V YY /V dc (b). V Y /V dc (c). V Ya /V dc (d). V a /V dc (e). V A /k n V dc (f). V An /V A1.5 Output Vltage Spectrum f the Reinjectin VSC THD V =% Harmnic Order Figure 2.6 Vltage wavefrms f 12-pulse VSC with ideal reinjectin

37 2.3 REINJECTION WAVEFORMS (a) I B (ωt) The Ideal Reinjectin Wavefrm fr Bridge (b) I BY (ωt) The Ideal Reinjectin Wavefrm fr Y Bridge (c) I BY (ωt)+i B (ωt) The Required DC surce fr Ideal Reinjectin Figure 2.7 The ideal reinjectin wavefrms

38 18 CHAPTER 2 FUNDAMENTALS OF THE REINJECTION CONCEPT implementatin. The ESEDS symmetrical reinjectin wavefrm, I B s (ωt), derived by the minimizatin prcess { [ π/6 ( ) ] min [I B (ωt) I B s (ωt)] 2 d[ib (ωt) I B s (ωt)] 2 + d(ωt) d(ωt) [ π/6 ( ) ] } (2.8) + [I BY (ωt) I BY s (ωt)] 2 d[iby (ωt) I BY s (ωt)] 2 + d(ωt) d(ωt) under the fllwing cnstrains f symmetry and equal area criterin between the tw grups f wavefrms, I B s (ωt) + I BY s (ωt) = 2 < ωt < π 6 π/12 I B (ωt) = π/12 I B s (ωt) π/6 π/12 I B (ωt) = π/6 π/12 I B s (ωt) is π/12 I BY (ωt) = I B s (ωt) = 1 + π/12 I BY s (ωt) 2( )π 12 ( sin ωt π ) 12 π/6 π/12 I BY (ωt) = < ωt < π 6 π/6 π/12 I BY s (ωt) (2.9) Figures 2.8 and 2.9 shw the current wavefrms f the 12-pulse CSC f Figure 2.1, when supplied respectively with ESEDS symmetrical and linear reinjectin wavefrms. 2.4 SYNTHESIS OF REINJECTION WAVEFORMS As it is still impractical t generate the ESEDS and linear reinjectin wavefrms, these are further apprximated by multi level reinjectin wavefrms. An equal area criterin is adpted t find the height f a particular level f the multi level wavefrm. Multi level apprximatin f the linear reinjectin wavefrm is purpsely assigned a zer height level t prvide a zer vltage r current switching cnditin. The multi level reinjectin wavefrms, t be applied t the tw main bridges can be frmed in tw different ways. 1. Divisin f the dc vltage r current int tw prtins using a peridically cntrlled multi tap divider. 2. Frward and reverse additin f a multi level ac vltage r current wavefrm t the cnstant dc vltage r current.

39 2.4 SYNTHESIS OF REINJECTION WAVEFORMS 19 2 Current Wavefrms f 12 pulse CSC with ESEDS Reinjectin (a). I B /I dc (b). I BY /I dc (c). I ca /I dc (d). I ay /I dc (e). k n I A /I dc (f). I An /I A1.1 Output Current Spectrum f the Reinjectin CSC THD I =1.168% Harmnic Order Figure 2.8 Current wavefrms f 12-pulse CSC with ESEDS reinjectin

40 2 CHAPTER 2 FUNDAMENTALS OF THE REINJECTION CONCEPT 2 Current Wavefrms f 12 pulse CSC with Linear Reinjectin (a). I B /I dc (b). I BY /I dc (c). I ca /I dc (d). I ay /I dc (e). k n I A /I dc (f). I An /I A1.1 Output Current Spectrum f the Reinjectin CSC THD I =1.553% Harmnic Order Figure 2.9 Current wavefrms f 12-pulse CSC with linear reinjectin

41 2.5 CONCLUSIONS 21 Cnverter cnfiguratins that use the first methd, emply the linear reinjectin methd, which permits using same rating switches and equal turn windings. The secnd methd requires the multi level ac vltage r current wavefrm amplitude t be related t the dc vltage r current f the cnverter system. Therefre the dc vltage r current is used t pwer the reinjectin circuitry and thus generate these wavefrms. Islatin f these ac wavefrms frm the dc surce is btained by using a reinjectin transfrmer. Cnverter cnfiguratins that adpt this methd, use the ESEDS methd, which prvides better harmnic suppressin withut the zer vltage r current switching cnditins. 2.5 CONCLUSIONS 1. The ideal reinjectin wavefrms are quasi-triangular wavefrms f six times the fundamental frequency and require a dc surce with cntrllable ripple. 2. The zer values f the ideal reinjectin wavefrms, cincide with the instances where the switches in the bridges are turned n and ff, which indicates the pssibility f achieving zer current switching (ZCS) r zer vltage switching (ZVS). 3. Bth the ESEDS and linear symmetrical reinjectin methds can prduce ac utput wavefrms with very small amunt f 12-pulse related harmnics (all belw 1%) and abut 1% ttal harmnic distrtin. 4. The ideal reinjectin wavefrm and the tw apprximatins (ESEDS and linear) share the cmmn characteristic f limited derivatives, which ensure the peratin at lw di/dt r dv/dt cnditins.

42

43 Chapter 3 MULTI LEVEL VOLTAGE REINJECTION VSC 3.1 INTRODUCTION Over the last tw decades, there has been a great develpment in the area f selfcmmutated vltage surce cnversin (VSC) fr FACTS and HVDC applicatins. Mst f FACTS cntrllers in peratin are based n vltage surce cnverters. The symmetrical multi level vltage reinjectin wavefrms supplied t the tw main bridges as described in Sectin 2.4, can be decmpsed int their dc and ac cmpnents, which will result in dc cmpnents with the same magnitude and ac cmpnents with the same amplitude but ppsite plarity. This enables these reinjectin wavefrms t be frmed by additin f an ac vltage, frwardly r reversely t a dc vltage. The amplitude f the symmetrical reinjectin wavefrm must be related t its dc cmpnent, and its frequency and phase must be synchrnized with the ac utput vltage f the main bridges. An additinal self-cmmutated circuit, pwered by the dc surce is adpted here, t generate the ac cmpnent f the reinjectin vltage wavefrms. Fr practical implementatin, this ac vltage cmpnent needs t be islated frm the dc side when is being added t the dc surce t frm the reinjectin vltage wavefrms fr the tw main bridges. An islatin transfrmer is incrprated t serve this purpse. Fr high pwer applicatins, 12-pulse based VSC is favured ver 6-pulse based VSC. Thus, tw types f cnfiguratins based n parallel and series duble bridge vltage surce cnverter cnfiguratin are described. The parallel scheme (shwn in Figure 3.1), uses a three limb reinjectin bridge cnnected acrss the dc capacitr; its utput vltage, cupled thrugh a fur winding single phase transfrmer, is added t the dc capacitr vltage t frm the reinjectin vltage wavefrms fr the tw main bridges. This scheme, thugh benefitting frm a reductin in the dc capacitance, suffers frm the reinjectin transfrmer secndary windings being cnnected in the main pwer flw path. The series scheme (shwn in Figure 3.11), uses tw single phase reinjectin bridges, each cnnected acrss ne half f the dc capacitr. The three level vltage utputs frm the tw reinjectin bridges are apprpriately phase shifted with respect t each ther t