Simulation of Push-pull Multi-output Quasi-resonant Converter

Transcription

1 IOSR Jurnal f Electrical and Electrnics Engineering (IOSR-JEEE) e-issn: ,p-ISSN: , Vlue 9, Issue 1 Ver. V (Feb. 14), PP 19-4 Siulatin f Push-pull Multi-utput Quasi-resnant Cnverter T.Anitha 1, S.Arulselvi 1 (Assistant Prfessr, Departent f Electrnics and Instruentatin Engg., Annaalai University,India) (Prfessr, Departent, f Electrnics and Instruentatin Engg., Annaalai University,India) Abstract : Pwer supply vltages in digital systes have been reduced cnsiderably in recent years and ften digital cpnents requiring different vltages are present in the sae bard. This has increased the deand fr ultiple utput pwer distributin systes with tight lad regulatin. In this paper, a detailed analysis and design f a ulti-utput push-pull zer vltage switching (ZVS) quasi resnant cnverter (QRC) has been carried ut. Als siulatin f ulti-utput push-pull zer vltage switching (ZVS) quasi resnant cnverter (QRC) has been carried ut using Matlab/SIMULINK sftware. The prpsed cnverter is suitable fr aerspace applicatins. Keywrds: - cnverters, push-pull cnverter, quasi-resnant cnverters, Zer vltage switching. I. INTRODUCTION Multi-utput PWM - cnverters are widely used in cunicatins, aerspace and cputer systes, as they are usually re cpact and less expensive than a cllectin f single-utput cnverters. Fig.1 shws the scheatic f single pwer cnverter with ultiple utputs, e.g. push-pull cnverter with ultiple secndary windings. In aerspace applicatins the allwable size and weight are highly restricted t accdate greater paylad. In the effrt t increase the pwer density f pwer supplies, the switching frequency is pushed t high values which, in PWM cnverter realizatins, nrally lead t cnsiderable pwer lss, high switching stresses, reduced reliability, and acustic nise. Anther significant drawback f the switch-de peratin is the EMI prduced due t large di/dt and dv/dt. T verce these shrt cings, new failies f QRCs are intrduced [1]-[].Few research papers have been presented abut the design and ipleentatin f push-pull hard switched and Quasi-resnant cnverters[3]-[5].push-pull cnverters is ainly used fr ediu and high pwer applicatins cpared t half-bridge and full-bridge cnverter. It has wide duty rati cntrl and it can be used fr ulti-utput applicatins with lw utput and input ripple current. This paper presents the design f ulti-utput push-pull ZVS-QRC. The prpsed ethd reduces the switching lsses and size f the cnverter. It can be used as high-density pwer supply fr aer-space applicatins. All siulatin wrks are carried ut using MATLAB/SIMULINK sftware. Figure 1 Multiple utputs using single pwer cnverter. II. ANALYSIS OF MULTI-OUTPUT PUSH-PULL ZVS QRC The prpsed push-pull tplgy is basically tw frward cnverters cnnected in anti-phase. An additinal tw resnant tanks are added in this tplgy cpared t PWM push-pull cnverter. The resnant 19 Page

2 Siulatin f Push-pull Multi-utput Quasi-resnant Cnverter tank shapes the switch vltage s that the active switches (S 1 and S ) are turned n at ZVS. Hence the turn-n lsses f the switch will be reduced cnsiderably cpared t PWM cnverters. Bth priary and secndary windings are arranged in a center-tapped cnfiguratin. The push-pull cnverter perates in tw quadrants (I and III) f the B-H curve, see-sawing back and frth as the each priary is activated. This allws the push-pull cnverter t deliver twice the axiu pwer than that f a frward cnverter. This akes the prpsed cnverter effective fr ediu and high pwer applicatins. The different des f peratin are explained in the fllwing sectin. Figure Circuit diagra f ulti-utput push-pull ZVS-QRC. Figure 3 Theretical resnant wavefrs f push-pull ZVS-QRC. T analyze its steady-state behavir, the fllwing assuptins are ade 1. The utput filter C f and the lad R R 1, are a cnstant sink f current I 1 and I respectively.. Seicnductr switches are ideal, i.e. n frward vltage drp in the n-state, leakage current in the ff state and n tie delays at bth. 3. Reactive current in the eleents are ideal. 4. Magnetizing inductance is larger than resnating inductance The fllwing paraeters are defined 1. Characteristic ipedance Z ( L r C ) r. Resnant angular frequency 3. Resnant frequency 1 ( L r * C r ) f / 4. Nralized Lad Resistance Page

3 R R L / Z 5. The priary current thrugh priary f transfrer (L ) is I I Siulatin f Push-pull Multi-utput Quasi-resnant Cnverter.1 MODES OF OPERATION The switch S 1 and S are alternatively pwer their respective windings. The resnating capacitrs C r1 and C r and resnating inductrs L r1 and are used t fr the resnant tank. The secndary vltage f the transfrer is rectified by fast recvery dides (D 1 and D ) and filtered t prduce a steady ripple free utput vltage V. Lwer and upper part f priary winding circuit is called here afterwards as upper and lwer..1.1 MODE 1: (t,t 1 ) UPPER: The switch S 1 is pened fr the beginning f a new cycle at t equal t t. The current flws thrugh resnant capacitr ( Cr1) and resnant inductr ( L r1). The capacitr vltage rises linearly fr t V. The capacitr vltage is given by the equatin, v I t / C cr1( When the resnant capacitr vltage reaches V at t = t 1.The duratin f this interval T d1 is given by d1 r T 4C V / I LOWER: The switch S pened in the previus cycle is still cntinued. The capacitr vltage v cr in the lwer part decreases linearly fr V t zer. The equatins fr v cr and i are given as v cr I ( V Z sin ωt i I cs t.1. MODE : ( t 1, UPPER: The series resnant L r1 and C r1 frs a resnant circuit. The state equatins are With initial cnditins dv di cr1 dt i 1( Cr1 1 dt ( V vcr1( ) 1 v cr1() V and i () I 1 The slutins fr the abve equatins are given by vcr1( V ) Z i 1( ) cs t r sin t At t equal t t, i 1 reaches zer value and v cr1 reaches its peak value as shwn in fig, 3a. They are given by T The duratin f the de d v cr1 V ) ( Z is given by T d t t1 LOWER: The switch S is turned n when V cr bece zer at t = t 1, t achieve zer vltage cnditin. During this stage the current i increases linearly and reaches the value I at t = t.the crrespnding state equatin fr i is given by di dt V L r The slutin f abve equatin is given by.1.3 MODE 3: t, ) ( t 3 i ) cs t UPPER: The equatins deterining this stage are di 1 dt ( V vcr1( ) 1 cr / dt i1( / Cr dv and 1 1 Page

4 With initial cnditins v i cr1() V () I 1 The slutin fr the equatins are given by i 1( ( I ( V Siulatin f Push-pull Multi-utput Quasi-resnant Cnverter / )cs t vcr 1 1( t T d 3 t4 t3 1 Td 3 ( 1 )sin [ V ( I Z d 3 ( ) / )sin t This stage terinates when V cr ) beces zer. The duratin f this stage is given by Where T ) ] The inductr current is given by LOWER: v cr is zer and With initial cnditins i 1 di 1 (sin [4V I Z]) )cs dt )) i () I The slutin fr abve equatin is.1.4 MODE 4: ) ( V vcr ( t i t ( t 3, t 4 ( )cs( ) UPPER: The switch S 1 is turned n when v cr1 bece zer t achieve zer vltage cnditin. During this de the current i 1 increases linearly and reaches the value I at t equal t t 4. The crrespnding state equatin is With initial cnditin The inductr current 1 di 1 dt V / 1 i () 1 )cs i ( is given by the equatin i1( ((V * ) (( I )cs ) This de terinates when inductr current bece I. The duratin f this stage is given by the equatin T d 4 t4 t3 T d 4 [ IZ 4V ](1 cs ) LOWER: The switch S is pened at t = t 4. The current flws thrugh resnant capacitr ( Cr ) and resnant inductr L r.the capacitr vltage rise s linearly fr zer t and it is gverned by equatin v cr ( ( I Cr1 At the end f this de, a new de cycle starts.. Theretical resnant wavefrs The theretical resnant wavefrs f the prpsed cnverter fr ne switching cycle are shwn in fig.3. Whenever there is a change in switching device fr ne state t anther, the circuit cnfiguratin changes. Each cnfiguratin is referred t as de. In this QRC, fur different stages are identified fr each half f the switching cycle..3 Design The design paraeters are given fr a ulti-utput push-pull ZVS-QRC with fllwing specificatins: V Page

5 Input vltage V 4V Output vltage f secndary1 V 1 5V Output Vltage f secndary V 1V Siulatin f Push-pull Multi-utput Quasi-resnant Cnverter Resnant frequency f 165kHz Switching frequency f s 5kHz Turns rati between priary and secndary n 1= N p1 N s n N p N.3 s The characteristic ipedance Z sqrt( L r C ) r The resnant capacitrs are assued t be equal Cr Cr1 Cr. 47icrF The resnant inductrs are assued t be equal 1. 16H III. OPEN LOOP STUDIES In this sectin the pen lp siulatin f ulti-utput push-pull ZVS-QRC circuit is realized with paraeters btained fr the design. The siulated resnant capacitr vltage and utput vltage f the cnverter are discussed in this sectin. The perfrance f the cnverter is studied fr different lad variatins. The cnverter is siulated using Matlab/SIMULINK sftware in pen lp with design paraeters. The SIMULNK del f the circuit is shwn in figure 4. The gating pulses applied t switch S 1 and S are shwn in fig. 5. It is bserved that the switch S 1 and S are turned n, when the resnant capacitr vltage beces zer t assure ZVS cnditin. The wavefr resebles the theretical wavefrs as shwn in fig 3. Figure 4 Siulink Mdel Diagra fr the Multi Output Push-Pull ZVS-QRC Figure 5 Siulated resnant wavefrs fr upper part and lwer part f priary. 3 Page

6 Siulatin f Push-pull Multi-utput Quasi-resnant Cnverter Figure 6 Siulated pen lp utput wavefrs f the secndary1 V 1 and secndary V (vlts). IV. CONCLUSION Theretical analysis and design prcedure f a new buck type push-pull ZVS-QRC was presented. The cnverter rated at 1W, perating at switching frequency f 5kHZ has been siulated using Matlab/SIMULINK sftware. Operating principle and theretical analysis are cnfired by siulatin results. The cnverter can als be ipleented in hardware which will give atching results as that f siulated results. Hence this is suitable fr high-density, ediu pwer requireent, fr exaple in aerspace applicatins. REFERENCES [1] Liu K.H. and LEE F.C.Y., Zer-vltage Switching Technique in DC-Dc Cnverters, IEEE Specialists Cnference Recrd, 1986,pp [] I.Barbi, J.C.Blacell,D.C.Martins and F.B.Liban, Buck Quasi-Resnant Cnverter perating at Cnstant Frequency:Analysis, Design and Experiantatin,IEEE,pp [3] Wildn C.P., de Araga Filh,I.Barbi, A Cparisn Between Tw Current-Fed Push-Pull DC-DC Cnverters-Analysis,Design and Experientatin, IEEE, 1996, pp [4] Grver V., T.Bascpe and I.Barbi, Islated Flyback-Current-Fed Push-Pull Cnverter Fr Pwer Factr Crrectin,IEEE,1996,pp [5] B.Swainathan and V.Raanarayanan, A Nvel Resnant Transitin Push-Pull DC-DC Cnverter,J.Indian Inst Sci,Nv.- Dec.4,pp Page