Modulation Technique to Reverse Power Flow for the Isolated Series Resonant DC-DC Converter with Clamped Capacitor Voltage

Transcription

1 Mdulatin Technique t Reverse Pwer Flw fr the Islated Series Resnant DC-DC Cnverter with Clamped Capacitr Vltage Yu Du, Student Member, IEEE, Srdjan M. Lukic, Member, IEEE, Bris S. Jacbsn, Senir Member, IEEE, and Alex Q. Huang, Fellw, IEEE Abstract Series resnant DC-DC cnverter with clamped capacitr vltage exhibits excellent characteristics in frward perating mde including simple cntrl, high reliability, sft switching, high pwer density and inherently limited lad fault current. Hwever, the cnventinal single angle phase-shift mdulatin that wrks well in the frward mde cannt reverse the pwer flw. In this paper, we prpse a mdulatin strategy fr reverse mde peratin by utilizing three phase-shift angles affrded by the tw active full bridges f the circuit. We identify the ptimal mdulatin trajectries in three-dimensinal mdulatin space and implement a lk-up table based mdulatr fr pwer flw cntrl. A high-fidelity simulatin mdel f a 35kW 750V input, 300V-600V utput, 50kHz IGBTbased cnverter was used fr verificatin. The prpsed mdulatin scheme and efficiency calculatins were validated n a scaled dwn (5kW) prttype. The pwer lss distributin was analyzed fr further cnverter efficiency ptimizatin. Index Terms Bidirectinal DC-DC pwer cnverters, energy strage, lk-up table, phase mdulatin, resnant cnverters. W I. INTRODUCTION ITH THE INCREASED USE f energy strage devices in a variety f applicatins, there is a grwing need f bi-directinal pwer cnversin. The applicatins f particular interest are electric vehicles []-[6], electric vehicle charging infrastructure [7], renewable pwer generatin systems [8]- [0], hybrid pwer surces []-[3]. Particularly challenging are the applicatins where the energy strage system vltage varies substantially during nrmal peratin as it des fr batteries, supercapacitrs r fuel cells [4]-[5]. In mst applicatins, high pwer cnversin efficiency is required fr Manuscript received December 5, 00; revised March 7, 0 and May 6, 0; accepted July 0, 0. This wrk was spnsred by Raythen Cmpany and made use f ERC shared facilities supprted by the Natinal Science Fundatin under Award Number EEC-08. Cpyright (c) 009 IEEE. Persnal use f this material is permitted. Hwever, permissin t use this material fr any ther purpses must be btained frm the IEEE by sending a request t pubs-permissins@ieee.rg. Y. Du, S. M. Lukic and A. Q. Huang are with the NSF FREEDM Systems Center, Department f Electrical and Cmputer Engineering, Nrth Carlina State University, Raleigh, NC 7606, USA ( ydu4@ncsu.edu; smlukic@ncsu.edu; aqhuang@ncsu.edu). B. S. Jacbsn is with Raythen Cmpany, Sudbury, MA 0776, USA ( bris_s_jacbsn@raythen.cm). Fig. : Cnventinal high pwer bi-directinal DC-DC cnverters: (a) vltage-fed and current-fed full bridges, (b) dual active full bridges. all perating cnditins. A number f transfrmer islated bi-directinal DC-DC cnverters have been cnsidered fr high pwer applicatins [6]-[8]. One f the reprted tplgies is the vltage-fedinput and current-fed-utput full-bridge cnverter, shwn in Fig. (a). In this figure V dc represents the high vltage stable DC bus, while V ds represents a wide-vltage-swing energy strage system. In the prpsed circuit, an auxiliary clamping circuitry is necessary t limit the vltage stress f cmpnents in the current-fed side due t the leakage energy f the high frequency transfrmer. Vltage clamping can be achieved using an active clamping circuit in Fig. (a) [9], RCD snubber [0] r lssless snubber []. Further investigatin indicates that the current-fed side cmpnents still suffer high vltage stress, especially with wide vltage range. The dual active bridges (DAB) DC-DC cnverter, shwn in Fig. (b), is anther widely used islated bi-directinal DC- DC cnverter []-[4]. Cnventinal mdulatin strategy uses the phase shift between the tw full bridges t cntrl the directin and amplitude f pwer flw. Hwever, the ptimal perating range is limited, making it unsuitable fr wide vltage range applicatins. Advanced mdulatin strategies imprve the DAB perfrmance [5]-[8]. The pwer stage f the transfrmer-islated, Clamped

2 TABLE I SPECIFICATIONS AND RESONANT TANK PARAMETERS OF THE CC-SRC Symbl Quantity Value V dc input vltage 750V V ds utput vltage 300V-600V P rated pwer 35kW f s switching frequency 50kHz N :N :N transfrmer turns rati :: L, L resnant inductr.6uh C r resnant capacitr 0.9uF f characteristic frequency 36kHz Z characteristic impedance 5.Ω Q m maximal lad quality factr.5 Fig. : The pwer stage f the bi-directinal phase-shift cntrlled series resnant DC-DC cnverter with clamped tank capacitr vltage (CC-SRC). Capacitr vltage, bi-directinal Series Resnant dc-dc Cnverter (CC-SRC) is shwn in Fig.. It is a fixedfrequency phase-shift-cntrlled series resnant cnverter. Its frward mde characteristics are well described by applying the numeric simulatin methd [9]-[33]. In frward mde, fur clamping dides D9-D ensure the cntrl f internal vltage and current under varius cnditins f line and lad. The clamping circuit prvides intrinsic current limiting capability at lad shrt-circuit. The maximum vltage stress f resnant capacitr is limited t the input vltage and there is n risk f damaging the capacitr at verlad r shrt-circuit cnditins. Therefre, the cnverter reliability is greatly enhanced even when the feedback signal is lst. High efficiency and ZVS are achieved in the wide vltage and lad range [9]. At light lad, ZVS can be maintained with auxiliary switches and inductrs [3]. There is little circulating current at light lad and the CC-SRC is ideally suited fr wide vltage pwer cnversin. Despite the excellent frward mde characteristic f the CC-SRC, reverse mde peratin is quite challenging. The simple phase-shift mdulatin f the secndary side fullbridge switches S5-S8 cannt reverse the pwer flw frm the secndary side t the primary side because series resnant cnverter essentially steps dwn the vltage [34]. T reverse the pwer flw, an advanced mdulatin strategy based n cntrlling all three phase-shift angles is necessary. In this paper the ptimal trajectry in the three-dimensinal mdulatin space with three phase-shift angles is prpsed t reverse the pwer flw f the CC-SRC when wide utput vltage range is required. A scheme fr reversing the pwer flw f the CC-SRC was first prpsed and experimentally validated in [34] based n the design f experiment apprach since the analytical slutin is nt feasible fr such a cmplex circuit. This paper presents an alternative mdulatin scheme that results in better efficiency at high input vltages. In additin, we prpse a clsed lp cntrl strategy based n the cntrl f a virtual phase-shift angle that is the amalgam f three actual cntrl variables. The remainder f this paper is rganized as fllws. In part II, the specificatins f the CC-SRC and the pwer stage parameters are described. In part III, the advanced mdulatin technique t reverse pwer flw with lw utput vltage is analyzed. Tw strategies fr selecting the mdulatin trajectry with high utput vltage are studied and cmpared in Part IV. In part V, the reversed pwer flw cntrl in wide utput vltage range is discussed. A lk-up table based mdulatr is used t simplify the pwer flw cntrl. The experiment wavefrms fr reverse mde peratin with wide utput vltage are reprted and cmpared with simulatin wavefrms in Part VI. In additin, the efficiency f the prpsed cnverter is calculated fr full lad range and verified at lwer pwer level by experiment n a scaled-dwn 5kW prttype. Lss breakdwn analysis is als cnducted. II. SPECIFICATIONS AND POWER STAGE PARAMETERS The pwer stage f CC-SRC is shwn in Fig.. The transfrmer primary winding is split int tw equal parts and the turns rati fr tw primary windings and ne secndary winding is N :N :N. Fur dides (D9-D) are added int the circuit t clamp the maximum resnant capacitr vltage t input vltage V dc, and t limit utput fault current. In rder t reverse pwer frm secndary t primary side, fur IGBTs (S5-S8) are emplyed as the secndary side full bridge. In frward mde, nly the primary side IGBTs S-S4 are cntrlled using phase shift. Detailed descriptin f frward mde peratin is explained in [9]-[34]. The cnverter specificatins in this study are listed in Table I, based n [34]. The resnant frequency is defined as, f LC r, () where L = L + L = L, and C r is resnant capacitance. The characteristic impedance f the resnant tank is Z L f L, () C f C The laded quality factr is defined as r Ttal energy stred Z Q, (3) Energy dissipated per cycle R r e

3 Fig. 3: Prpsed mdulatin strategy based n three phase-shift angles fr reverse mde peratin: gate signals fr 8 IGBTs. where R e is the equivalent lad resistance. T represent the utput lad resistance in terms f the equivalent resistance seen by the resnant tank, (4) is used [36]. The equivalent lad resistance is R e N 8 R L 0.8N R L, (4) where R L is utput lad resistance. Frm [36], the utput vltage with zer phase-shift angle (φ =0) is V ds Vdc I ds RL, (5) N ) Q ( f s / f f / f s where I ds is the DC utput current and calculated by rectifying the fundamental cmpnent f the resnant tank highfrequency AC current. The cnsideratins and trade ff fr selectin f transfrmer turns rati N= N /N, resnant inductance L=L +L = L and resnant capacitance C=C r is presented in [34] in detail and the parameters are listed in Table I. III. REVERSE MODE MODULATION STRATEGY WITH LOW OUTPUT VOLTAGE It is difficult and inefficient t derive the cmplicated analytical mdels fr the CC-SRC because there are fur state variables assciated with fur energy strage cmpnents in the circuit and there are nine pssible cnductin mdes f the fur clamping dides in which at least D and D cnduct alternately fr sme perid in each switching cycle [33]. But with φ =0 the intrinsic vltage step-dwn characteristic f the cnverter described by (6) is btained frm (5), M V Vds V. (6) dc N Q ( f / f f / f ) Equatin (6) represents the CC-SRC maximum vltage transfer rati crrespnding t the phase shift angle φ f zer when nne f the clamping dides cnduct. As described in detail in [34] and as can be cncluded frm (6) the series resnant DC-DC cnverter steps dwn vltage under the assumptin f : (N=) transfrmer turns rati. It is impssible t reverse the pwer flw frm V ds back t V dc by s s Fig. 4: Illustratin f the selected numeric simulatin pints in the three-dimensinal phase-shift mdulatin space. simply cntrlling S5-S8 r φ since V ds is smaller than V dc. Therefre, mre advanced mdulatin technique shuld be prpsed t realize reverse mde peratin. With full bridge in bth primary and secndary side, there are three mdulatin variables t utilize (see Fig. 3): the primary side full bridge phase-shift angle φ (used slely fr frward mde pwer flw cntrl), the secndary side full bridge phase-shift angle φ (shwn as inadequate as the sle cntrl variable when vltage bsting is required) and the phase shift angle between the secndary side and the primary side bridges φ (used as the cntrl variable fr the cnventinal DAB cnverter). It is apparent that all three degrees f freedm shuld be explred as ptential candidates fr the reverse mde cntrl. Since there is n analytical cnverter mdel derived fr the reverse mde peratin, a systematic numeric simulatin study has been cnducted. T cver the wide perating range, 36, 90 and 44 have been selected fr each phase-shift angle giving a ttal f 7 cmbinatins fr three mdulatin variables as shwn in Fig. 4. The assumptin is that there are n majr nnlinearities r discntinuities between the simulated pints and that the curve fitting apprach will prvide a gd predictin f the behavir f the cnverter fr the pints that have nt been explicitly tested. Once the cntrl path is chsen, additinal simulatins are perfrmed t verify the system behavir at the pints f interest. Simulatins are perfrmed t calculate the weighted average rms current and the reversed pwer at the pints f interest. In the simulatins, the hard switching (HS), zer vltage switching (ZVS) f IGBTs, and the specific reversed pwer are all recrded t determine the ptimal perating strategy. The specific reversed pwer is defined as the rati f reversed pwer t the weighted average rms current f cnverter. Trivariate splines implemented in Matlab are used t interplate between the simulated pints [35]. We define the cnverter weighted average rms current as I rms 3i 3i 5i i i )/5, (7) ( T T T3 D9 D

4 Fig. 5: The specific reversed pwer fr different cmbinatins f three phase-shift angles [φ, φ, φ ] (V dc =750V, V ds =300V). where i D9 and i D are the rms current f the clamping dides, i T -i T3 are the rms current f the transfrmer windings. Each gain represents the cumulative cnductin lsses thrugh the cmpnents that are in the current path. In this analysis, as a simplificatin, equal weight is given t the cnductin lss in each cnducting device. Nw the specific reversed pwer P S is defined as, P P S, (8) Irms where P is the reversed pwer and I rms is the weighted average rms current f the cnverter. The weighted average rms current defined in (7) is a measurement f the current stress f cmpnents in the circuit. At sme cmbinatins f the three phase-shift angles, the reactive pwer in the circuit is very large which causes high cmpnent current stress r damage. The specific reversed pwer defined in (8) is an indicatin f the reactive pwer and current stress in the circuit. High specific reversed pwer indicates lwer current stress and, ptentially, mre efficient pwer cnversin. Fig. 5 shws the specific reversed pwer when secndary side vltage V ds is 300V, the lwest utput vltage. The cmbinatin f three phase-shift angles is labeled in the sequence as [φ, φ, φ ] with the unit f degree. The fllwing criteria are used t identify the trajectry f mdulatin variables in a three-dimensinal space. (). High specific reversed pwer; (). Zer vltage switching (ZVS) if pssible; (3). Mntnic change f pwer alng the trajectry; (4). Piecewise linear trajectry fr simplicity. The first criterin is used t reduce the current stress f cmpnents and imprve efficiency in reverse mde peratin. The secnd criterin, ZVS, is als imprtant because 00V/300A IGBTs are switched at 50kHz. Hard switching (HS) shuld be avided at high pwer levels, given the 50kHz switching frequency. At lwer pwer level, if ZVS is lst, it is easier t use snubber inductrs and auxiliary Fig. 6: The identified trajectry fr reverse mde peratin with lw cmpnent current stress fr 300V utput (V dc =750V, V ds =300V). switches t inject inductive current and retain ZVS. The third criterin is used fr simpler design f feedback cntrl lp. If the pwer des nt change mntnically alng the trajectry, the sign f small signal transfer functin will change causing ptential stability prblems. The results f the cmprehensive simulatin prcedure, fr 300V utput, are shwn in Fig. 5. T satisfy the first criterin, the chsen mdulatin strategy shuld utilize the high specific pwer perating pints. Angle cmbinatins that result in hard switching are eliminated when the pwer utput is abve 5kW. Fr pints belw 5kW, snubber inductr and/r auxiliary switches can be utilized t inject additinal inductive current at the mment f switching and facilitate the zer vltage switching f IGBTs [3]. Based n these criteria, the angle cntrl path is defined. Fig. 6 shws the identified trajectry fr angle cntrl which results in pwer regulatin frm full lad t n lad. In the figure, slid cntur lines represent the reversed pwer and the dtted line is the bundary between the sft switching (ZVS) and hard switching (HS) regin. The key pints defining the trajectry are als marked based n the abve analysis. In Fig. 6, three adjacent and perpendicular planes in the three-dimensinal mdulatin space are expanded int a tw-dimensinal plane fr simpler illustratin. T reverse the pwer frm 40kW t 0kW, the trajectry starts at [3.6, 36, 90 ] ([φ, φ, φ ]), and then ges t [3.6, 90, 36 ]. This piece f the trajectry is n the plane f φ =3.6. The rest f the trajectry mves t the plane f φ =36, starting at [3.6, 90, 36 ], thrugh [36, 44, 36 ], [90, 44, 36 ] and ending at [44, 44, 36 ]. A lk-up table is used t stre the trajectry crdinates and discussed in detail in part V. IV. REVERSE MODE MODULATION STRATEGY WITH HIGH OUTPUT VOLTAGE A similar prcedure is nw applied fr the highest expected energy strage vltage f 600V. Fig. 7 shws the utput

5 Fig. 7: The specific reversed pwer fr different cmbinatins f three phase-shift angles [φ, φ, φ ] (V dc =750V, V ds =600V). pwer pltted against the specific reversed pwer. Only the pints in the 0-40kW range f interest will be cnsidered. Based n the same trajectry selectin criteria as 300V ds the perating pints are chsen and highlighted with circles in Fig. 7. We will call this strategy. It can be fund that all these pints are n the plane f φ =44 in the threedimensinal mdulatin space. The strategy trajectry is defined with [36, 44, 90 ] fr 39kW, [90, 44, 90 ] fr 9kW and [44, 44, 90 ] fr kw lad as a straight line. It is imprtant t nte that the criterin fr mntnically regulated pwer alng the trajectry and piecewise linearity are satisfied. Hwever, tw pints in hard switching regin result in much higher specific reversed pwer. These pints are marked with squares in Fig. 7. We will call these pints strategy, which discards the requirement f cnverter nature ZVS at heavier lad cmpared t strategy. These tw pints have much lwer current stress and cnductin lss. Althugh they are in hard switching regin, at 600V utput the current in IGBTs is much smaller than that at 300V. These tw pints are bth n the plane with φ =36, and the reversed pwer with φ =36 and different φ and φ is shwn in Fig. 8. Therefre, the trajectry f the strategy starts at [36, 36, 36 ] fr 35kW lad, then ges t [90, 90, 36 ] fr 7kW, and ends at [44, 44, 36 ] at light lad. Auxiliary inductrs and switches are emplyed t btain the ZVS cnditin [3] fr strategy. T cmpare the viability f the tw mdulatin strategies, the efficiency f the tw trajectries was calculated and cmpared in Fig. 9. The high fidelity mdel cntains detailed mdeling fr all cmpnent pwer lss including the IGBT cnductin lss, experimentally validated switching lss, dide cnductin lss and reverse recvery lss, winding and cre lss f inductrs and transfrmer, gate driver lss, capacitr lss and cable lss. The accuracy f the efficiency mdel agrees very well with the 5kW experiment prttype as presented in Part VI. Frm Fig. 9, at light lad, the tw Fig. 8: The identified trajectry fr reverse mde peratin with strategy fr 600V utput vltage (V dc =750V, V ds =600V, φ =36 ). Fig. 9: The calculated efficiency fr the reverse mde mdulatin trajectries based n strategy and with 600V utput (V dc =750V, V ds =600V). strategies have similar efficiency. Hwever, frm medium t full lad, the pwer cnverter efficiency f strategy is 4-5% higher than that f strategy. Therefre, with 600V utput vltage, strategy generates a better trajectry. V. CONSIDERATIONS FOR REVERSED POWER FLOW CONTROL IN WIDE OUTPUT VOLTAGE RANGE Based n the discussin abve, the CC-SRC can be cntrlled in reverse mde in a wide vltage range f V. The actual implementatin can be achieved with a twdimensinal lk-up table (LUT) with its frmat shwn in Table II. There are tw inputs fr LUT. The first ne is a prpsed virtual phase-shift angle α, which cntrls the reversed pwer P. The secnd entry is the vltage V ds *, which defines different trajectries in three-dimensinal mdulatin space fr different battery vltage. Each rw in LUT stres a trajectry. The utput f LUT is the three phaseshift angles [φ, φ, φ ] (i,j) crrespnding t the battery string vltage V i ( i M) and the angle α j ( j N), where M is the number f vltage entries and N is the number f angle

6 TABLE II THE FORMAT OF THE LUT AND THE CORRESPONDING REVERSED POWER Fig. 0: Simulated reversed pwer f generated trajectry at V ds *=300V. entries, i and j are integers. The virtual phase shift angle α deserves further discussin. This parameter is an amalgam f the three phase shift angles and is directly used fr pwer flw cntrl. The relatin between α and P must be mntnical. Fr simplicity a linear relatinship is defined in equatin (9) fr each V ds * in LUT, where the unit f α is degree and P m is the maximum reversed pwer (e.g. 40kW): P Pm( ). (9) 80 The reversed pwer is cntrlled by nly ne variable. When α is increased, the reversed pwer decreases. This is similar t the phase-shift angle φ in frward mde pwer cntrl and greatly simplifies the cnverter cntrller design fr the reverse mde peratin. T generate a high-fidelity LUT, simulatins fllwing the prcedure in sectins III and IV were repeated fr utput vltages f 400V and 500V. The criterin in Sectin III was applied fr 400V utput and the strategy frm sectin IV was utilized at 500V. As befre, each trajectry is piecewise linear and defined by several key pints. T ensure that (9) is satisfied fr a given battery vltage, additinal 5-0 reference pints were identified using linear interplatin t evenly cver the whle trajectry. The reversed pwer fr these reference pints was measured frm the simulatins giving the apprpriate α fr these perating pints. Apprpriate phase shift angles at pints between these reference pints were generated by linear interplatin. N simulatin calibratin is required fr these pints. Fr illustratin, the simulated reversed pwer f the reference pints, sme interplated pints at V ds =300V are shwn in Fig. 0 as indicatin f gd linearity f interplatin frm the reference pints. The prcedure described abve results in smth reverse pwer flw cntrl when the cmmanded V * ds equals 300V, 400V, 500V r 600V. T achieve smth pwer cntrl fr any cmmanded vltage between 300V and 600V, trajectries fr additinal vltage cmmands are needed. T achieve this, TABLE III THE REQUIRED RESOURCES FOR LUT WITH DIFFERENT SIZE Quantity interplatin is used t determine the phase shift angles fr reference V ds * f 350V, 450V and 550V. Again, the pwer at key pints and reference pints are simulated t determine the apprpriate α t satisfy (9). Fr illustratin, the generated trajectries are shwn in Fig.. The prcedure is repeated again fr V ds * f 35V, 375V, 45V, 475V, 55V and 575V. It is fund that at these vltage trajectries the simulated P f reference pints at each α j is already very clse t the predictin by (9). One mre interplatin and recalibratin was dne t verify that the linearity is indeed achieved, resulting the ttal f 5 trajectries in LUT that all match (9). The trajectry fr the rest f the vltage can be btained by linear interplatin frm abve 5 existing trajectries in the LUT. The phase angles fr the vltage V ds at α j are calculated by (0), [,, ] K K [,, ] Cnfiguratin [,, ] ( i, j) ( V ds Cnfiguratin ( i, j) ( V V ) [,, ] i ds V ) Cnfiguratin 3 number f trajectries M number f pints n trajectry N required 6-bit memry size 9467 (903k) (75k) i 9600 (9.375k) number f nline interplatin 0 3 ttal arithmetic peratins cntrller clck 50MHz 50MHz 50MHz cmputatin time 0 90ns 660nS ( i, j), (0) where V i < V ds < V i+, i and j are integer, K =(M-)/(V M -V. ). [φ, φ, φ ] are the phase-shift angles fr V ds at α j, which are nt stred in LUT. [φ, φ, φ ] (i+,j) and [φ, φ, φ ] (i,j) are the phase-shift angles stred in the LUT frm the tw adjacent

7 This article has been accepted fr publicatin in a future issue f this jurnal, but has nt been fully edited. Cntent may change prir t final publicatin. Fig. : The generated trajectries in LUT by prpsed prcedure in wide utput vltage range f Vds: (a) φ, (b) φ, (c) φ. Fig. : The diagram f the LUT based mdulatr. trajectries crrespnding t Vi+ and Vi at the same αj. The size f the lk-up table is the trade ff between the required memry size and the cmputatin time f the digital cntrller. Three cnfiguratins f the LUT are prpsed in Table III. Each angle is stred in a 6-bit memry cell. In cnfiguratin and, 0-bit reslutin is used fr the virtual angle s that there is n requirement fr n-line interplatin fr α. Linear interplatin fr Vds is achieved frm 5 existing trajectries by applying (0). In cnfiguratin the interplatin is calculated ff-line, whereas fr cnfiguratin the interplatin is calculated n-line. In cnfiguratin 3, t reduce the size f the LUT, linear interplatin is perfrmed n-line fr bth α and Vds fllwing () - (3), [,, ]' K [,, ](i, j ) ( j ) K [,, ]( i, j ) ( j ) [,, ]( i, j ), [,, ]' ' K [,, ](i, j ) ( j ) K [,, ](i, j ) ( j ) [,, ](i, j ) [,, ] K [,, ]' ' (Vds Vi ) K [,, ]' (Vds Vi ) [,, ]', (), () (3) where Vi < Vds < Vi+, α j < α < α j+, i and j are integer, K=(M-)/(VM-V.), K=(N-)/80. T calculate the phase-shift angles [φ, φ, φ] at α and Vds, the interplatin can be cnducted first fr the intermediate angles [φ, φ, φ] n trajectry Vi by () and [φ, φ, φ] n trajectry Vi+ by () fr α, and then t btain [φ, φ, φ] frm [φ, φ, φ] Fig. 3: The prttype f the 5kW scaled-dwn bi-directinal series resnant DC-DC cnverter with clamped capacitr vltage (CC-SRC). and [φ, φ, φ] fr Vds based n (3). Cnfiguratin requires external memry but cnsumes the least arithmetic resurces. Cnfiguratin and 3 utilize the n-chip memry f state-f-the-art micrcntrller. Cnfiguratin 3 requires minimal memry size but cnsumes mre arithmetic resurces. Hwever, the cmputatinal time is apprximately.66us and nly a small prtin f the 0uS switching cycle. The diagram f the LUT based mdulatr fr cnfiguratin 3 is shwn in Fig.. The sensed battery pack vltage is sent t Vds and the cntrller utput is cnnected t α. The synthesized angles [φ, φ, φ] are inputs f the phase shift pulse width mdulatin (PSPWM) mdule t generate IGBT gate signals f S-S8 fr required reverse pwer P(j). It is nted that in energy strage applicatins such as batteries and ultracapacitrs, Vds changes at a much slwer rate than the speed f the pwer regulatin lp. VI. SIMULATION AND EXPERIMENTAL RESULTS A 750V input, V utput and 50kHz switching frequency prttype with 5kW scaled-dwn pwer rating is cnstructed t verify the reverse mde peratin f the CCSRC. The picture f the prttype is shwn in Fig. 3. The cmpnents used in the prttype include, IGBTs: APTGF300A0G; Clamping dides: APTDF400AK60G in series;

8 This article has been accepted fr publicatin in a future issue f this jurnal, but has nt been fully edited. Cntent may change prir t final publicatin. Fig. 4: Simulatin (a) and experiment (b) wavefrms in reversed mde with Vds=300V and.6kw lad (φ=6, φ=5, φ=36 ). Fig. 5: Simulatin (a) and experiment (b) wavefrms in reversed mde with Vds=600V and 4.8kW lad (φ=6, φ=4, φ=36 ). Transfrmer turns rati: ::; Transfrmer primary winding leakage: 0.6uH; Transfrmer secndary winding leakage: 7.5uH; Transfrmer magnetizing inductance: 30uH (referred t the secndary side T3); Resnant inductrs:.0uh; Resnant capacitance: 0.9uF; It shuld be nted that there is additinal 7.5uH series leakage inductance in the transfrmer secndary winding T3. This is the majr difference between the experimental implementatin and the simulatin discussed abve where the leakage inductance is assumed t be zer. The simulatin and experiment wavefrms with 750V input (Vdc) and 300V utput (Vds) and.6kw lad in DC-link fr the reversed mde peratin f the CC-SRC are shwn in Fig. 4 (a) and (b) respectively. The reference directin f il, il and it3 fr all the simulatin and experiment wavefrms is labeled in Fig.. The phase shift angles used in the experiment is φ=6, φ=5 and φ=36. The reverse pwer is lwer than that predicted in Fig. 6 due t the additinal 7.5uH transfrmer leakage inductance. The simulatin wavefrms cincide well with the experiment wavefrms. The simulatin and experiment wavefrms with 750V input Fig. 6: The experiment test wavefrms f nature ZVS peratin fr primary side full bridge (S and S4) in reverse mde peratin. (Vdc) and 600V utput (Vds) and 4.8kW DC-link lad fr the reversed mde peratin f the cnverter are shwn in Fig. 5 (a) and (b) respectively. The phase shift angles used in the experiment is φ=6, φ=4 and φ=36. The experimental wavefrms f zer vltage switching (ZVS) in reverse mde peratin with 300Vds and 750Vdc/8.6kW reversed pwer are shwn in Fig. 6. Dual

9 Fig. 8: The calculated and experiment tested efficiency in frward mde with 300V and 600V utput vltage f V ds (V dc =750V). Fig. 7: The simulated reverse mde transient respnse fr DC-link lad change with prpsed mdulatin technique (V ds =300V, V dc =750V). pwer supply vltage (+5V and -5V) is used fr the gate driver. Fr primary side bridge, nature ZVS is btained and Fig. 6 shws the gate drive vltage V ge and utput vltage V ce f S and S4. Auxiliary inductr and switches are required fr secndary side IGBTs S7/8 t achieve ZVS at this lad. T verify the prpsed mdulatin technique and LUTbased mdulatr, the cnverter transient respnse in reverse mde was simulated with clse-lp feedback cntrl. The effectiveness f simulatin mdel was verified by Fig. 4 - Fig. 5. The DC-link vltage (V dc ) is sampled and regulated t 750V by a PI cntrller with the utput cnnected t the input α f the LUT-based mdulatr (see Fig. ). V ds is battery vltage. The lad current in DC-link side (i dc ) switches between the half and full lad. The wavefrms f DC-link vltage, lad current, AC vltage f primary and secndary full bridges, current in transfrmer primary and secndary windings, three phase-shift angles and the virtual phase-shift angle, at 300 V ds, are shwn in Fig. 7. Pwer lss mdels were built fr each cmpnent in the cnverter t predict the efficiency in full lad range. The calculated efficiency curves in frward mde with 300V and 600V utput are shwn in Fig. 8. The experimental tested efficiency pints f 5kW prttype are als shwn in Fig. 8, which indicate gd agreement with the mdel predictin. Frm the medium t heavy lad range, the efficiency ranges frm 94%-96% with 600V utput and 9%-9% with 300V utput. It can be bserved that the 300V utput efficiency decreases at high pwer utput. One pssible reasn is the large rati f reactive current due t the high quality factr Q at heavy lad (small R e ) assciated with lwer V ds. Larger phase-shift angle φ is required fr 300V utput than fr 600V at the same utput pwer, which als injects mre current t D& and results in higher clamping circuit lss. The calculated efficiency curves in reversed mde peratin with 300V and 600V utput are shwn in Fig. 9. The efficiency curve with 600V utput is calculated based n Fig. 9: The calculated and experiment tested efficiency in reversed mde with 300V and 600V utput vltage f V ds (V dc =750V). the reverse mdulatin strategy. The experimental tested efficiency pints f the prttype are als shwn in Fig. 9. Cmpared t the frward mde the reverse mde efficiency drps abut -3% frm the medium t high pwer range. This is mainly due t the additinal turn-ff lss cntributed by the secndary side IGBTs S5-S8. The efficiency drp at heavy lad is bserved as well fr 300V ds. In reversed mde, the reactive pwer can be indicated by phase-shift angles. With 300V battery vltage, it is mre difficult t reverse the pwer flw and the secndary side full bridge needs t lead the primary side by a larger angle at heavy lad (φ =90 ). Hwever, this angle als causes higher reactive pwer in the circuit, whereas fr 600V ds, φ is nly 36. The pwer lss breakdwn analysis fr the CC-SRC prttype in reverse mde with 300V ds /.6kW is shwn in Fig. 0. The cnductin and turn-ff lss f S3&S4 are larger than that f S&S because frm Fig. 4 the mdulatin strategy at.8kw reversed pwer results in higher current stress (i L ) in T, L, S3/D3 and S4/D4 branch than that (i L ) in T, L, S/D and S/D branch. But at high pwer r high utput vltage level, the current unbalance is mitigated.

10 Fig. 0: The pwer lss distributin fr the 5kW prttype with 300V ds /.6kW in reverse mde (ttal lss 035W, V dc =750V, V ds =300V). VII. CONCLUSION The series resnant DC-DC cnverter with clamped capacitr vltage (CC-SRC) exhibits excellent characteristics in frward mde, but single phase-shift angle cntrl cannt reverse the pwer flw. The advanced mdulatin strategy based n three phase-shift angles is prpsed t reverse the pwer flw and the ptimum mdulatin trajectries with lw and high utput vltage in three-dimensinal space are identified, based n the design f experiment and systematic numeric simulatin apprach. A LUT based digital mdulatr is prpsed t simplify the angle cntrl strategy. The prpsed cnverter peratin is verified by a scaled-dwn experimental prttype and the simulatin wavefrms cincide well with test wavefrms. The cnverter efficiency is calculated and verified fr bi-directinal peratin. ACKNOWLEDGMENT The authrs wuld like t thank Prfessr Ming-Jun Lai at Department f Mathematics, University f Gergia fr his genersity fr prviding us with his MATLAB prgrams f trivariate splines fr data interplatin which are based n thery f multivariate splines. REFERENCES [] S. M. Lukic, J. Ca, R. C. Bansal, F. Rdriguez and A. Emadi, Energy strage systems fr autmtive applicatins, in IEEE Transactins n Industrial Electrnics, vl. 55, n. 6, pp , Jun [] S. Vazquez, S. M. Lukic, E. Galvan, L. G. Franquel and J. M. Carrasc, Energy strage systems fr transprt and grid applicatins, in IEEE Transactins n Industrial Electrnics, vl.57, n., pp , Dec. 00. [3] A. Emadi, Y. J. Lee and K. Rajashekara, Pwer electrnics and mtr drives in electric, hybrid electric, and plug-in hybrid electric vehicles, in IEEE Transactins n Industrial Electrnics, vl. 55, n. 6, pp , Jun [4] Z. Amjadi and S. S. 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DiPerna, Design f a series resnant cnverter with clamped capacitr vltage and anti-crss-cnductin inductrs, in IEEE 998 Applied Pwer Electrnics Cnference and Expsitin, vl., pp , Feb.998. [3] B. S. Jacbsn, J. McGainty and P. C. Thmas, Methd and apparatus fr a pwer system fr phased-array radar, United States Patent, N. 6,856,83, Feb.005. [3] T. Kat and G. C. Verhgese, Efficient numerical determinatin f bundaries between perating mdes f a pwer cnverter, in IEEE 99 Wrkshp n Cmputers in Pwer Electrnics, pp. 05 6, Aug.99. [33] T. T. J. H, G. C. Verghese, C. Osawa, B. S. Jacbsn and T. Kat, Dynamic mdeling, simulatin and cntrl f a series resnant cnverter with clamped capacitr vltage, in IEEE 994 Pwer Electrnics Specialists Cnference, vl., pp.89-96, Jun.994. [34] Y. Du, X. Bian, S. M. Lukic, B. S. Jacbsn and A. Q. Huang, A nvel wide vltage range bi-directinal series resnant cnverter with clamped capacitr vltage, in IEEE 009 Annual Cnference f Industrial Electrnics Sciety, pp.8-87, Nv.009. [35] G. Awanu, M. J. Lai, and P. Wenstn, The multivariate spline methd fr numerical slutin f partial differential equatins and scattered data interplatin, in Wavelets and Splines: Athens 005, edited by G. Chen and M. J. Lai, Nashbr Press, 006, pp [36] R. W. Eriksn and D. Maksimvic, Fundamentals f Pwer Electrnics, nd ed. Kluwer Academic Publishers, 00, pp Yu Du (S 0) was brn in Chengdu, Sichuan, China. He received the B.S. and M.S. degrees in electrical engineering (pwer electrnics) in 00 and 005 respectively, frm the Department f Electrical Engineering at Zhejiang University, Hangzhu, China. Frm 005 t 007, he was with Glbal Research Center (Shanghai, China) f General Electric Cmpany (GE). He develped medical pwer supplies fr GE Healthcare and cnducted interdisciplinary research n nvel electric-driven desalinatin prcess. He is the recipient f 006 Glbal Research Rkie Award. Since 007, Mr. Du has been wrking twards his PhD degree in NSF FREEDM Systems ERC at Nrth Carlina State University, Raleigh. He was exchanged t the Pwer Electrnics Systems Lab at ETH-Zurich, Switzerland fr three-mnth research. His research interests include ultra-cmpact bidirectinal cnverters, high vltage cnverters and distributed energy strage systems. He hlds 6 U.S. patents and has tw U.S. patents pending. Carlina State University, Raleigh. He serves as a Faculty Member and Testbed Leader fr plug-in hybrid electric vehicles in the Future Renewable Electric Energy Delivery and Management Systems Engineering Research Center. His research interests are bradly in the field f pwer electrnics and mtr drives applied t electric energy strage systems, electric vehicle drivetrains, and inductive pwer transfer systems. Bris S. Jacbsn received a Diplma in electrical engineering (pwer electrnics) in 974 frm St. Petersburg Electrtechnical University, St. Petersburg, Russia and a MSEE (systems) degree in 989 frm the University f Lwell, Lwell, MA. He has 36 years f experience in such pwer electrnics areas as plasma arc treatment, mining, medical equipment, data prcessing, military electrnics and shipbard systems. He jined Raythen Cmpany in 987 where he wrks n pwer systems and cnverters and cnsults thrughut Raythen. Currently, he wrks as Technical Directr fr the Cmpact Pwer Cnversin Technlgies (CPCT) prgram (Office f Naval Research). The CPCT effrt changes paradigm fr shipbard pwer systems and Micr-Grids. His area f expertise cvers systems, grunding methds, lw-nise system, high frequency cnverters and magnetics. He published 8 papers and has patents in the fields f cnverters tplgies, system architectures and magnetic devices. Bris is a Senir Member f IEEE and serves n several IEEE Standards cmmittees including IEEE Guide fr Recmmended Practice fr Electrical Installatins n Shipbard - Systems Integratin and IEEE Guide fr Cntrl Architecture fr High Pwer Electrnics ( MW and Greater) used in Electric Pwer Transmissin and Distributin Systems. He served n Technical Cmmittees f fr ASNE Day Cnference, IEEE Electric Ship Technlgies Sympsiums. Alex Q. Huang (Fellw, IEEE) was brn in Zunyi, Guizhu, China. He received the B.Sc. degree frm Zheijiang University, Hangzhu, China, in 983 and the M.Sc. degree frm Chengdu Institute f Radi Engineering, Chengdu, China, in 986, bth in electrical engineering, and the Ph.D. degree in electrical engineering frm Cambridge University, Cambridge, U.K., in 99. Frm 99 t 994, he was a Research Fellw at Magdalene Cllege, Cambridge, U.K. Frm 994 t 004, he was a Prfessr at the Bradley Department f Electrical and Cmputer Engineering, Virginia Plytechnic Institute and State University, Blacksburg. Since 004, he has been with Nrth Carlina State University, Raleigh, and is currently the Prgress Energy Distinguished Prfessr f Electrical and Cmputer Engineering and directs the NSF FREEDM Systems ERC, NCSU Advanced Transprtatin Energy Center (ATEC). Since 983, he has been invlved in the develpment f mdern pwer semicnductr devices and pwer integrated circuits. He fabricated the first IGBT pwer device in China in 985. He is the inventr and key develper f the emitter turnff thyristr technlgy. His current research interests are utility pwer electrnics, pwer management micrsystems, and pwer semicnductr devices. He has published mre than 00 papers in the internatinal cnferences and jurnals, and has 4 U.S. patents. Dr. Huang is the recipient f the Natinal Science Fundatin (NSF) CAREER award and the prestigius R&D 00 Award. Srdjan M. Lukic (S 0 M 07) received the M.S. and Ph.D. degrees in electrical engineering frm the Illinis Institute f Technlgy, Chicag, in 004 and 007, respectively. Frm 00 t 004, he was with Firefly Energy Inc., where he was respnsible fr ptimizing certain aspects f carbn/graphite fam-based lead acid batteries fr nvel autmtive applicatins. He is currently an Assistant Prfessr in the Department f Electrical and Cmputer Engineering, Nrth