Impedance matching concept given ZL, design a matching network to have in=0 or selected value. matching. Zin (=Z Z o )

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Chapter 5 Ipedance atching and tuning 5. Matching with luped eleents -sectin atching netwrks using Sith chart 5. Single-stub tuning shunt stub, series stub 5.3 Duble-stub tuning frbidden regin 5.

1 Chapter 5 Ipedance atching and tuning 5. Matching with luped eleents -sectin atching netwrks using Sith chart 5. Single-stub tuning shunt stub, series stub 5.3 Duble-stub tuning frbidden regin 5.4 The quarter-wave transfrer frequency respnse 5.5 The thery f sall reflectins single-sectin transfrer, ulti-sectin transfrer 5.6 Binial ultisectin atching transfrers 5.7 Chebyshev ultisectin atching transfrers 5.8 Taper lines expnential taper, triangular taper 5.9 The Bde-Fan criterin -Bandwidth 5-

2 Ipedance atching cncept given, design a atching netwrk t have in=0 r selected value atching in netwrk in (= ) Discussin. Matching netwrk usually uses lssless cpnents:, C, transissin line and transfrer.. There are pssible slutins fr the atching circuit. 3. Prperly use Sith chart t find the ptial design. 4. Factrs fr selecting atching circuit are cplexity, bandwidth, ipleentatin and adjustability. 5-

3 5. Matching with luped eleents (-eleent -netwrk) Sith chart slutin cnstant G-circle cnstant R-circle C -plane Y-plane CW add series CW add shunt C (reduce series C) (reduce shunt ) CCW add series C CCW add shunt (reduce series ) (reduce shunt C) 5-3

4 j0.5 -j0.5 (explanatin) A C C C j -j B D -j j cnstant R-circle r C in series.5 () CW A B : j0.5 jx j jx j.5 j : add an in series () CCW B A: j jx j0.5 jx j.5 C jc.5 : add a C in series.5 r CCW B A: j jx j0.5 jx j.5 j.5 : reduce extra jx j.5 (r reduce series by ) (3) CCW C D : j0.5 jx j jx j.5 C jc.5 : add a C in series.5 (4) CW D C : j jx j0.5 jx j.5 j : add an in series r CW D C : j jx j0.5 jx j.5 C jc.5 reduce extra jx j.5 (r reduce series C by C ).5 in -plane CW add a series (r reduce series C) CCW add a series C (r reduce series ) 5-4

5 cnstant G-circle r C in shunt -j j A C C -j C j -j0.5 B D j0.5.5y () CW A B : j jb j0.5 jb j.5y jc C : add a C in shunt r CW A B : j jb j0.5 jb j.5y j.5y : reduce shunt jb j.5 Y (r reduce shunt by ).5Y () CCW B A : j0.5 jb j jb j.5 j : add an in shunt (3) CCW C D : j jb j0.5 jb j.5 j : add an in shunt.5y r CCW C D : j jb j0.5 jb j.5y jc C.5Y reduce shunt jb j.5 Y (r reduce shunt C by C ) (4) CW D C : j0.5 jb j jb j.5 jc : add a C in shunt in Y-plane CW add a shunt C (r reduce shunt ) CCW add a shunt (r reduce shunt C) 5-5

6 Discussin. inside +jx circle, tw pssible slutins Sith chart slutin (shunt-series eleents) +jb circle B z +jx circle A: A B: series-shunt eleents? N analytical slutin jx jx jb 5-6 jb R jx B 0 C,B 0 X 0, X 0 C

7 . utside +jx circle, tw pssible slutins Sith chart slutin (series-shunt eleents) +jb circle B A z +jx circle A B shunt-series eleents? Y analytical slutin jb jx R j( X X B 0 C,B 0 jb X 0, X 0 C ) 5-7

8 3. Ex. 5. =00-j00, =00, f=500mhz A: B A 3 C z. z=-j, y=0.4+j0. Slutin A. y=0.4+j0.5 jb=j0.3 jb=jc=jb/ C=b/ =0.9pF z=-j. jx=j. jx=j =jx =x / =38.8nH Slutin B 3. y=0.4-j0.5 jb=-j0.7-jb=/j=-jb/ =- /b=46.nh z=+j. jx=-j. jx=/jc=-jx C=-/x =.6pF frequency respnse (p.33, Fig.5.3(c)) B: C 5-8

9 4. Pssible 3-eleent -netwrk z +jx circle series? Y +jb circle z 5-9

10 5. Pssible 4-eleent -netwrk shrter paths fr a wider peratinal bandwidth z +jx circle +jb circle z 5-0

11 6. uped eleents (size</0) capacitr: chip capacitr, MIM capacitr (<5pF), interdigital gap capacitr (<0.5pF), pen stub(<0.pf) inductr: chip inductr, lp inductr, spiral inductr (<0nH) resistr: chip resistr, planar resistr All these luped eleents inherently have parasitic eleents in the icrwave range. (p.33, pint f interest ) B A C D 5- Size (il) A B C D il=0.00in=5u=/40

12 5. Single-stub tuning equivalent icrstrip eleents a series C --- a series in series with a high ipedance icrstrip line a shunt C in shunt with an pen icrstrip line, r in series with a lw ipedance icrstrip line a shunt in shunt with a shrt icrstrip line an pen-circuited icrstrip line a shrt-circuited icrstrip line in in j tan l jc j tan l j, l a high/lw ipedance icrstrip line l j tan Y3 l j tan sin l j 5- high lw j l βl j

13 (derivatin f high/lw ipedance line), l l j tan Y3 high,y3 0 l j tan sin l j j βl l βl l j βl jω ω c 3 jsin l 3 j csc l Y3 j sin l j (ct l csc l) j l cs l sin l l sin lsin cs 5-3 l j sin cs lw,, 0 slide (4 ) j (ct l csc l) j cscl 3 cs l sin l sin j tan l l l βl βl l j jωc C ω c l βl j

14 Discussin. Shunt stub Sith chart slutin y in jb jc d G y l y in jb cnstant -circle y in jb j d G y l y in jb 5-4

15 . Series stub Sith chart slutin z in jx d G z l z in jx jc z in jx d G z l z in jx j 5-5

16 3. Ex. 5. =60-j80, =50, f=ghz, using a shunt shrt stub G S.C. l 3 4. z=.-j.6, y=0.3+j0.4 Slutin A B. y=+j.47 d=0. 3. y=-j.47 l=0.095, shrt stub 5 l A z Slutin B 4. y=-j.47 d= y=j.47 l=0.405, shrt stub d frequency respnse (p.37, Fig.5.5(c)) Slutin A has a wider bandwidth. l 5-6

17 4. Ex. 5.3 =00+j80, =50, f=ghz, using series pen stub G l B 4 A 3 5 z O.C. l. z=+j.6 Slutin A. z=-j.33 d=0. 3. z=j.33 l=0.397, pen stub Slutin B 4. z=+j.33 d= z=-j.33 l=0.03, pen stub frequency respnse (p.40, Fig.5.6(c)) It can nt be ipleented in icrstrip lines. 5-7

18 5. Analytical slutin fr shunt stub Y in jb d l Y in Y jb j tan d Y Re d j tan d pen stub j tan d tan l B I l j tan d shrt stub tan l 5-8

19 6. Analytical slutin fr series stub in jx d l in jx j tan d Re d j tan d j tan d - pen stub X I tan l l j tan d tan l shrt stub 5-9

20 5.3 Duble-stub tuning 4, 5 ±jb, 3 /8 G 5 z l l frbidden regin 3 4 Discussin. There exists a frbidden regin fr. It can be tuned ut by adding a certain length f line. 5-0

21 G l. Ex. 5.4 =60-j80, =50, f=ghz, using duble-shuntpen-stubs. z=.-j.6, y=0.3+j0.4 l 7 Slutin A 6. y=0.3+j b = l 5 = y=+j b = -.38 l =0.35 O.C. B A 4 Slutin B 3. y=0.3+j b =.34 3 z l = l 5. y=-j b = 3.38 l 8 l =0.04 /8 l l 5- frequency respnse (p.45, Fig.5.9(c))

22 3. Analytical slutin Y = Y - jb Y d l jb l jb Y Re Y Y Y Y I jb, Y Y B Y B l l jb j j tan d tan d 5-

23 5.4 The quarter-wave transfrer frequency respnse l / 0=0 / 0= (real) Γ( θ ) cs, fr near, l - : ax. tlerated Γver the bandwidth f 4 Γ f π cs ( ),, increases f Γ 5-3

24 (derivatin f (θ) cs ) j tan ( ) j tan j tan ( θ) ( ) j tan j tan in j tan j tan in j tan ( ) ( ) j tan j tan j tan sec cs Δf 4 (derivatin f cs ( )) f π Γ / 5-4 Γ j ( θ) ( ) 4 4 / [( ) ( tan ) ] [ tan ] ( ) ( ) 4 [ sec ] ( ) tan /

25 Γθ ( ) 4 [ sec ] ( ) / ( ) cs ( ) cs cs f f vp( f) f f f TEM line: l v ( f ) 4 v ( f ) 4 f f f f f f p p ( f f) f 4 4 cs f f 5-5

26 partial reflectin cefficients 5.5 The thery f sall reflectins single-sectin transfrer, 3 T T 3 (real) in in T e 3 T e j j e j 3 e j, T, T Γ in 5-6 jθ 3 jθ ΓΓ3e Γ Γ Γ e ( )( ) Γ e Γ Γ jθ jθ 3 3 jθ ΓΓ3e Γ e Γ Γ e 3 3 TT Γe jθ jθ Γ Γ e if jθ 3

27 ultisectin transfrer N N (real) Γ( ) Γ Γ e Γ e... Γ e, if Γ Γ, Γ Γ... jθ j4θ j Nθ N N N e [ Γ ( e e ) Γ ( e e )... Γ ( e e )] N dd e Γ e e Γ e e Γ N even jnθ jnθ jnθ j( N ) θ j( N ) θ jθ jθ ( N)/ jnθ jnθ jnθ j( N ) θ j( N ) θ [ ( ) ( )... N/ ] jnθ e [ Γ cs N Γ cs( N )... Γn cs( N n)... Γ( N )/ cs ] N dd jnθ e [ Γ cs N Γ cs( N )... Γn cs( N n)... Γ N / ] N even given Γ( ), design,,... n 5-7

28 5.6 Binial ultisectin atching transfrer axial flatness respnse fr () jθ N N N jnθ jθ j4θ n N jnθ n0 Γ( ) A( e ) A C e Γ Γ e Γ e... Γ e Γ n AC N n Discussin. Maxial flatness respnse,. 3. (p.54, Table 5. fr n values) 5-8 d N d Γ( ) N N N Γ(0) A A Γ x ln (ln ) x n n n n x n n n rl 4 0 n N N N N N ln Γn ACn Cn Cn ln n

29 4. Δf 4 Γ N N N cs [ ( ) ], N, Δ f, Γ A cn θ f π A jθ N N N Γ( ) A( e ) Γ( ) A cs f 4 4 f cs [ ( N ) ] 5. Ex.5.6 =50, =00, N=3, =0.05 Δf N 3, A ln , 70% N N f ln C ln ln C ln 9.7 n N N 3 3 n 0 n ln C ln 70.7, ln C ln (p.56, Fig.5.5 fr frequency respnse f Γ ) 5-9 Γ A

30 5.7 Chebyshev ultisectin atching transfrers Equal ripple respnse fr (): ptial design jnθ Γ( ) e [ Γ cs N Γ cs( N )... Γ cs( N n)...] jnθ Ae T (sec cs ) Γ (p.60, Table 5.) N n T ( x) x, T ( x) x, T ( x) 4x 3 x, T ( x) 8x 8x, cs Tn ( x) xtn- ( x) Tn- ( x), x, x cs Discussin.. (0) AT N (sec θ) A T (sec θ ) AT () A T N 3. Optial design: given, axial f given f, inial. N f 4 (sec ) (5.63) Γ f N 5-30 n - x π-θ θ

31 4. Ex.5.7 =00, =50, N=3, =0.05 N 3, Γ( ) e ( Γ cs 3 Γ cs ) Ae T (sec cs ) Ae j3θ 3 3 j3θ j3θ 3 (4sec cs 3sec cs ) j3θ 3 Ae [sec (cs 3 3cs ) 3sec cs ] f A Γ sec = % T f 3(sec ) 3 Γ Asec Γ Γ3 Γ A(3sec 3sec ) Γ Γ Γ Γ Γ Γ frequency respnse (p.6, Fig.5.7) 5-3

32 5.8 Tapered lines Frequency respnse (z) + 0 z z+z z d d ln d dz dz d dz jz ( ) e (ln ) 0 dz 5-3

33 Discussin. Expnential taper az ( z) e 0 z a ( ) e a ln d sin Γ e e dz e jz az j ( ) (ln ) ln 0 dz, Γ( ) (p. 63, Fig.5.9). Triangular taper (z/) ln e 0 z (z) ( 4z/z / ) ln e z j sin( ) Γ( ) ln e [ ] first null at (p. 64, Fig.5.0) 5-33

34 3. Klpfenstein taper z ( ) (5.74), (5.75), Γ( ) (5.76), ptial taper 4. Ex.5.8 =00, =50, =0.0 az expnential taper: ( z) e, a ln sin Γ( ) ln sin triangular taper: Γ( ) ln [ ] cs ( ) A Klpfenstein taper: Γ( ) Γ, A 3.543, Γ csh A frequency respnse (p. 66, Fig.5.) 5-34

35 5.9 The Bde-Fan criterin lssless () atching C R 0 netwrk ln d ( ) RC Discussin. ln/ ln/ 5-35

36 0 ln ln d ln ( ) RC d : cnstant () given RC () 0, unless =0 i.e., =0 nly at a finite nuber f frequencies (3) R and/r C and/r high Q lad is harder t atch lssless () atching C R netwrk 5-36 parallel resnatr Q= RC

37 Slved prbles: Prb.5.7 find and l.95+j0.98 z 4+j =40Ω, l 00+j00 zin r in 0.8 r ax j00 j tan l j (00 j 00) tan l 40 j8000 tan l 4000 tan l 00 j00 j tanl tan l 00 j8000 tan l j00 j tanl 5tan l j j j l l 0.5 l tan tan kr k, 50 kr R ' in in ' in R' ax ax ' ax r' in r' ax in ax R ' R' k r ' r ' k 4. k.05 () (50)

38 Prb.5.4 find the best R ver perating range f 3.~0.6GHz () UWB netwrk 0.6pF 75Ω 0 ln d Γ( ) ln (0.6 3.) ln , R 6.4dB RC 5-38

39 Prb. Fr a lssless and reciprcal tw-prt atching netwrk, * * if then. s in ut ssless and reciprcal atching circuit S in ut () if S in S S in in in S in in in in in S in in S in in in in in in in S ( ) in in in in in if ut ut ut ut ut ut ut ut ut ut ut ut ut ut ut ut ut ut ( ) ut ut ut ut ut 5-39

40 S S S S 0...( i) lssless S S S S S S 0...( ii) () S S S S...( iii) in ADS exaples: Ch5_prj 5-40 ssless and reciprcal atching circuit S S...( iv) S in () i SS SS S S S S S S S S SS S SS S SS S S S S S S S S S S S S S S S S ( iii) in if ut S in...( v) ( ) () i SSS SS S S S S SS S S S SS SS S SSS S SSS S S S S S S S S ( ) S ( ) ( ),( ) ( ) S iv i ii v SS SS SS SS S( in S) S SS S SSS S SSS S( Sin ) SS S S( S S SS S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S ( ) ) S ut

Impedance Matching and Tuning

C h a p t e r F i v e Impedance Matching and Tuning This chapter marks a turning point, in that we now begin to apply the theory and techniques of previous chapters to practical problems in microwave engineering.