Current-Source Modular Medium-Voltage Grid- Connected System with High-Frequency Isolation for Photovoltaic Applications

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1 Current-Surce Mdular Mediu-ltage Grid- Cnnected Syste with High-Frequency slatin fr Phtvltaic Applicatins Ahed Darwish *, and Mhaed A. Elgenedy, Meber, EEE * a.badawy@lancaster.ac.uk Abstract Large-scale grid-cnnected phtvltaic energy generatin systes are prgressg rearkably benefitg fr the latest develpents slid-state seicnductrs technlgy. n such systes, the phtvltaic arrays can be cnnected directly t the ediu-vltage grid withut eplyg a bulky le-frequency transfrer t step up the vltage. Nancrystalle cres with a sall size and a high pereability peratg at ediu r high frequency can be stalled the pwer cnversin stage. Hence, the necessary islatin as well as vltage bstg features can be prvided. Hwever, nly a few pwer cnverters allw this type f islatin. his paper prpses a new dular cnverter structure suitable fr ediu-vltage grid cnnected systes with high-frequency islatin. he utput vltages f the series-cnnected dules are added rder t prvide the necessary vltage bstg. Fur different pwer cnverter tplgies with sall put capacitrs can be used as subdules fr the presented ediu-vltage cnfiguratin havg different advantages and drawbacks. hese different tplgies are analysed ters f pwer lsses, ftprt and functinality. validate the atheatical analysis and the cputer siulatins, a scaled-dwn 5 ka three-phase, k prttype is built and tested with fur dules fr each phase. nde ers-- Mdular ediu-vltage cnverter, phtvltaic pwer plants, renewable energy systes. R. NRODUCON ECENLY, there is a rearkable crease the stalled capacity f renewable energy pwer plants, especially phtvltaic systes. he cuulative capacity f stalled P syste wrldwide is estiated t be re than 500 GW by the end f 08 []. ndia and Cha have several P plants with pwer capacity f re than 50 MW. Other prects generatg electrical pwer f re than 300 MW are already service. Hwever, these etreely large-scale pwer plants have t be built n large areas and therefre they are cnvenient rural areas. he ttal stalled capacity Eurpe has eceeded 03 GW 06 []. n the near future, it is epected that a huge nuber f P pwer plants will be stalled the Middle East and Nrth Africa (MENA) regin which has ecellent cnditins fr P pwer generatin vestents. n Eurpe, new P pwer plants f capacity re than 8 GW are stalled 05 []. Accrdgly, creasg the efficiency and iprvg the reliability f such P plants beces re iprtant. n ttal, P pwer shares arund 5% f the ttal Eurpean pwer deand []. terface these P systes t the ediu/high-vltage grids, a large step-up transfrer peratg at the ac lefrequency is stalled t atch the vltage levels, which are nrally between 6.6k t 33k. Fr eaple, the k, MA vacuu cast cil dry-type ier transfrer fr ABB weights 5 tns and has a vlue f 3. his adds t the ttal cst, weight and size, let alne the required atenance f the syste especially when it is stalled rural distant areas. he latest develpents sei-cnductr pwer switches technlgy led t the eergence f cascaded dular ultilevel cnverter (MMC) with large nuber f subdules (SMs) as key players several applicatins [3] [5]. Such systes have the advantages f dularity and scalability where additinal dules can be easily stalled if it is required t crease the vltage/pwer levels the future. Als, it is easy t replace a faulted dule if it has been daaged fr any unplanned reasn and hence the reliability f the syste is creased. Hwever, MMC tplgies require balancg techniques fr the different SMs vltages r balanced ultiple dc supplies have t be used. n additin, the cnventinal half-bridge MMC dules are nt able t prvide fault-ride-thrugh capability fr faults at the put side, epsg the vulnerable dides t severe and destructive currents [6]. n [7], an MMC tplgy with H-bridge dules is used with ultiple P arrays actg as islated put dc surces prpsg iprtant features fr ediu-vltage systes. As a drawback, the leakage currents flwg thrugh the stray capacitance between the P neutral pt and the grund fr a ar risk fr the syste safety, peratin and lifetie [8]. Fr this reasn, dc/dc dular structures based n sall-size High Frequency (HF) islatg transfrers are prpsed t avid risks and iprve the syste safety cnditins. ncreasg the switchg frequency f the cnverter leads t a significant decrease the islatg transfrers sizes, weights, and vlues [8]. n additin, the islatg transfrer prvide a beneficial vltage bstg as well as Electr-Magnetic nterference (EM) itigatin which is very critical these applicatins [9]. nspectg the different tplgies f pwer electrnic cnverters [0] and [], fur buck-bst tplgies that have the ability t be islated with HF islatg transfrers can be fund naely, C5 (Cuk), F5, G5 (SEPC), and P5, see Fig.. hese cnverters have tw prciples fr energy transfer between the put and utput sides. Fr C5, G5, and P5, the energy is transferred stantaneusly between the priary and secndary sides f the transfrer withut beg

2 stred side it. Cnsequently, a sall transfrer cre can be used. While F5, the energy is teprarily stred the agnetic cre f the transfrer and then released after a perid f tie. S, the cre vlue liits the aiu transferred energy which equals ½BH lue [9]. Fr the abveentined buck-bst tplgies, the put current is cntuus and therefre the put filterg capacitances are nt necessarily large. his allws usg plastic r fil capacitrs which have lifetie uch lnger than electrlytic capacitrs rated at the sae peratg vltages and currents. he rise f the syste peratinal teperature causes a significant reductin the electrlytic capacitrs lifetie [9]. Cnsequently, eliatg electrlytic capacitrs can significantly iprve the reliability f cnverters []-[3]. his paper presents a new dular cnverter structure fr a three-phase ediu-vltage P syste based n the HF islated current surce buck-bst cnverters shwn Fig.. As shwn the blck diagra Fig., the utput terals f the dules f each phase are cnnected series rder t crease the ttal utput vltage and t enable direct grid cnnectin. he prpsed structure prvides the required galvanic grid-islatin and vltage bstg. n additin, it eliates the need t bulky le-frequency transfrers and reduces the required le filters. he agnetic islatin each subdule aids reducg the cn de and vltage ibalance prbles P dules. Owg t the cntuus current nature at the put side, the candidates fr this structure are suitable fr Maiu Pwer Pt rackg (MPP) peratin fr P applicatins withut the need t stall large electrlytic capacitrs. herefre, the syste s reliability can be iprved. Unlike the cnventinal halfbridge MMC structures, the prpsed tplgy can blck dc and ac faults at put and utput sides respectively. he dular and scalable nature f the prpsed tplgy helps reducg the cst and crease the reliability the perspective f large-scale P applicatins [4]-[5]. Fig.. HF-islated cnverters C5, F5, G5, and P5 Fig.. Blck diagra f the prpsed cnverter

3 3 he paper eplas the basic peratin and prvides the atheatical analysis f the prpsed structure. Additinally, cparisns between the different pssible candidates ters f pwer lsses, vltage/current ripples, stresses, switch ratgs and ttal efficiencies are prvided. he practical feasibility f the prpsed structure is assessed with a scaleddwn 5 ka three-phase, k prttype usg fur dules fr each phase and cntrlled with MS30F8335 DSP.. SYSEM DESCRPON Fr all the selected cnverter candidates, the dulatin prciple is shwn Fig. 3 and can be described as fllws: (i) Durg perid t n, where S is n and S is ff, the ductrs energize while the capacitrs discharge. δ is the duty rati as t n δt s while t s is the switchg perid f the cnverter. (ii) Durg perid t ff, where S is ff and S is n, the ductrs de-energize while the capacitrs charge. t ff (-δ)t s. he duty rati value is cpared t a saw-tth carrier signal with frequency f s /t s. Hence, v can be epressed as: v N () Fig. 3. Mdulatin prciple fr the cnverter candidates he prpsed syste Fig. can perate tw different des f peratin. epla that, tw successive subdules (SMs) - and have been selected Fig. 4a where is an even nuber. n the first de (Mde ), the dules are fed fr different P arrays as shwn Fig.4b. he SMs utput vltages can be written as: v a s t + d c v a s( ) t + + d c v a s s( ) t + d c t + d c if - and dc- dc s the utput vltage is: v st (3) a n the secnd de f peratin (Mde ), shwn Fig.4c, the tw successive SMs are fed fr the sae P arrays and each SM perates fr nly half cycle withut addg the dc ffset. he equatins can be epressed as: v v a a S Carrier signal S tn tff st 0 t 0 t 0 0t s( t + ) t t s δ t t t (4a) (4b) Aga, if -, the utput vltage is: v st (5) a P - + P - - P + P - Fig. 4. Mdes f peratins: basic structure, Mde, and Mde f the utput vltage peaks are equal the tw des, the put P current ( pv ) will be dubled Mde. Hwever, the aiu vltage and current stresses acrss and thrugh the switches and the dides are equal the tw des. Due t the absence f dc vltages the SMs, it is epected that Mde will have lwer lsses and better efficiency than Mde. n this paper, Mde will be analyzed details and then a cparisn with Mde will be prvided. he utput vltages and currents can be epressed as: v s( t + ) (6a) i s( t + ) (6b) where represents phase a, b, r c and φ {0, -⅔π, ⅔π}. he duty rati f the SM nuber k phase can be calculated fr: vk k N k (7) vk k v + N k SM a - SM a shw the basic peratin f the three-phase syste, a MALAB/SMULNK del is built usg the cnditins and paraeters able fr the C5 cnverter. Because the syste is balanced and all SMs are identical, the first SM phase a has been shwn. Fig. 5a shws the siulatin results fr the first P array current pv with the put current f the first C5 SM phase a ( a). Because each tw successive SMs any phase are cnnected t the sae P array, the P arrays nuber is halved. Figs. 5b shws the vltage acrss the priary and secndary capacitrs ( cpa and csa) respectively. he utput vltages fr the first successive tw SMs phase a ( a and a) are shwn Fig. 5c. he threephase utput current f the syste is shwn Fig. 5d. a - + a - - a - a + v a - v a ωt ωt v a + - ωt

4 4 ABLE PARASC COMPONEN ALUES AND CRCU CONDONS Paraeter alue hree-phase utput vltage k Output pwer P MW Nuber f dules n 50 P array vltage 300DC urns rati N nput and utput ductrs L L H Priary and secndary sides capacitrs C p C s 0 µf Output capacitr C µf As shwn the results Fig. 5, the P arrays currents are cntuus and cnstant s MPP can be applied. he vltage and current stresses acrss the eleents and the seicnductr switches can be reduced by creasg the dules nuber and decreasg the P arrays vltages. and L( peak ) L( peak ) L L L Fig. 6. C5 (Ćuk) peratin durg ne saple perid t s (9) n practice, these factrs are usually selected as 0% f the peak current values. Siilarly, the capacitr f the SM can be epressed as: C t a s p (0a) cp t Cs N a s cs (0b) where cp and cs are the aiu allwable vltage ripple factr fr C p and C s currents respectively. c p( peak ) c s( peak ) cp and cs () Fig. 5. Siulatin results f the prpsed syste usg C5 SMs: pv and a, cpa and csa, a and a, and three-phase utput current. COMPARSONS BEWEEN CANDDAES his sectin discusses the paraeter selectin f the different cnverter candidates and prvides cparisns between the. he fur pssible candidates have differences regardg their put/utput ripples, passive eleents stresses and the transfrer cre size as stated earlier. Hwever, all candidates have the sae seicnductrs stresses (vltages and currents) at the sae peratg cnditins. A. Paraeters Selectin and Cparisn Assug shrt switchg perids (t s) fr C5 cnverter, the currents and vltages can be cnsidered lear as Fig. 6. Averagg the circuit f C5 SM alng the perids t n and t ff yields: at s L (8a) L L at s L. N L (8b) where L and L are the aiu allwable current ripple factr fr L and L currents respectively. he utput capacitance C is respnsible fr iprvg the tal Harnic Distrtin (HD) by prvidg additinal filterg t L and reduce the ripples the utput current and can be selected accrdg t: ts C where is the aiu utput current ripple: L( peak ) () ( peak ) (3) able lists the frulas fr selectg the paraeters f ther candidate cnverters. he passive eleents are usually selected t keep the currents and vltages f the passive eleents under 0% and t keep the HD f the utput current belw 5%. Als, the put current ripples shuld be kept lw as pssible t enable a prper peratin f the MPP cntrller and hence aiu pwer can be harvested fr the P arrays [6]. Figs. 7, 8 and 9 shw the siulatin results fr the prpsed three-phase syste with the ther SM candidates. Sce the three phases are identical and balanced, the currents and vltages f the first SM phase a are nly shwn. Fig. 0a shws a cparisn between the required capacitances fr different candidate SMs. Fig. 0b shws the ttal ductance required fr the different SMs. t is bvius that althugh the P5-based syste requires the highest capacitance values, it requires the lwest ductances. S, it is

5 5 cntrversy t terpret that as an dicatr fr SMs sizes. he aiu stred energy a SM can be calculated fr (4). ABLE PARASC COMPONEN FORMULAS SM type Eleent Frula Ripple factr C c ( peak ) c F5 G5 P5 L L C L C p C s L C a Nts c ( a ) t 4C L s a ( a ) t s N L ( a ) t s N at s L L a tsn cp ( a ) t s N cs L at s. N at s N L L ( peak ) L ( peak ) L ( peak ) L( peak ) L cp cp ( peak ) cs L cs ( peak ) L( peak ) ( peak ) L, C and C Sae as F5 Sae as F5 ( a ) t s L peak L LN L C p L 3 C s a tsn cp at sn ( ) cp cp ( peak ) L3 ( peak ) L3 L3 at s c p( peak ) cs cs Fig. 8. Siulatin results f the prpsed syste usg G5 SMs: and a, cpa and csa, a and a, and utput current pv (e) (f) Fig. 9. Siulatin results f the prpsed syste usg P5 SMs: and a, ca, cpa and csa, and La and L3a (e) a and a, and (f) three-phase utput current pv Fig. 7. Siulatin results f the prpsed syste usg F5 SMs: pv and a, ca, a and a, and three-phase utput current n Estred Lk Lk peak + Ck Ck peak k (4) able lists the aiu value f the stresses n each passive eleent. Fig. is generated by substitutg these aiu values (4) t shw the different estiated sizes f the different SMs. he C5 SM stres the lwest energy and therefre is epected t have the sallest size and vlue. Fig. 0. Passive eleents candidate SMs: Capacitance and ductance On the ther hand, F5 SM stres the highest energy and hence it will have the largest size. A further discussin abut the practicality, advantages and disadvantages f different SMs will be carried ut Sectin.

6 6 ABLE SRESSES ON PASSE ELEMENS SM type Eleent / Frula Maiu alue C5 F5 G5 P5 C p L C s v cp i L v cs in N L i L i C v c v L i in C v c L L / N + C v c v L i L i in C p v cp C s v cs 0 0 L i L i C v c v L i in C v C L i L in C p v cp 0 0 L 3 i L i C p v cs 0 0 C v c v where P P + P (5a) SM cnd s cnd D cnd P R + v S cnd n s rs c s avg P R + v D cnd F D rs F D avg (5b) where s_rs and D_rs are the rs currents thrugh S and D, currents s_avg and D_avg are the average currents, R n and R F are the n-state and frward resistances f S and D devices, v c, v F are the cllectr eitter and frward vltage drps f S and D respectively. Fr Fig., the rs currents can be calculated as: / / s rs s e 0 0 i dt i dt / N ( i ) dt (6) 0 N(3 + cs ) ( + cs ) / / D rs D e 0 0 i dt i ( ) dt / i ( ) ( ) dt (7) cs Siilarly, the average currents can be calculated as: / / i dt i dt s avg s e 0 0 / N ( i ) dt (8) 0 4 cs Fig.. tal Stred Energy Cparisn B. Seicnductrs pwer lsses By peratg Mde, stated earlier, the fur SM candidates have the sae current and vltage thrugh and acrss the. Devices S and D are cnductg current ne half cycle while they are ff the ther ne. Devices S and D are always ff and they are required nly Mde. he currents thrugh these devices are shwn Fig.. S D D S Fig.. Seicnductr devices currents Mde he devices cnductin pwer lss ne SM can be epressed as [7]: / / i dt i ( ) dt D avg D e 0 0 / i ( )( ) dt (9) 0 Assug balanced three-phase syste, the ttal devices cnductin pwer lss can be calculated fr: Psys cnd 3 n( Ps cnd + PD cnd ) (0) he switchg pwer can be estiated as [8] s avg PSM sw ( n + ff ) () where n and ff are the turn-n tie and turn-ff tie f the switch S. Siilarly, the ttal switchg pwer lsses the three-phase syste can be calculated fr: P C. nductrs pwer lsses 3 n P () sys sw SM sw he frulas describg the current thrugh the ductr f each candidate cnverter are listed able. Fr C5 as an

7 7 eaple, the current thrugh L can be epressed as: i N cs cs( t ) 0 t i L 0 t (3) N + ( + N )(3 + cs ) ( + cs ) s rs + + (8) f r is the ternal resistance f L, the pwer lss can be estiated fr: PL i L rs r ( + cs ) r (4) 6 Siilarly, the current L is: i 0 t il (5) 0 t And the pwer lss L : PL i L rs r r (6) 4 Fr ductr currents with frula f, as i L F5, the pwer lss and rs current can be epressed as: i Fig. 4. Eperiental setup cs cs P i r r L L rs ( ) 8N 6N 4 N (7) he ductrs lsses any cnverter can be estiated fr (4), (6), and (7) as all SM currents are fllwg these three frulas, see able. Fig. 3a shws the pwer lsses plts fr the different SMs while Fig. 3b shws the ttal efficiency f the SMs accrdg t the previus analysis. Fig. 3. Pwer lsses switches and ductrs and ttal efficiency. EXPERMENAL RESULS FOR MODE shw the peratin f the prpsed structure, a scaleddwn 5 ka three-phase, k prttype is built with fur dules and cntrlled with MS30F8335 DSP. he eperiental setup is shwn Fig. 4. he SMs are built with changeable terals t enable testg different cnverter candidates usg the sae cnfiguratin. able shws the circuit paraeters fr the setup. Figs. 5 t 8 shw the results f the prpsed three-phase syste under an pen-lp peratin and cnsiderg the sall isatches between the different passive eleents each SM. he results can be cpared t the cputer siulatins sectin.. A COMPARSON BEWEEN MODE AND MODE Eag Mde a siilar way, the devices currents can be shwn as Fig. 9. Fr S and D (the put side devices), each device is cnductg ne half cycle perid. Fr S, the rs current s_rs can be calculated fr: Fig. 5. Eperiental results f the C5-based syste: put currents fr the SMa and SMa, iddle capacitrs vltages f SMa, utput vltages f SMa and SMa, and utput three-phase currents Fig. 6. Eperiental results f the F5-based syste: put currents fr the SMa and SMa, put capacitr (C ) vltage and secndary ductr current (L ) f SMa, utput vltages f SMa and SMa, and utput three-phase currents he rs value fr the dide current D can be calculated fr:

8 8 ( N + ) ( + N )(3 + cs ) ( + cs ) ABLE CRCU PARAMEERS OF EXPERMENAL SEUP Paraeter alue D rs + R.M.S utput vltage k Output pwer P 3 kw Nuber f dules n 4 nput DC vltage 00DC urns rati N 3 Switchg frequency 5 khz Seicnductr switch (GB) RG4PC50FPbF (600, 70A) Dide FFSH400ADN (00, 40A) Output lad 500 Ω (9) Fig. 8. Eperiental results f the P5-based syste: put currents fr the SMa and SMa, iddle capacitrs vltages f SMa, utput vltages f SMa and SMa, and utput three-phase currents Fig. 7. Eperiental results f the G5-based syste: put currents fr the SMa and SMa, iddle capacitrs vltages f SMa, utput vltages f SMa and SMa, and utput three-phase currents he average values f s and D can be epressed as: cs 4 + s avg ( ) (30) 8 cs dc D avg ( + ) (3) 8 Siilarly, the rs and average values f the utput side devices (S and D ) can be calculated fr: s rs D rs N + dc (3 + cs ) + 4N N (3) N + dc (3+ cs ) 4N N (33) cs s avg D avg (34) he ttal seicnductr cnductin lsses can be calculated fr: P P + P + P + P (35) SM cnd s cnd D cnd s cnd D cnd P R + v S cnd n s rs c s avg P R + v D cnd F D rs F D avg P R + v S cnd n s rs c s avg P R + v D cnd F D rs F D avg S D S D Fig. 9. Seicnductr devices currents Mde he currents thrugh different ductrs have three different frulas as listed able. he three frulas are: (i) il in, (ii) i L i and (iii) i i L3. he rs values fr these frulas can be epressed as: dc ( + cs ) i L_ rs + (36a) 3 ( N + dc ) ( + cs ) L_ rs N 3N i + (36b) i L3_ rs (36c) Because the syste is balanced and identical, the ttal pwer lsses the ductrs can be calculated by ultiplyg the pwer lsses the subdule by 3n. Cparg the devices and ductr pwer lsses, it can be deduced that the pwer lsses f the subdules peratg Mde are higher when cpared with Mde. he eperiental cparisn f the syste under the tw des is shwn Fig. 0. he lsses breakdwn f each cnverter are shwn Fig.. On the ther hand, the put dule current is halved Mde and therefre it ay be desirable when it is required t reduce the dc current f the P arrays. he selectin prcess f the st suitable cnverter candidate depends n the syste cnditins as well as its desired perfrance. he syste s perfrance can be easured by fur a aspects: (i) ttal efficiency, (ii) syste s reliability (iii) ttal size, and (iv) nuber f passive eleent.

9 arrays and the basic ethdlgy fr the MPP cntrller. Assug that the syste is peratg Mde and cnnected t the grid via three-phase les f per-phase ipedance z r+x L, the utput currents can be epressed as: 9 Fig. 0. tal efficiencies f the different candidates Mde and Mde Fig.. Lsses breakdwn: C5, G5, P5, and F5 he ttal efficiency can be easured fr the ttal lsses f each candidate while the reliability f the syste is directly prprtinal with reducg the aiu stresses f the seicnductr devices as well as the electrlytic capacitrs the syste. he ttal size f the syste can be sensed by calculatg the stred energy side the passive eleents. Fr the previus analyses and results, the selectin prcess will depend n the nal put vltage fr the P arrays as well as the nuber f the dules. Fr the syste able as an eaple, the P arrays at the put side are cnnected t prvide a nal vltage f 300 t the terals f each f the 50 dules. Fr the efficiency analysis Fig. 3b, it can be deduced that the best candidate ters f the ttal efficiency is F5, fllwed by C5, G5 and fally P5. Cnsiderg the reliability f the different candidates the secnd place, it can be fund that the ttal required capacitances as well as the aiu stresses f the seicnductr devices are very siilar at 300 put vltage, see Fig. 0. hen, it can be seen fr Fig. that F5 has the largest size fllwed by G5, C5 and then P5. Hwever, P5 cnverter has the highest nuber f passive eleents, fllwed by C5, G5 and then F5. Fr these reasns, it can be deduced that C5 cnverter is the best cprise at the decided cnditins and criteria. Hwever, this chice will be different if the nal arrays vltages have been changed r the design pririties are different. Fr eaple, if the size is nt an iprtant criterin fr the designer.. PERFORMANCE OF HE PROPOSED OPOLOGY DURNG PARAL SHADNG his sectin describes the general perfrance fr the prpsed syste s peratin durg partial shadg f P n / + s( t + + ) g s( t + ) i () t r + X s( t + ) L (37) where g,, are the peak values f the ac grid vltage, subdules ac utput vltage, and syste utput current respectively. θ and γ are the phase-shift angles f subdule ac vltages and the utput currents respectively while represents phase a, b, r c and φ {0, -⅔π, ⅔π}. Neglectg the pwer lss the cable resistances, the ttal utput pwer f the syste is calculated fr: P ttal 3n cs( ) 3 cs( ) g (38) 4 n nral peratin, the unshaded dules pwer can be epresses as: P 3 cs( ) (39) 4 d_ u he syste reference vltages and currents are calculated fr slvg equatins (37), (38) and (39), hence the syste can track the aiu pwer pt. Fig.. _ and P_ characteristics f the P arrays: unshaded, shaded Fig. a shws the and P characteristics f the unshaded P arrays durg nral cnditins. Durg partial shadg, the reference values f the grid current and dules utput vltages can be adusted t harvest the aiu available pwer fr the syste. epla that briefly, a case where k dules f the syste are shaded while ther dules (n-k) are unshaded. Fig. b shws the and P characteristics f the shaded P arrays. t shuld be nted that the characteristics f the P arrays change with their type, nuber f series/parallel cells side each array. Hwever, there will always be glbal and lcal peaks as shwn Fig. b. n this case, the new utput currents can be calculated as: k / _ sh + _ sh s( t + sh + ) + ( n k) / + s( t + + ) g s( t + ) i () t r + X s( t + ) L (40) where _sh is the peak value f the shaded subdule utput vltage, ` is the new peak value f the utput currents, and θ sh is the phase angle f the shaded dules ac vltages. he shaded dules pwer can be calculated fr:

10 0 P 3 cs( ) _ sh sh d_ sh _ sh _ sh (4) he new ttal syste pwer can be calculated fr: 3( n k) cs( ) + 3k cs( ) 3 cs( ) _ sh sh g ttal (4) P 4 4 he syste new reference vltages and currents are calculated fr slvg equatins (40), (4) and (4) rder t track the aiu available pwer pts fr unshaded and shaded dules. (e) Fig. 3. Eperiental results fr C5 syste Mde durg partial shadg: put vltage and current f Mdule (unshaded), put vltage and current f Mdule (shaded), Mdule utput vltages, Mdule utput vltages, and (e) utput three-phase currents Fig. 3 shws the eperiental results f C5-based threephase verter, peratg Mde, t iic the case when tw f the fur dules are shaded at a shadg tie (t sh). n the nral unshaded cnditin, the syste is cnnected t the grid and generates 3 kw evenly shared by the fur dules per phase. S, each SM generates 50W and each three-phase dule generates 750W. he peak f the three-phase vltage at the pt f cn cuplg is g 3 while the put vltage is 00. At the shadg cnditins, the generated pwer f the lwer tw dules drps t 5%. Figs 3a and 3b shw the put currents and vltages dule and dule 3. Fig 3c and d shw the utput vltages f dule and dule 3. he syste s utput three-phase current is shwn Fig. 3e. n this case, the cntrller changed the reference values f the dules vltages, and hence the utput currents, rder t keep the tw unshaded dules unchanged and deliver the aiu available pwer fr the ther tw shaded dules.. DSCUSSON Accrdg t the afreentined theretical analysis, cputer siulatins and eperiental results, the fllwg pts can be deduced: he devices f the SMs are peratg nly ne half cycle Mde and therefre the seicnductr and cpper lsses are lwer when cpared with Mde. Hwever, the put P array currents are dubled Mde which requires re P arrays t be cnnected parallel at the put side. he ttal capacitance required the SMs creases significantly when the put vltage (P arrays vltage) decreases. satisfy the sae vltage/current ripples requireents, P5 SM shuld have the highest capacitance values while the C5 SM shuld have the lwest. On the ther hand, the ttal ductance required the SMs creases with the put dc vltage. C5 SM has the highest ductance value while the P5 dule has the lwest. Cnsiderg the energy the SMs, P5 stres the lwest aunt side the transfrer cre and passive eleents and hence the transfrer cre will have the sallest vlue. F5 SM has the highest stred energy while C5 and G5 are clse t each ther. Althugh the P5 SM has the sallest vlue, it requires re passive eleents than the ther dules, especially F5. S, there is a trade-ff between the nuber f eleents and the ttal SM size. P5 SM has tw priary and secndary side capacitrs (C p and C s) havg alst zer average vltage, see Fig. 9 and able. Cnsequently, these capacitrs can be very sall and cheap when cpared with the C5 and G5 SMs. he vltages, currents and switchg pattern f the seicnductr devices are the sae fr all SMs. Fr this reasn, the switchg and cnductg lsses are the sae fr each Mde f peratin. he C5-based syste has the best efficiency when the put vltage is derate, see Fig. 3 and Fig. 0. Hwever, when the put vltage creases F5-based syste ffers the best efficiency. Generally, all candidates have an ptiu pt versus the put vltage and SMs nuber. After this pt, the efficiency f the syste decreases. he ttal pwer lsses crease significantly when the put dc vltage and the SMs nuber are lw. his ccurs because the devices and the ductrs currents bece very high. he best suitable cnverter depends n the put P arrays vltages as well as the nuber f dules. t can be sensed fr the previus analyses and results that C5 is the best chice when the put vltage is lw while F5 is better when the put vltage creases t very high liits. Althugh the theretical analysis illustrates that F5-based syste has the best efficiency at higher put vltages, it necessitates fr a bigger transfrer cre with re cre lsses practice. Hwever, these transfrer cre lsses are lw when cpared with the seicnductr and ductr lsses. Because Mde has balanced vltage and current wavefrs, it is easier t be cntrlled with the classical dq frae cntrllers [9].

11 . CONCLUSON his paper presents a new dular energy cnversin syste fr ediu-vltage P applicatins. he prpsed syste has tw different des f peratins. Different fur candidates, able t be islated with high-frequency transfrer cres, were prpsed and analyzed ters f vltage/current ripples, sizes, vlues, and pwer lsses. he prpsed syste ffers the required dularity and enables cst and size reductin. he prpsed syste is able t perate under partial shadg f se r all f the put P arrays by changg the SMs duty ratis if the cntrller has the fratin abut the P arrays characteristics advance. he cntrller design and the apprpriate MPP syste are yet t be cnsidered further future publicatins. [5] H. Liu, K. Ma, and F. Blaaberg, Device ladg and efficiency f dular ultilevel cnverter under varius dulatin strategies, Prc. 7th EEE nt. Syp. Pwer Electrn. Distrib. Gener. Syst., Jun. 06, pp. 7. [6] A. H. El Khateb, N. A. Rahi, J. Selvara and B. W. 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Khadkikar, Dynaic delg and cntrl f terleaved flyback dule-tegrated cnverter fr P pwer applicatins, EEE rans. nd. Electrn., vl. 6, n. 3, pp , Mar. 04 [9] A. Darwish, A. M. Massud, D. Hlliday, S. Ahed and B. W. Willias, "Sgle-Stage three-phase differential-de buck-bst verters with cntuus put current fr P Applicatins," EEE ransactins n Pwer Electrnics, vl. 3, n., pp , Dec. 06. [0] A. Darwish Badawy, " Current surce dc-dc and dc-ac cnverters with cntuus energy flw," Degree f Dctr f Philsphy, Departent f Electrnics and Electrical Engeerg, University f Strathclyde, Glasgw, 05. [] B. W. Willias, Generatin and analysis f cannical switchg Cell DC t-dc cnverters, EEE rans. nd. Electrn., vl. 6, n., pp , Jan. 03. [] J. Knight, S. Shirsavar, and W. Hlderbau, An iprved reliability Cuk based slar verter with slidg de cn-trl, EEE rans. Pwer Electrn., vl., n. 4, pp. 07 5, Jul [3] A. Darwish, A. Elserugi, A. Abdel-Khalik, S. Ahed, A. Massud, D. Hlliday, and B. Willias, A sgle-stage three-phase DC/AC verter based n Cuk cnverter fr P applicatin, GCC Cnference and Ehibitin (GCC), 03 7th EEE, 03, pp [4] H. Akagi, Classificatin, terlgy, and applicatin f the dular ultilevel cascade cnverter (MMCC), EEE rans. Pwer Electrn., vl. 6, n., pp , Nv. 0. Ahed Darwish received the B.Sc. and M.Sc. degrees electrical engeerg fr the Faculty f Engeerg, Aleandria University, Egypt, 008 and 0, respectively, and the Ph.D degree electrical engeerg fr Electric and Electrnic Engeerg Departent at the University f Strathclyde, Glasgw, U.K., 05. Fr 009 t 0, he was a Research Assistant at eas A&M University at Qatar. Fr 05, he was with PEDEC grup at the University f Strathclyde as a Pstdctral Research Assciate fr tw years. He has ed Lancaster University as a Lecturer Electrical Engieerg 08. His research terests clude dc-dc cnverters, ultilevel cnverters, electric aches, digital cntrl f pwer electrnic systes, energy cnversin, renewable energy, and pwer quality. Mhaed A. Elgenedy (S 5-M 7) received the B.Sc. (with first-class hnrs) and M.Sc. degrees Electrical Engeerg fr Aleandria University, Egypt 007 and 00 respectively, and the Ph.D. degree electrical engeerg fr Electric and Electrnic Engeerg Departent at the University f Strathclyde, Glasgw, U.K., 08. He is currently a Pstdctral Research Assciate with PEDEC grup at Strathclyde University, Glasgw, U.K. He is als an assistant lecturer with the Electrical Engeerg Departent, Faculty f Engeerg, Aleandria University. Fr 0 t 03, he was with Spiretrnic LLC, Hustn, X, USA, as a Research Engeer. Fr 03 t 04, he was a Research Assciate at eas A&M University at Qatar, Dha, Qatar. His research terests clude high pwer electrnics, pulse pwer generatr, electric ache drives, energy cnversin, electric vehicles and renewable energy.