Current-Sourced Buck Converter

Transcription

1 urrent-surced Buck nverter Jari eppäah, Matti Karppanen and Teuv Sunti Abstract Slar and magnetic energy harvestg may benefit frm the use f current-surced cnverters fr terfacg thse surces t the practical usage due t their current-surce nature. The paper vestigates the implementat and dynamics f such cnverters by means f a current-surced buck cnverter. Duality cncepts are applied t bta the cnverter frm the crrespndg vltage-surced buck cnverter. The dynamic analysis is carried ut cntuus capacitr-vltagemde under direct-duty-rati cntrl. The theretical fdgs are verified by extractg the transfer functs frm the Matlab -Simulk-based switchg mdels. Index Terms urrent transfrmer, buck cnverter, dynamics T I. INTRODUTION HE vltage-put r surced cnverters are the basic media fr transferrg energy frm a surce t anther due t the dmatg nature f the vltage surces as energy supplies []-[5]. Inherently thse cnverters are usually vltage surces, which can be cnverted t current surces by prvidg feedback frm the utput current [],[],[6] r by usg current-mde cntrl at pen lp [7],[8]. It shall be, hwever, nticed that the utput-vltage feedback changes the current-mde-cntrlled cnverters back t vltage surces at clsed lp. Smetimes the vltage-surced cnverters are errneusly named as current-surced cnverters as [9]. There are energy surces such as slar cells r arrays [0]- [3] and supercnductive magnetic energy strage (SMES) systems [4],[5], which have current-surce nature. Mst ften the terfacg cnverters used t cnnect the slar arrays t the rest f the pwer system are cnvental vltage-surced cnverters [],[3] requirg a sufficiently large capacitr t be cnnected at the put f the cnverter. The cnverters used t terface SMES systems are usually current-surced cnverters as discussed [4],[5]. Als the slar-array terfacg may benefit frm the use f real current-surced cnverters. The paper vestigates the implementat f the currentsurced cnverters and the dynamics related t them. Duality cncepts can be applied t cnstruct the pwer stages frm the crrespndg vltage-surced cnverters as described detail [6]-[9]. Direct-duty-rati cntrl is the basic cntrllg mde f current-surced cnverters similarly t vltage-surced cnverters [4],[5]. Therefre, the basic dynamics f the cnverter can be fund applyg the methd knwn as state space averagg (SSA) described detail [5] and [0]. urrent-surced buck cnverter is used as an example. The theretical predicts are validated extractg the frequency respnses frm the Matlab -Simulk-based switchg mdels. The rest f the paper is rganized as fllws: The duality transfrmat methds are trduced and applied t a bucktype cnverter Sect II. The general dynamic descript f the current-surced cnverter as well as its average and small-signal mdelg are trduced Sect III. The pwer-stage design issues and the dynamics extracted frm the switchg mdel are presented Sect IV. The cncluss are drawn Sect V. II. DUAITY TRANSFORMATION METHODS A. Duality Transfrmat Prciples The duality cncept is well knwn circuit thery [6] and applied already late 970s t cnstruct current-surced cnverters frm the crrespndg vltage-surced cnverters [7]. The applicat f duality transfrmat t the basic circuit elements such as vltage and current surces, ductrs, capacitrs, pen and clsed switches usually cnstitutg the different tplgies prduces the duals as shwn Fig., D where x dentes the duality peratr. J. eppäah is with the Electrical Energy Engeerg Department, Tampere University f Technlgy, Tampere, FI-3300 Fland ( jari.leppaah (at) tut.fi). M. Karppanen is with the Electrical Energy Engeerg Department, Tampere University f Technlgy, Tampere, FI-3300 Fland ( matti.karppanen (at) tut.fi). T. Sunti is with the Electrical Engeerg Department, Tampere University f Technlgy, Tampere, FI-3300 Fland (crrespndg authr, teuv.sunti (at) tut.fi). Fig.. Element-wise duality transfrms. NORPIE/008, Nrdic Wrkshp n Pwer and Industrial Electrnics, June 9-, 008

2 Different electric circuits can be presented by usg graphs, where each arc represents a certa circuit element the selected tplgy. In this case, the vltage-put circuit is naturally the base frm which the first graph will be cnstructed. The dual f the graph can be cnstructed such a way that the arcs cnnected series the rigal graph will be cnnected parallel the dual f the graph and the parallel cnnected arcs series, respectively. The crrespndg current-put circuit will be btaed frm the graph by cnnectg the duals f the elements (Fig. ) as the graph dictates. These prcedures are illustrated Fig. based n a simple -filter circuit. Applyg the methds described abve Subsect A, the graph f the vltage-put buck cnverter Fig. 3b can be transfrmed t its dual as shwn Fig. 4a. The arcs f the dual f the graph determe the elements and their cnnects and thus the tplgy f the current-put buck cnverter as shwn Fig. 4b. Fig. 4. urrent-put buck cnverter: a) Graph and b) Schematics. Fig.. -filter: a) Vltage-put schematics, b) Its graph, c) The dual f the graph and d) urrent-put schematics. III. DYNAMI REPRESENTATIONS The dynamics f the vltage-put-vltage-utput cnverter can be represented by means f a lear tw-prt netwrk with G-parameters (Fig. 5) [],[3],[0], which cnstitute the set f transfer functs given by B. urrent-input Buck nverter A cnvental vltage-put buck cnverter with synchrnus rectificat is shwn Fig. 3a. The crrespndg graph, where S dentes the high-side MOSFET and S ff the lw-side MOSFET, is shwn Fig. 3b. n where [ ] u i Y Ti Gci i = u G i Z G c c T () î u dentes the utput vectr and u i c the put vectr (See Fig. 3a). The general cntrl variable is dented by ĉ. The transfer functs () represent the pure ternal dynamics, where the lad and surce effects are elimated. T Fig. 3. Vltage-put buck cnverter: a) Schematics and b) Graph. Fig. 5. ear tw-prt netwrk with G-parameters.

3 3 The dynamics f the current-put-current-utput cnverter can be represented by means f a lear tw-prt netwrk with H-parameters [0] (Fig. 6), which cnstitutes the set f transfer functs given by lw-side MOSFET cnducts and the crrespndg tplgical circuit structure is shwn Fig. 8b, respectively. i u Z Ti Gci u i = Gi Y G () c c T where u i dentes the utput vectr and i T u c dentes the put vectr (See Fig. 4b). The general cntrl variable is dented by ĉ. Similarly t the vltage-put cnverter, the transfer functs () represent the ternal dynamics f the current-put cnverter. Fig. 7. urrent-put synchrnus buck cnverter. Fig. 6. ear tw-prt netwrk with H-parameters. A. Average and Small-Signal Mdelg The average and small-signal mdelg f a current-put cnverter can be dne similarly t the vltage-put cnverter by applyg state-space-averagg (SSA) technique trduced detail [5] and []. We cnsider the cnverter t perate cntuus cnduct mde (M), which means that the capacitr vltages are cntuus similarly t the ductr currents the vltage-put cnverters. The state variables f the system are the time-averaged values f the capacitr vltages and ductr currents []. In rder t cnstruct the averaged state space, we have t slve the derivatives f the capacitr vltages and ductr currents durg the n and ff times. The averagg is carried ut by multiply the n-time equats with the duty rati d and the ff-time equats with the cmplement f the duty rati d and summg them tgether. Similar prcedures are applied t the utput variables ( u and i ) fr btag the utput equats. The small-signal state space can be btaed frm the averaged state space by develpg the prper partial derivatives, i.e., by learizg the averaged state space []. The pen-lp current-put buck cnverter with the relevant parasitic elements is shwn Fig. 7. Durg the n time, the high-side MOSFET cnducts and the crrespndg tplgical circuit is shwn Fig. 8a. Durg the ff time, the Fig. 8. urrent-put buck cnverter durg the a) n time and b) ff time. Applyg the abve described prcedures and Kirchhff s vltage and current laws, the averaged state space can be given by du d = i i dt di r r dr = u i i u dt u = d u dr i ( drds dr ds dr ) i i = i The steady-state peratg pt can be slved frm (3) by lettg the derivatives t be zer. These prcedures yield I = DI U = U Dr I U DU D r DDr Dr Dr I = ( ds ds) The small-signal state space can be slved frm (3) by develpg the prper partial derivatives, which yields (3) (4)

4 4 where du D I = i i d dt di r r Dr ri = u i i u d dt u = Du Dr i ri Ud i = i U = U ( Dr Dr r r ) I r = Dr Dr Dr ds ds ds ds A small-signal tw-prt mdel similar t the cannical equivalent circuit prvided [5] can be cnstructed frm the small-signal state space (5) as shwn Fig. 9. The parameters es ( ), ( js ) and r e can be given by I es ( ) = U ( Dr ( Dr ) rds rds) I js () = D (6) r = Dr Dr DDr e ds ds (5) the crrespndg vltage-put cnverter cnstitutg the G- parameter set () as fllws (): Y Ti Gi Z = Ds D( sr) D( sr ) ( r Drds Dr ds s)( sr ) (8) r Drds Dr ds r s s DU ( ( rds rds ) I ) s Gci ( U ( rds rds ) I )( sr ) = I G c r Drds Dr ds r 0 s s The small-signal equivalent circuit [5] fr the vltage-put buck cnverter can be given as shwn Fig. 0, where the parameters es ( ), ( js ) and r e can be given by U ( rds rds) I es ( ) = js () = I D r = r Dr Dr e ds ds (9) Fig. 9. Small-signal equivalent circuit f the current-put buck cnverter. The transfer functs cnstitutg the H-parameters () can be slved frm (5) aplace dma by utilizg the cnvental matrix manipulat methds. These prcedures yield the pen-lp transfer functs as fllws: Z Ti Gi Y = D (( s r) r r) D( sr) D( sr ) s r 0 r r 0 0 (7) s s DI (( s r ) r r ) G ci I ( sr ) U G = r r c 0 s s Fr cmparisn, we give the pen-lp transfer functs f Fig. 0. Small-signal equivalent circuit f the vltage-put buck cnverter. The small-signal equivalent circuits shwn Figs. 9 and 0 ffer excellent physical sight t the ternal dynamics f the cnverters and thereby, reveal explicitly the similarities and differences they have terms f ternal dynamics. IV. PRATIA DESIGN AND DYNAMI ISSUES The ductrs a vltage-put cnverter are typically chsen allwg a certa peak-t-peak ripple current t appear an ductr, which is the rder f 0-40 % f their average current. The utput capacitr is chsen such that the utput-vltage dip will be less than a certa value, when the utput current is changed step-wisely fr a certa amunt. Similar methds can be als applied the case f the currentput cnverter but the ripple defit will be applied t the capacitrs and the transient specificats t bta the value f the utput ductr, respectively.

5 5 The ripple vltage f the capacitr is triangular shaped, because it is charged and discharged by means f effectively cnstant currents. The up slpe f the vltage ( m ) can be i i given by and the dwn slpe ( m ) by i. This means that the peak-t-peak ripple vltage can be given by DTs ( I I ) Δ u pp = (0) and the average slpe f the capacitr vltage by du Di i = () dt The value f the capacitr ( ) can be naturally slved accrdg t (0), when the ripple value is specified. The utput-vltage step change ( Δ U ) causes D vltage t appear ver the ductr fr a time Δ t = Δ U /( d u / dt). The resultg vlt-secnds Δ λ = Δt Δ U / wuld cause an undersht r versht the utput current, which can be given by Δ i =Δ λ / () Fig.. a) Ma simulat set-up and b) PWM-blck mdel. The value f the utput ductr ( ) can be naturally slved accrdg t (), when the transient specificats are given. A. ircuit Element Select The design f the cnverter will be carried ut by usg the fllwg specificats: I = - A, U = 3-5 V, I = 0.5 A and f s = 00 khz. The allwed capacitr-vltage peak-t-peak ripple is 0 % f the nmal value and the utput-current dip 0 % f the nmal value, respectively. These specificats yield 0 μf (Eq. (0)) and 500 μh (Eq. ()). The circuit parasitic elements are taken as fllws: r = 0. Ω, r = 30 mω and rds = rds = 0. Ω. The simulats have been carried ut by usg Matlab Simulk Tlbx, where the switchg mdels are cnstructed by means f the n and ff-time state spaces (Fig. 8), which are implicitly bservable als (5): Fig. a shws the ma simulat set-up and Fig. b the PWM-mdulatr blck. Fig. shws the pwer-stage mdels. The simulated capacitr vltage and utput current are shwn Figs. 3 and 4. The capacitr-vltage wavefrms resemble the ductr-current wavefrms typically bserved a vltage-put cnverter and the utput-current wavefrms the utput-capacitr wavefrms, respectively. These phenmena are expected due t the applied duality transfrmats, when cnstructg the current-put cnverter. Fig.. Pwer-stage simulat mdels: a) Ma set-up, b) Inductr-current blck and c) apacitr-vltage blck.

6 6 B. Dynamic Evaluat The dynamic evaluat f the predicted transfer functs (7) is basically dne such a way that a sus signal is jected n the tp f the rigal put signal t the prt servg as the excitat put and the crrespndg respnd is recrded frm the prt servg as the respnse utput. The sgle-frequency value f the impulse respnse is cmputed based n the respnse and ject data applyg Fast Furier Transfrmat (FFT) methd. A Matlab script is cnstructed t execute the required FFT prcedures. The frequency range f terest is scanned with an apprpriate number f jects. The cntrl-t-utput transfer funct ( G c ), put-t-utput transfer funct ( Gi ) and the utput admittance ( Y ) are subjected fr the evaluat. Similarly t the VM-cntrlled vltage-put cnverter peratg M, the VM-cntrlled current-put cnverter wuld exhibit resnant behavir havg resnant frequency at.5 khz. ntrl-t-output The frequency respnses f the cntrl-t-utput transfer funct ( G c ) are shwn Fig. 5 at the put current f A and A, respectively. The respnses resemble the crrespndg respnses f the vltage-put cnverter. The dts dente the switchg-mdel-based (Figs. and ) respnses, which ccide exactly with the predicted respnses (7). Fig. 5. ntrl-t-utput transfer functs at the put current f A (dashed le) and A (slid le). Input-t-Output Fig. 3. apacitr-vltage wavefrms at the put current f A and A. The frequency respnses f the put-t-utput transfer funct ( Gi ) are shwn Fig. 6 at the put current f A and A. The respnses resemble the respnses f the crrespndg vltage-put cnverter. The dts dente the switchg-mdel-based respnses ccidg exactly with the predicted respnses (7). Fig. 4. Output-current wavefrms at the put current f A and A. Fig. 6. Input-t-utput transfer funct at the put current f A (dashed le) and A (slid le).

7 7 Output Admittance The frequency respnse f the utput admittance is shwn Fig. 7, where the dts dente the switchg-mdel-based respnses. The shape f the respnse crrespnds t the put admittance f the vltage-put cnverter nt the utput impedance. Fig. 7. Output admittance. V. ONUSIONS The paper vestigated the implementat and dynamic mdelg f current-put cnverters. Buck-type cnverter was used as an example. It was shwn that the duality prciples and graph technique can be used t bta the pwer stage f the current-put cnverter frm the crrespndg vltage-put cnverter. The dynamic mdels f the direct-duty-rati cntrl can be btaed by applyg stage-space averagg yieldg accurate mdels up t the half the switchg frequency. The btaed frequency respnses resemble the respnses f the vltage-put cnverter. The practical prblems with the current-put cnverters wuld be related t the auxiliary-pwer generat. [7]. W. Deisch, Simple switchg cntrl methd changes pwer cnverter t a current surce, Prc. IEEE PES 78, 978, pp [8] T. Sunti and M. Karppanen, Methds t characterize pen-lp dynamics f current-mde-cntrlled cnverters, Prc. IEEE PES 08, 008 ( press). [9] W. W. Weaver and P. T. Kre, Analysis and applicat f a currentsurced buck cnverter, Prc. IEEE APE 07, 007, pp [0] S. iu and R. A. Dugal, Dynamic multiphysics mdel fr slar array, IEEE Trans. n Energy nvers, vl. 7, n., June 00, pp [] D. Sera, R. Tederescu and P. Rdriguez, PV panel mdel based n data sheet values, Prc. IEEE ISIE 07, 007, pp [] W. Xia, W. G. Dunfrd, P. R. Palmer and A. apel, Regulat f phtvltaic vltage, IEEE Trans. n Industrial Electrnics, vl. 54, n. 3, June 007, pp [3] W. Xia, N. Ozg and W. G. Dunfrd, Tplgy study f phtvltaic terface fr maximum pwer pt trackg, IEEE Trans. n Industrial Electrnics, vl. 54, n. 3, June 007, pp [4] R. W. Bm and H. A. Petersn, Supercnductive energy strage fr pwer systems, IEEE Trans. n Magnetics, vl. MAG-8, n. 3, September 97, pp [5] D. Shmilvitz and S. Sger, A switched mde cnverter suitable fr supercnductive magnetic energy strage (SMES) systems, Prc. IEEE APE 0, 00, pp [6]. A. Deser and E. S. Kuh, Basic ircuit Thery, McGraw-Hill: New Yrk, NY, USA, 969. [7] S. uk, General tplgical prperties f switchg structures, Prc. IEEE PES 79, 979, pp [8] D. Shmilvitz, Applicat f duality fr derivat f current cnverter tplgies, HIT Jurnal f Science and Engeerg B, vl., ns. 3-4, pp [9] R. Rabvici and B. Z. Kaplan, Nvel D-D cnverter schemes btaed thrugh duality prciple and tplgical cnsiderats, IEE Electrnics etters, vl. 7, n., Octber 99, pp [0]. K. Tse, ear ircuit Analysis, Addisn Wesley ngman, Harlw, England, 998. [] T. Sunti, Unified average and small-signal mdelg f direct-n-time cntrl, IEEE Trans. n Industrial Electrnics, vl. 53, n., February 006, pp REFERENES [] Y. Huang and. K. Tse, ircuit theretic classificat f parallel cnnected cnverters D-D cnverters, IEEE Trans. n ircuits and Systems -I: Regular Papers, vl. 54, n. 5, May 007, pp [] T. Rila, M. Hankaniemi, T. Sunti, M. Sippla and M. Vilkk, Dynamical prfile f a switched-mde cnverter Reality r imagat, Prc. IEEE INTEE 07, 007, pp [3] T. Sunti, M. Hankaniemi and M. Karppanen, Analysg the dynamics f regulated cnverters, IEE Prc. Electric Pwer Applicats, vl. 53, n. 6, Nvember 006, pp [4] G. W. Wester and R. D. Middlebrk, w-frequency characterizat f switched-dc-dc cnverters, IEEE Trans. n Aerspace and Electrnic Systems, vl. AES-9, n. 3, May 973, pp [5] R. D. Middlebrk and S. uk, A general unified apprach t mdelg switchg-cnverter pwer stages, Int. Jurnal f Electrnics, vl. 4, n. 6, 977, pp [6] M. Hankaniemi and T. Sunti, Dynamical mdelg and cntrl f current-utput cnverters, Internatal Review f Electrical Engeerg, vl. 4, n. 5, September-Octber 007, pp