Multiple Sets of Pulse Adjustment Control Technique Based on Input Voltage Feed-forward Compensation for DC-DC Converters Ming Qina, Jingchao Lib

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1 5th Internatal Cnference n Envirnment, Materials, Chemistry and wer Electrnics (EMCE 016) Multiple Sets f ulse Adustment Cntrl Technique Based n Input ltage Feed-frward Cmpensat fr DC-DC Cnverters Mg Qa, Jgcha ib Schl f Electrical Engeerg, Zhengzhu University, Zhengzhu , Cha; a qmg@zzu.edu.cn, b @163.cm Keywrds: put ltage feed-frward, pulse adustment, DC-DC cnverters. Abstract. In rder t crease the applicable put ltage scpe f ulse Adustment (A) cntrlled cnverter, a new cntrl technique fr DC-DC cnverters, Multiple Sets f ulse Adustment Based n Input ltage Feed-frward Cmpensat (IF-MSA), is prpsed this paper. By trducg put ltage feed-frward cmpensat, at the begng f each switchg perid IF-MSA cntrller senses the put ltage f the DC-DC cnverter and selects ne amng multiple sets f cntrl pulses. Each set f cntrl pulses is cmpsed f high-pwer pulse and lw-pwer pulse. The high-pwer pulse r lw-pwer pulse is selected t drive the pwer switch by sensg the utput ltage f the DC-DC cnverter at the begng f each switchg perid. The prciple and peratal prcess f IF-MSA cntrl technique are trduced the paper. The cntrl regulat and steady-state perfrmance f IF-MSA cntrlled Bst cnverter peratg discntuus cnduct mde ( DCM ) are studied. The prprts f IF-MSA and A cntrl pulses as the funct f put ltage with ne repetit cycle are analyzed. Simulat and experimental results are presented t verify the feasibility and advantages f IF-MSA cntrl technique as well as the crrectness f the theretical analysis. Research results shw that the IF-MSA cntrlled cnverter enys excellent steady and transient state perfrmance as well as the wider put ltage scpe. 1. Intrduct In recent years, the cuntries arund the wrld are facg such utstandg prblems as the energy crisis and envirnmental degradat. It is crucial t use all kds f energy cmprehensively and efficiently fr future sustaable energy supply. Our cuntry per-capital share f il resurces is far lwer than the wrld average, there is an bvius il energy gap. At the same time, such as fg and water pllut envirnment prblems als affect the natal ecnmy and peple s livelihd which need t be slved urgent. Therefre, further studyg a series f technlgy prblems f new energy is the key t sustaable develpment and slvg energy shrtage. Clean fuels such as slar and wd energy is cncerned, clean energy pwer generat technlgy is develpg rapidly and has a clear future. Cmpared with the tradital thermal pwer, clean energy pwer generat system has the advantages f renewable, n pllut, high degree f autmat, but due t the fluence f natural envirnment, its utput characteristic is mre cmplex, the pwer quality is difficult t guarantee, nt directly prvide electricity equipment. S specific pwer transfrmat technlgy is usually used, DC-DC switchg technlgy (that is DC-DC switchg cnverter) is ne imprtant part f it. Due t the nnlear characteristics f phtltaic array, the utput ltage f phtltaic array is affected by light tensity, envirnmental temperature and lad cndits[1-7]. Therefre, it is necessary t study a DC switchg cnverter technique which can adapts t changes wide range put surce ltage. In recent decades, ulse Width Mdulat (WM) technique based n the classical lear cntrl thery is widely used the field f switch cnverter technlgy, but its perfrmance transient characteristics and stability is pr, thus sme schlars put frward a kd f new cntrl technique which is based n nnlear cntrl regulat called ulse Adustment (A). Cmpared with the cnvental WM, A cntrl technique has mre excellent transient perfrmance and stability, but the A cntrlled cnverter by a cmbat f tw different cntrl pulses has the 016. The authrs - ublished by Atlantis ress 7

2 drawback f relatively narrw range f put ltage which limits its applicat phtltaic field [8-1]. Then sme mdified pulse adustg cntrl technique maly fcus n the features f ptimizg the utput characteristic f the cntrlled cnverter which als des nt apply t the ccass required wide range put ltage [13-15]. In rder t slve this prblem, the paper puts frward and studies a new cntrl technique named IF-MSA fr switchg cnverters. First, the paper will trduce the basic prciple f the IF-MSA cntrl technique, then study the wrk characteristics and cntrllg regulat f Bst cnverter peratg DCM as an example, fally verify the feasibility and advantages f IF-MSA cntrl technique thrugh the simulat and experimental results.. rciple f IF-MSA Cntrl Technique Unlike rigal pulse adustment (A) cntrl technique realized by a cmbat f tw different cntrl pulses, IF-MSA cntrl technique extends these tw different pulses t multiple sets f cntrl pulses. The prciple f IF-MSA cntrl technique is trduced as fllws: At the begng f each switchg perid, the IF-MSA cntrller senses the put ltage and utput ltage f DC-DC cnverter. The put ltage is cmpared with the pre-defed ltage bundary σ n-1 (n=, 3) t determe which ne set f 1 and 1, and, 3 and 3 will be selected as the cntrl pulses. At the same time, the utput ltage is cmpared with desired ltage ref t determe crrespndg level pulse between and ( = 1,, 3). When the utput ltage is higher than the desired level, lw-pwer pulse with shrter turn-n time is emplyed. On the cntrary, when the utput ltage is lwer than the desired ltage, high-pwer pulse with lnger turn-n time is used t drive the pwer switch. The lnger the turn-n time, the mre pwer is delivered t the lad. As shwn Fig. 1, this is a IF-MSA cntrlled DC-DC cnverter peratg DCM, with IF-MSA cnsistg f three sets different cntrl pulses 1 and 1, and, 3 and as an example. 3 At the begng f each switchg perid, if < σ 1,which means the put ltage is much lwer than the rated put ltage, the highest level f a set f cntrl pulse is emplyed sequentially; if σ 1 < < σ, which means the put ltage is clse t the rated put ltage, the secnd higher level f a set f cntrl pulse is emplyed sequentially; If > σ,which means the put ltage is much higher than the rated put ltage, the lwest level f a set f cntrl pulse is emplyed sequentially. Accrdg t the utput ltage sensed, high-pwer pulse pulse is used, if < ref, high-pwer pulse r lw-pwer is selected t drive the pwer switch; if > ref, lw-pwer pulse is selected t drive the pwer switch. Abve all, the IF-MSA cntrller selects ne amng multiple sets f cntrl pulse accrdg t the amplitude f the cnverter put ltage and emits the high-pwer pulse r lw-pwer pulse accrdg t the relatship between the utput ltage f DC-DC cnverter and the desired ltage. A IF-MSA repetit cycle is cnsisted f pulse sequence cnstructed by the cmbat f and.when the cnverter is peratg the steady-state, the IF-MSA cntrller emits the same pulse sequence repeatedly. 8

3 v DC-DC Cnverter + Cmparatr Cmparatr - vref Driver σ1 1 1 σ vp 3 3 Fig.1 Blck diagram f IF-MSA cntrller 3. Analysis f the IF-MSA Cntrlled Bst Cnverter Operatg DCM 3.1 Steady-state Characteristics Analysis. As shwn Fig., this is the Bst cnverter pwer circuit. Assumg that the Bst cnverter utput ltage ripple can be ignred each switchg perid, the analysis is trduced as fllws. v S i is Fig. Diagram f Bst cnverter With and ( = 1,, 3) cntrl pulse cycle, the averaged current flwg frm is respectively I, D T ( ) = 1,, 3 (1a) I, D T ( ) = (1b) Where the duty rati f the and The delivered energy frm put durg E E D C cntrl pulse are D and D, respectively. R and cntrl pulse cycle is respectively, = DT (a) ( ), = DT (b) ( ) We assumes that the numbers f cntrl pulses and + with ne IF-MSA repetit cycle are µ and µ, respectively. Therefre the energy delivered frm put durg the IF-MSA repetit cycle is 9

4 E = μ E, + μ E, (3) Durg ne IF-MSA repetit cycle, we have ( μ + μ ) T = η E (4) Where ƞ is the pwer cnvers efficiency f the Bst cnverter and = R is the pwer cnsumed by the lad. Then by cmbg () (4), we have ( k D + D) = ηt (5) ( )( k + 1) Where the prprt f cntrl pulses k = µ µ. and with ne IF-MSA repetit cycle is Frm (5), we cme t the cnclus that the parameters f k, D and D need t be changed t adapt t the changes the put ltage f the Bst cnverter. An illustrative example, if the put ltage changes the first amplitude range ( < σ 1 ), by adustg the pulse number rati k 1, the IF-MSA cntrlled Bst cnverter is adapted t the variat f the put ltage, D 1 and D 1 are emplyed. 3. The Design f the Cntrl arameters The IF-MSA cntrl parameters are vitally imprtant t achieve the cntrl strategy and gd cntrl characteristics r nt, the design f the IF-MSA cntrl parameters is described detail as fllws. The parameters f the Bst cnverter are given Table 1. Table 1 The parameters f the Bst cnverter arameters Significat alue Rated put ltage 6 Output ltage 1 W Output pwer 4.5 µ Inductr 33 C µf Filter capacitr 000 T µs Switchg cycle 50 The critical cndit f the Bst cnverter peratg DCM is I I D (6) Where I is the current flwg frm the lad and I D is the averaged current flwg frm the dide D ne switchg cycle. Frm (6), we have D(1 D) < RT (7) Then accrdg t the data Table 1, we deduce that any cntrl pulse duty rati D must be less than 0.76 if the Bst cnverter peratg DCM. With nly sgle cntrl pulse cycle, analgizg frm (5), we have T D = η ( ) (8) Then by assumg α =, β = η T, we deduce α + αβ D α = (9) β D Frm (9), the Bst cnverter peratg 4 put ltage, the duty rati D f the sgle cntrl pulse is Analgusly, the weighted average f the duty rati f cntrl pulses and 1 with ne IF-MSA repetit cycle is ( k 1 D 1 + D 1 ) ( k )=0.47. In rder t bta lesser utput ltage ripple, the difference between D 1 and D 1 shuld nt be set t much, 1 30

5 with k 1 =1. Fally, we determe that the duty rati D 1 and D 1 are 0.68 and 0.6, respectively. Accrdg t the methd described abve, D and D, D 3 andd 3 are determed respectively (listed Table ). Table The parameters f the IF-MSA cntrl arameters Significat alue D 1 Duty rati f cntrl pulse D 1 Duty rati f cntrl pulse D Duty rati f cntrl pulse 0.48 D Duty rati f cntrl pulse 0.16 D 3 Duty rati f cntrl pulse D 3 Duty rati f cntrl pulse σ 1 Reference put ltage 5 σ Reference put ltage Cntrl ulse Cmbat Frm (5), we deduce that k as a funct f is ( ) ηtd k = η T D ( ) Therefre, equat (10) and Figure 3a can be used t estimate the prprt f IF-MSA cntrl pulses at any put ltage. (10) k k 1 k 3 k 3 k σ1 σ 9.3 (a) The IF-MSA cntrl (b) The A cntrl Fig.3 k r k as a funct f put ltage Frm Fig 3a, we knw that the IF-MSA cntrlled Bst cnverter can nrmally perate under put ltage variats frm 3.3 t 9.3, k varyg between 14 and 4. The larger k than 4 and the smaller k than 14, the larger the utput ltage ripple. Frm Fig 3b, we deduce that the A cntrlled Bst cnverter can nrmally perate under put ltage variats frm 5.1 t 7.3, k varyg between 14 and 4. In cnclus, the applicable put ltage scpe f the IF-MSA cntrlled Bst cnverter is much wider than the A cntrlled Bst cnverter. 31

6 4. Simulat Results Simulats are perfrmed usg the same parameters given Table 1 and Table. Fig.4 shws the steady-state wavefrms f the IF-MSA cntrlled Bst cnverter peratg the rated put ltage 6. Fig.4 Steady-state wavefrms f IF-MSA cnverter fr 6 put ltage A i t ms (a) Inductr current t ms (b) Cntrl pulses t ms (c) Output ltage Frm Fig.4b, we can knw that the cntrl pulses with the IF-MSA repetit cycle are - - -, and the prprt k f the IF-MSA cntrl pulses is 3. Frm Fig.4c, we can deduce that the utput ltage f the IF-MSA cnverter is 1, and the ltage ripple is 65m. The wavefrms f IF-MSA and A cntrlled cnverter under put ltage variats are shwn Fig.5. Frm Fig.5, we can see the utput ltage ripple f the IF-MSA cntrl is 70m, put ltage varyg frm 3.5 t 5 t 7 t 9, while the utput ltage ripple f the A cntrl is 100m, put ltage varyg frm 5 t 7. Frm Fig.5a, we can knw that there is n bvius rise fr the utput ltage f the IF-MSA cntrlled cnverter under put ltage varyg frm 5 t 7; frm Fig.5b, we can see that there is a little rise fr the utput ltage f the A cntrlled cnverter under put ltage varyg frm 5 t 7. Frm the discuss abve, we deduce that the utput ltage ripple f the IF-MSA cntrl is lwer than the A cntrl under put ltage variats, and cmpared with the A cntrlled cnverter, the IF-MSA cntrlled cnverter enys excellent steady and transient state perfrmance and the wider put ltage scpe. 3

7 t ms Inductr current t ms A v i Output ltage t ms Input ltage (a) IF-MSA cntrl t ms Inductr current t ms Output ltage t ms Input ltage A i v (b) A cntrl Fig.5 Wavefrms f IF-MSA and A cntrlled cnverter under put ltage variats 5. Experimental Results Experiments are als perfrmed usg the same parameters given Table 1 and Table. The wavefrms f the IF-MSA cntrlled cnverter under different put ltage (4, 6, 8) are shwn Fig.6~fig.8. (5div) (50mdiv) i (1Adiv) (5div) div) Inductr current and cntrl pulses div) Output ltage and ltage ripple Fig.6 Experimental results f IF-MSA cntrl fr 4 put ltage (5div) (50mdiv) i (1Adiv) (5div) div) Inductr current and cntrl pulses div) Output ltage and ltage ripple Fig.7 Experimental results f IF-MSA cntrl fr 6 put ltage 33

8 (5div) (50mdiv) i (1Adiv) (5div) div) Inductr current and cntrl pulses div) Output ltage and ltage ripple Fig.8 Experimental results f IF-MSA cntrl fr 8 put ltage The wavefrms f the A cntrlled cnverter under 4 put ltage are given Fig.9, frm which is knwn that the A cnverter can nt nrmally perate steady-state s that the utput ltage 11 is much lwer than the desired ltage 1. (10div) (50mdiv) i (Adiv) (5div) div) div) Inductr current and cntrl pulses Output ltage and ltage ripple 9 The wavefrms f the A cntrl fr 4 put ltage Fig. 6. Summary Multiple Sets f ulse Adustment Based n Input ltage Feed-frward Cmpensat (IF-MSA), a new cntrl technique fr DC-DC cnverters is prpsed and studied the paper. Bst cnverter peratg DCM is taken as an example t illustrate the prciple and cntrl regulat f IF-MSA cntrl scheme. Thery analysis, simulat results and experimental results shw that the IF-MSA cntrlled cnverter enys gd steady and transient state perfrmance as well as the wider put ltage scpe cmpared with the A cntrlled cnverter. Acknwledgement The research wrk is supprted by the Natal Natural Science Fundat f Cha under prect number and Cha stdctral Science Fundat under prect number 01M References [1]. WU F,SUN X,JIANG Y. Effect f DC micr-grid peridical ripple n utput pwer f phtltaic system and its elimat[j]. Electric wer Autmat Equipment,014,34 (3): 34

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