ENG2410 Digital Design Arithmetic Circuits

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1 ENG24 Digital Design Arithmetic Circuits Fall 27 S. Areibi Schl f Engineering University f Guelph Recall: Arithmetic -- additin Binary additin is similar t decimal arithmetic N carries + + Remember: + is 2 (r () 2 ), which results in a carry ++ is 3 (r () 2 ) which als results in a carry Carries 4 Tpics Half Adder (One bit adder) Binary Adders Binary Ripple Carry Adder s and 2 s Cmplement Binary Subtractin Binary Adder-Subtractrs Binary Multipliers BCD Arithmetic S = XY + X Y = X Y C = X.Y 2 5 Resurces Full Adder Chapter #5, Man Sectins 5.2 Binary Adders 5.3 Binary Subtractin 5.4 Binary Adders-Subtractrs 5.5 Binary Multiplicatins 5.7 HDL Representatins -- VHDL Three inputs: X Y Third is C in Z Tw utputs: Sum C ut C ut x Full Adder S y Z Implementatin? 3 6 Schl f Engineering

2 Straight Frward Implementatin: Any Alternatives? K Map fr S Z S Try t make use f hierarchy t design a -bit full adder frm tw half adders. Als, try t share lgic between the Sum utput and Carry utput. What is this? Half Adder S = X Y C = XY Full Adder S = X Y Z C = XY + XZ + YZ 7 Straight Frward Implementatin: A Different Way t Represent C K Map fr C XYZ X Y X C YZ X XY C = XY + XZ+ YZ Z Y Z XYZ C = XY + XYZ + XYZ C = XY + Z (XY + XY) 8 Implementatin Issues Tw Half Adders (and an OR) C = XY + XZ+ YZ Hw many Gates d we need? If we try t implement the Optimized Blean functins directly we will need hw many gates? Seven AND gates and tw OR Gates!! Can we d better? YES!! x y Share Lgic Hierarchical Design. C Full Adder Z 9 S 2 Schl f Engineering 2

3 Binary Ripple-Carry Adder VHDL Half Adder (DATA FLOW) A Parallel binary adderis a digital circuit that prduces the arithmetic sum f tw binary numbers using nly cmbinatinal lgic. The parallel adder uses n full addersin parallel, with all input bits applied simultaneusly t prduce the sum. The full adders are cnnected in cascade, with the carry utput frm ne full adder cnnected t the carry input f the next full adder. entity half_adder is prt (x_ha,y_ha: in std_lgic; s_ha,c_ha: ut std_lgic); end half_adder; architecture dataflw f half_adder is begin s_ha <= x_ha xr y_ha; c_ha <= x_ha and y_ha; end dataflw 3 6 Binary Ripple-Carry Adder VHDL Full Adder (Structural) Straightfrward cnnect full adders Carry-ut t carry-in chain C in case this is part f larger chain, maybe just set t zer 4 entity full_adder is prt (x_fa, y_fa, z_fa: in std_lgic; s_fa, c_fa: ut std_lgic); end full_adder; architecture struc_dataflw f full_adder is cmpnent half_adder prt (x_ha, y_ha : in std_lgic; s_ha, c_ha : ut std_lgic); end cmpnent; signal hs, hc, tc: std_lgic; begin HA: half_adder prt map (x_fa, y_fa, hs, hc); HA2: half_adder prt map (hs, z_fa, s_fa, tc); c_fa <= tc r hc; end struc_dataflw hs hc tc 7 Hierarchical 4-Bit Adder Any Prblems with this Design? We can easily use hierarchy here. Design half adder 2. Use TWO half adders t create full adder 3. Use FOUR full adders t create 4-bit adder VHDL CODE? Delay Apprx hw much? Imagine a 64-bit adder Lk at carry chain 5 8 Schl f Engineering 3

4 Carry Prpagatin & Delay BCD Additin One prblem with the additin f binary numbers is the length f time t prpagate the ripple carry frm the least significant bit t the mst significant bit. The gate-level prpagatin path fr a 4-bit ripple carry adder f the last example: Nte: The "lng path" is frm A r B thrugh the circuit t S 3. A 3B3 A 2 A A B 2 B B C 3 C 2 C C If the binary result is greater than 9, crrect the result by adding a 6 Multiple Decimal Digits Tw Decimal Digits C 4 S 3 S 2 S S 9 22 Recall: Binary Cded Decimal BCD Additin Binary Cded Decimal (BCD) Each Decimal Digit is represented by 4 bits ( 9) Valid cmbinatins ( 5) Invalid cmbinatins Decimal BCD Fur binary digits cunt up t 5 () but in BCD we nly use the representatins up t 9 (). The difference between 5 and 9 is 6. If yu want 9+ t prduce, which is, yu have t add 6 t make wrap t. It is dne t skip the six invalid states f binary cded decimal i.e frm t 5 and again return t the BCD cdes BCD Additin One decimal digit + ne decimal digit If the result is decimal digit ( 9 ), then it is a simple binary additin 5 Example: If the result is tw decimal digits ( ), then binary additin gives invalid cmbinatins Example: BCD Arithmetic 8 Eight +5 + Plus Five 3 is 3 (> 9) Nte that the result is MORE THAN 9, s must be represented by tw digits! T crrect the digit, add 6 8 Eight +5 + Plus 5 3 is 3 (> 9) + s add 6 carry = leaving 3 + cy Final answer (tw digits) ENG24/Digital Design 24 Schl f Engineering 4

5 BCD Additin Circuit Binary Subtractin Brrw a Base when needed Design a BCD Adder that adds tw BCD digits. Cnstraints: Use 4-bit Binary Adders Hints: A detectin circuit that detects invalid BCD digits will need t be designed = () 2 = (77) = (23) = (54) BCD Additin Subtractin BCD # BCD # 2 Addend Augend Output Carry Detectin Circuit fr Invalid BCD 4-bit binary adder r 6 Input Carry Add if result is valid Add 6 if result is invalid We managed t design an Adder easily. Fr subtractin, we will als need t design a Subtractr!! Can we perfrm subtractin using the Adder Circuit we designed earlier? YES, we can use the cncept f Cmplements. X = Y Z X = Y + cmplement(z) 4-bit binary adder BCD Sum ENG24/Digital Design Z 3 Z 2 Z Z BCD Additin Cmplements? There are tw types f cmplements fr each base-r system The radix cmplement, the (r s) cmplement. The diminished radix cmplement, (r-) s cmp. Fr Decimal System s cmplement 9 s cmplement Fr Binary Systems 2 s cmplement s cmplement 27 3 Schl f Engineering 5

6 Cmplements f Decimal System Binary Subtractin The 9 s cmplement f a decimal number is btained by subtracting each digit frm 9. Example: The 9 s cmplement f 5467 is = The s cmplement is btained by adding t the 9 s cmplement: Example: The s cmplement f 5467 is = = 4533 Or, 5467 = 4533 Or, leave all least significant s unchanged, subtract the first nnzer LSD frm, and subtract all higher significant digits frm 9. We ll use unsigned subtractin t mtivate use f cmplemented representatin 3 34 Unsigned Decimal Subtractin = Example # Use s cmplement t perfrm the subtractin M = (5-digits), N = 325 (4-digits) Since N has nly 4 digits append a zer N=325 What is the s cmplement f N (325)? = = 9675 Nw add M t the s cmp f N = (carry ccurred) The ccurrence f the end carry indicates that M > N Discard end carry (69282 = 69282) s Cmplement s Cmplement (Diminished Radix Cmplement) All s becme s All s becme s Example () 2 () 2 If yu add a number and its s cmplement??? Unsigned Decimal Subtractin Example #2 s Cmplement: Example = (HOW??) Cmpare the numbers, exchange their psitins, Use s cmplement t perfrm the subtractin M = 325 (4-digits), N = (5-digits) Since M has nly 4 digits append a zer M=325 What is the s cmplement f N (72532)? = = Nw add M t the s cmp f N = 378 (There is n end carry!) N end carry indicates that M < N (make crrectin!!) Answer: -( s cmplement f 378) = Ntice that the s cmplement f the number can be btained by cmplementing each bit 2 n - - N s Cmpl. 36 Schl f Engineering 6

7 2 s Cmplement 2 s Cmplement (Radix Cmplement) Take s cmplement then add OR Tggle all bits t the left f the first frm the right Example: Number: s Cmp.: + 37 Example Brrw (M) Minuend (N) Subtrahend - Difference Crrect Diff - Prcedure? If n brrw, then result is nn-negative (minuend >= subtrahend). Since there is brrw, result must be negative. The result must be crrected t a negative number. 9 3 = s Cmplement: Example Algrithm: Subtractin f tw n-digit Numbers M-N can be dne as fllws 2 n - N s Cmp 2 s Cmpl. Ntice that the 2 s cmplement f the number can be btained by cmplementing each bit and adding.. Subtract N frm M If n brrw, then M N and result is OK! Else, N > M s result must be subtracted frm 2 n and a minus sign shuld be appended 2. NOTE: Subtractin f a binary number frm 2 n t btain an n-digit result is called 2 s cmplement 3. Circuit? 38 4 Example: Incrrect Result Adder/Subtractr Circuit!! Minuend is smaller than Subtrahend Brrw (M) Minuend (N) Subtrahend - Difference 9 3 = 2!!!!! Binary Adder Binary Subtractr Incrrect Result!! Hw can we knw if the result is incrrect? Hw t fix the prblem? EXPENSIVE!! Schl f Engineering 7

8 Hw t get rid f Subtractin Operatin? Example 2 Any Idea? Use cmplements f numbers t replace the subtractin peratin with additin nly. Y = minus X = Ntice Y < X Y + 2 s cmp X Sum N end carry Answer: - (2 s cmplement f Sum) - We said numbers are unsigned. What des this mean? Subtractin f Unsigned Numbers Using Cmplements Adder-Subtractr. M N Equivalent t M + (2 s cmplement f N) 2. Add (2 s cmplement f N) t M This is M + (2 n N) = M N + 2 n Ntice we are using additin t achieve subtractin. 3. If M N, will generate carry! Result is crrect Simply discard carry Result is psitive M - N 4. If M < N, n end carry will be generated! Make Crrectin Take 2 s cmplement f result Place minus sign in frnt I. By using 2 s cmplement apprach we were able t get rid f the design f a subtractr. II. Need nly adder and cmplementer fr input t subtract III. Need selective cmplementer t make negative utput back frm 2 s cmplement Example Selective s Cmplementer? X = minus Y = Ntice that X > Y The 2 s cmplement f Y= is btained first by getting the s cmplement and then adding () Cntrl X + 2 s cmp Y Sum When X = we transfer Y t utput When X = we cmplement Y Cntrl Schl f Engineering 8

9 S B In Design Subtractin f Unsigned Numbers Using Cmplements S lw fr add, high fr subtract Inverts each bit f B if S is Signed Magnitude Representatin Magnitude is magnitude, des nt change with sign S Magnitude (Binary) (+3) ( ) 2 ( 3) ( ) 2 Sign Magnitude Selective s Cmplementer Adds t make 2 s cmplement Negative Numbers s Cmplement Representatin Cmputers Represent Infrmatin in s and s + and signs have t be represented in s and s 3 Systems Signed Magnitude s Cmplement 2 s Cmplement All three use the left-mst bit t represent the sign: psitive negative 5 Psitive numbers are represented in Binary Magnitude (Binary) Negative numbers are represented in s Cmp. Cde ( s Cmp.) (+3) ( ) 2 ( 3) ( ) 2 There are 2 representatins fr!!!!!! (+) ( ) 2 ( ) ( ) 2 53 Signed Binary Numbers s Cmplement Range First review signed representatins Signed magnitude Left bit is sign, psitive, negative Other bits are number s cmplement s cmplement 5 4-Bit Representatin 2 4 = 6 Cmbinatins 7 Number Number +2 3 n-bit Representatin 2 n + Number +2 n Decimal s Cmp Schl f Engineering 9

10 2 s Cmplement Representatin Psitive numbers are represented in Binary Magnitude (Binary) Negative numbers are represented in 2 s Cmp. Cde (2 s Cmp.) 4-Bit Example Number Representatins Unsigned Binary Signed Magnitude s Cmp. 2 s Cmp. Range N 5-7 N +7-7 N +7-8 N +7 (+3) ( ) 2 ( 3) ( ) 2 There is representatin fr (+) ( ) 2 ( ) ( ) 2 s Cmp. + Psitive Negative Binary Binary Binary Binary X Binary s Cmp. 2 s Cmp s Cmplement Range Example in 8-bit byte 4-Bit Representatin 2 4 = 6 Cmbinatins 8 Number Number n-bit Representatin 2 n Number + 2 n Decimal 2 s Cmp Represent +9 in different ways Signed magnitude s Cmplement 2 s Cmplement Represent -9 in different ways Signed magnitude s Cmplement 2 s Cmplement The Same! Cnvert 2 s Cmplement t Decimal Observatins bit index bit weighting Example Decimal x-2 7 x2 6 x2 5 x2 4 x2 3 x2 2 x2 x = 82 bit index bit weighting Example Decimal x-2 7 x2 6 x2 5 x2 4 x2 3 x2 2 x2 x = All psitive numbers are the same s Cmp and Signed Mag have tw zers 2 s Cmp has mre negative than psitive All negative numbers have in high-rder bit 6 Schl f Engineering

11 Advantages/Disadvantages Signed magnitude has prblem that we need t crrect after subtractin One s cmplement has a psitive and negative zer Tw s cmplement is mst ppular i.e arithmetic peratins are easy 6 Signed Magnitude Arithmetic Cmplex Rules!! The additin f tw numbers M+N in the sign magnitude system fllws the rules f rdinary arithmetic: If the signs are the same, we add the tw magnitudes and give the sum the sign f M. If the signs are different, we subtract the magnitude f N frm the magnitude f M. The absence r presence f an end brrw then determines: The sign f the result. Whether r nt a crrectin is perfrmed. Example: ( ) + ( ) = End brrw f ccurs, M < N!! Sign f result shuld be that f N, Als crrect result by taking the 2 s cmplement f result 64 Signed Magnitude Representatin Binary Subtractin Using s Cmp. Additin Magnitude is magnitude, des nt change with sign S Magnitude (Binary) (+3) ( ) 2 ( 3) ( ) 2 Sign Magnitude Can t include the sign bit in Additin (+3) + ( 3) Change Subtractin t Additin If Carry = then add it t the LSB, and the result is psitive (in Binary) If Carry = then the result is negative (in s Cmp.) (5) () (+5) + (-) + + (5) (6) (+5) + (-6) + ( 6) Signed Magnitude Representatin Tw s Cmplement The signed-magnitude system is used in rdinary arithmetic, but is awkward when emplyed in cmputer arithmetic (Why?). We have t separately handle the sign 2. Perfrm the crrectin if necessary!! Therefre the signed cmplement ( s cmplement and 2 s cmplement number representatins) is nrmally used. T Add: Easy n any cmbinatin f psitive and negative numbers T subtract: Als easy! Take 2 s cmplement f subtrahend Add This perfrms A + ( -B), same as A B Schl f Engineering

12 Binary Subtractin Using 2 s Cmp. Additin Change Subtractin t Additin If Carry = ignre it, and the result is psitive (in Binary) If Carry = then the result is negative (in 2 s Cmp.) (5) () (+5) + (-) + (5) (6) (+5) + (-6) Additin f : a Psitive and Negative Numbers Additin (-6) + 3 = +7 (this is 2 s cmp f +6) The carry ut was discarded 67 7 Examples frm Bk Subtractin f Tw Numbers The numbers belw shuld be in 2 s cmp representatin Additin (+6) + 3 (-6) + 3 (+6) + (- 3) (-6) + (-3) Subtractin (-6) - (-3) (+6) - (-3) The subtractin f tw signed binary numbers (when negative numbers are in 2 s cmplement frm) can be accmplished as fllws:. Take the 2 s cmplement f the subtrahend (including the sign bit) 2. Add it t the minuend. 3. A Carry ut f the sign bit psitin is discarded Additin f Tw Psitive Numbers Subtractin f Tw Numbers Additin (+6) + 3 = If a carry ut appears it shuld be discarded. 69 Subtractin (+6) (+3) = (2 s cmp) What is? Take its 2 s cmplement=> The magnitude is 7 S it must be Schl f Engineering 2

13 Circuit fr 2 s cmplement Numbers Overflw Tw cases f verflw fr additin f signed numbers Tw large psitive numbers verflw int sign bit Nt enugh rm fr result Tw large negative numbers added Same nt enugh bits Carry ut can be OK N Crrectin is needed if the signed numbers are in 2 s cmplement representatin Sign Extensin Examples Sign extensin is the peratin, in cmputer arithmetic, f increasing the number f bits f a binary number while preserving the number s sign (psitive/negative) and value. This is dne by appending digits t the mst significant side f the number Examples: 2 s cmplement (6-bits 8-bits) 2 s cmplement (5-bits 8-bits): Tw signed numbers +7 and +8 are stred in 8-bit registers. The range f binary numbers, expressed in decimal, that each register can accmmdate is frm +27 t -28. Since the sum f the tw stred numbers is 5, it exceeds the capacity f an 8-bit register. The same applies fr -7 and Overflw In rder t btain a crrect answer when adding and subtracting, we must ensure that the result has a sufficientnumber f bits t accmmdate the sum. If we start with tw n-bit numbers and we end up with a number that is n+ bits, we say an verflw has ccurred. Overflw Detectin Carries: Carries: The additin f +7 and +8 resulted in a negative number! 2. The additin f -7 and -8 als resulted in an incrrect value which is psitive number! 3. An verflw cnditin can be detected by bserving the carry int the sign bit psitin and the carry ut f the sign bit psitin. 4. If the the carry in and carry ut f the sign bit are nt equal an verflw has ccurred Schl f Engineering 3

14 Circuit fr Overflw Detectin Multiplier Cnditin is that either C n- r C n is high, but nt bth Multiply by ding single-bit multiplies and shifts Cmbinatinal circuit t accmplish this? The value f A B Will either be r What type f gate can we use? Binary Multiplicatin Cmbinatinal Multiplier Bit by bit x AND cmputes A B Half adder cmputes sum. Will need FA fr larger multiplier Binary Multiplicatin: Example II Larger Multiplier: Resurces X What type f lgic circuit d we need t perfrm Binary Multiplicatin? Fr J multiplier bits and K multiplicand bits we need J x K AND gates (J-) K-bit adders t prduce a prduct f J+K bits Schl f Engineering 4

15 Larger Multiplier A k=4-bit by j=3-bit Binary Multiplier. J = 3 (Multiplier) K = 4 (Multiplicand) Jxk = 2 AND Gates (J-) Adders Of k bits each 85 Schl f Engineering 5