# Medium Scale Integrated (MSI) devices [Sections 2.9 and 2.10]

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1 EECS 270, Winter 2017, Lecture 3 Page 1 f 6 Medium Scale Integrated (MSI) devices [Sectins 2.9 and 2.10] As we ve seen, it s smetimes nt reasnable t d all the design wrk at the gate-level smetimes we just want bigger building blcks. Fr example, we used full-adders as the building blcks f ur ripple-carry adder. Yu can imagine that as we d designs we might find that there are certain building blcks we use ver and ver again. As yu might guess, being familiar with a cmmnly-used set f building blcks can make designing digital devices easier. Building blcks that are mre cmplex than gates are smetimes called medium-scale integrated devices, r MSI devices fr shrt. Exactly what makes a device medium in scale rather than large r very large (as in VLSI which yu may have heard f) is nt always agreed n, but we ll generally stick with devices that are fairly simple and where small versins f them can be implemented in a cuple dzen gates r s. The devices We ll cver fur cmmn devices tday: decder, encder, pririty encder, and MUX. The MUX we ve seen befre. Other MSI devices yu ll need t be familiar with are the cmparatr, adder, and demux (see text). Decder N inputs, 2 N utputs. It decdes the N-bit binary number and sets exactly ne f the decder s utputs t 1. S if the input f the 2 t 4 decder shwn belw is I[1:0]=01, then O 1 will be a 1 and the ther three utputs will be a 0. 2 t 4 decder I0 I1 O0 O1 O2 O3 Questins/prblems 1. If the input I[1:0]=11, what will the utputs be? 2. Draw the lgic gates needed t build the abve 2 t 4 decder. 3. Cnsider the lgic equatin (ABC+A BC +AB C ). Using nly a 3 t 8 decder and ne gate implement that lgic functin.

2 EECS 270, Winter 2017, Lecture 3 Page 2 f 6 Encder 2 N inputs, N utputs It assumes exactly ne input is a 1 and utputs a binary number that crrespnds t the input that is a ne. Put anther way, it undes the wrk f the decder. Fr example, if I[3:0]=0010, O[1:0]=01. 4 t 2 encder I0 I1 I2 I3 O0 O1 Questins/prblems 1. If the I[3:0]=1000, what will the utputs be? 2. If the input I[3:0]=0100, what will the utputs be? 3. If the input I[3:0]=1001, what will the utputs be? 4. Draw lgic gates which implement a 4 t 2 encder. Yu can assume that exactly ne input will be a 1. Pririty Encder Just like an encder but if mre than ne input is a 1 the utput is based n the largest input. S if I[3:0]=0101, O[1:0]=10. Questins/prblems 1. If I[3:0]=D 16, what will the utputs be? 2. If I[7:0]= , what will the utputs be? 3. If I[7:0]= 0C 16, what will the utputs be? Nte: it is cmmn t have an enable utput (EO) signal which is 1 nly if at least ne input is 1.

3 EECS 270, Winter 2017, Lecture 3 Page 3 f 6 MUX We ve lked at 2 t 1 MUXes previusly, but we culd have X t 1 where X is any integer greater than 1. We culd als have n-bit MUXes. Fr example, belw we have a 4-bit 2 t 1 MUX. Here we are just chsing ne f tw grups f 4 t rute t the utput. 4-bit 2 t 1 MUX 4 t 1 MUX A[3:0] B[3:0] X[3:0] A B C D X 2 S S[1:0] Naming cnventins fr MUXes are nt as standard as we might like. That leftmst figure might be called a 4-bit 2:1 MUX, a 4-bit 2-1 MUX, r even an 8 t 4 MUX. Questins/prblems 1. Fr the 4 t 1 MUX, if A=0, B=1, C=0, D=1 and S=01, what is X? 2. Hw many select lines wuld yu need fr a 2-bit 8 t 1 MUX? 3. Build a 2-bit 2 t 1 MUX ut f 2 t 1 MUXes. 4. Build a 4 t 1 MUX ut f 2 t 1 MUXes. 5. Build a 2 t 1 MUX ut f gates.

4 EECS 270, Winter 2017, Lecture 3 Page 4 f 6 Slving prblems with MSI devices In cmputer architecture it is cmmn t have N devices that culd request a given resurce. This is ften implemented by giving each device a request line (which if it s 1 means they want t use the resurce) and a grant line (which if it s ne means they have been granted the device.) Using MSI devices design an arbiter takes 4 request lines and asserts nly ne grant line. If multiple devices are requesting at the same time, yu can pick any f them (yu pick the pririty). Designing an MSI device Design, at the gate level, a 2-bit greater than cmparatr. That is it takes tw 2-digit numbers A and B and utputs a 1 if and nly if A>B. Hw wuld yu design a 4-bit greater-than cmparatr?

5 EECS 270, Winter 2017, Lecture 3 Page 5 f 6 Representing negative numbers in binary ( , p st) When we represent negative numbers in decimal, we use an additinal symbl, the minus sign, t indicate that the number is negative. When using a cmputer we nly have nes and zers, s we can t use sme extra character t indicate that the number is negative. One trick we culd play is t have ne f the bits f the number indicate sign. Signed-magnitude representatin One scheme yu culd use is just t have ne f the bits in the number be the sign bit. Say if the leftmst bit (i.e. the mst significant bit) is a ne the rest f the number is negative and if it s zer then the number is psitive. S 1100 is -4 while 0100 is 4. Hw wuld we write -6?. 6? In a cmputer r ther digital device we generally have a fixed number f bits per number. Say we are using 4-bit numbers. What is the smallest number we can represent? The largest? Fr an n-bit number using signed magnitude representatin, what is the range f representatin? Hw many different values can we represent with n-bits? This scheme has any number f dwnsides. The mst bvius is that building an equals cmparatr is a bit tricky. Why? Anther issue is that building an adder which can add tw signed-magnitude numbers is a bit tricky 2 s cmplement representatin The scheme that is mst cmmnly used t represent negative numbers in a cmputer is called 2 s cmplement. The text ges int a gd degree f backgrund abut the name and why it wrks. But the basic idea is that we treat the mst significant bit as being negative but f the same magnitude it wuld be in a nrmal (unsigned) binary number. S as an unsigned number is 8. As a 2 s cmplement number it s as a 2 s cmplement number is -7 (-8+1) while 1111 is -1 ( ). It turns ut that changing the sign f 2 s cmplement numbers isn t as hard as yu might think (thugh harder than signed magnitude). Flip all the bits and add 1. S 1111 = -1. Flip the bits and yu get Add 1 and yu get 0001 r 1. Say we are using 4-bit numbers. What is the smallest number we can represent? The largest? As befre we generally have a fixed number f bits per number. Say we are using 4-bit numbers. What is the smallest number we can represent? The largest? Fr an n-bit number using 2 s cmplement representatin, what is the range f representatin? Hw many different values can we represent with n-bits?

6 EECS 270, Winter 2017, Lecture 3 Page 6 f 6 Adding 2 s cmplement numbers The reasn we tend t use 2 s cmplement numbers is that traditinal binary additin wrks exactly the same as lng as the result is in the range f representatin. We just lp ff any extra bits. Fr the fllwing prblems add the values as if they were unsigned numbers, nly keeping the first fur digits. Which f these additins are crrect fr 4-bit unsigned values? Fr 4-bit 2 s cmplement values? ======= ========= ========= ========= Bits is bits What is the value f the binary value 1000? The right answer is it depends. As an unsigned number it s 8. As a 2 s cmplement number it s -8. As a signed-magnitude number it is 0. The key pint is that we use 0s and 1s t represent everything. Exactly hw we treat thse 0s and 1s depends n the cntext. In a cmputer the same 0s and 1s culd be used t represent different numbers, r letters (ASCII fr example), cmputer instructins, r just abut anything else. Bits dn t have meaning withut cntext, thugh we ften assume they are unsigned numbers when n cntext is given. Questins Treated as an 8-bit 2 s cmplement number, what is the value f 4C 16? FF 16? C0 16? When ding additin f fixed-bit unsigned numbers, hw d yu detect verflw? Hw abut with fixed-bit 2 s cmplement numbers?

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