Chapter 3 Digital Transmission Fundamentals

Transcription

1 Chapter 3 Digital Transmissin Fundamentals Errr Detectin and Crrectin Errr Cntrl Digital transmissin systems intrduce errrs, BER ranges frm 10-3 fr wireless t 10-9 fr ptical fiber Applicatins require certain reliability level Data applicatins require errr-free transfer Vice & vide applicatins tlerate sme errrs Errr cntrl used when transmissin system des nt meet applicatin requirement Errr cntrl ensures a data stream is transmitted t a certain level f accuracy despite errrs Tw basic appraches: Errr detectin & retransmissin (ARQ) Frward errr crrectin (FEC)

2 Key Idea All transmitted data blcks ( cdewrds ) satisfy a pattern If received blck desn t satisfy pattern, it is in errr Redundancy: Only a subset f all pssible blcks can be cdewrds User infrmatin All inputs t channel satisfy pattern r cnditin Encder Channel Channel utput Pattern checking Deliver user infrmatin r set errr alarm Single Parity Check Append an verall parity check t k infrmatin bits Inf Bits: b 1, b 2, b 3,, b k Check Bit: b k+1 = b 1 + b 2 + b b k mdul 2 Cdewrd: (b 1, b 2, b 3,, b k,, b k+! ) All cdewrds have even # f 1s Receiver checks t see if # f 1s is even All errr patterns that change an dd # f bits are detectable All even-numbered patterns are undetectable Parity bit used in ASCII cde

3 Example f Single Parity Cde Infrmatin (7 bits): (0, 1, 0, 1, 1, 0, 0) Parity Bit: b 8 = = 1 Cdewrd (8 bits): (0, 1, 0, 1, 1, 0, 0, 1) If single errr in bit 3 : (0, 1, 1, 1, 1, 0, 0, 1) # f 1 s =5, dd Errr detected If errrs in bits 3 and 5: (0, 1, 1, 1, 0, 0, 0, 1) # f 1 s =, even Errr nt detected Checkbits & Errr Detectin Infrmatin bits Received infrmatin bits k bits Recalculate check bits Calculate check bits Sent check bits n k bits Channel Received check bits Cmpare Infrmatin accepted if check bits match

4 Hw gd is the single parity check cde? Redundancy: Single parity check cde adds 1 redundant bit per k infrmatin bits: verhead = 1/(k + 1) Cverage: all errr patterns with dd # f errrs can be detected An errr patten is a binary (k + 1)-tuple with 1s where errrs ccur and 0 s elsewhere Of 2 k+1 binary (k + 1)-tuples, ½ are dd, s 50% f errr patterns can be detected Is it pssible t detect mre errrs if we add mre check bits? Yes, with the right cdes What if bit errrs are randm? Many transmissin channels intrduce bit errrs at randm, independently f each ther, and with prbability p Sme errr patterns are mre prbable than thers: P[ ] = p(1 p) 7 = (1 p) 8 p 1 p and p 2 P[ ] = p 2 (1 p) 6 = (1 p) 8 1 p In any wrthwhile channel p < 0.5, and s (p/(1 p) < 1 It fllws that patterns with 1 errr are mre likely than patterns with 2 errrs and s frth What is the prbability that an undetectable errr pattern ccurs?

5 Single parity check cde with randm bit errrs Undetectable errr pattern if even # f bit errrs: P[errr detectin failure] = P[undetectable errr pattern] = P[errr patterns with even number f 1s] n n = p 2 (1 p) n-2 + p (1 p) n- + 2 Example: Evaluate abve fr n = 32, p = P[undetectable errr] = (10-3 ) 2 ( ) (10-3 ) ( ) (10-6 ) (10-12 ).96 (10 - ) Fr this example, rughly 1 in 2000 errr patterns is undetectable What is a gd cde? Many channels have preference fr errr patterns that have fewer # f errrs These errr patterns map transmitted cdewrd t nearby n-tuple If cdewrds clse t each ther then detectin failures will ccur Gd cdes shuld maximize separatin between cdewrds x x x x x x x x = cdewrds = nncdewrds x x x x x x x Pr distance prperties Gd distance prperties

6 Tw-Dimensinal Parity Check Mre parity bits t imprve cverage Arrange infrmatin as clumns Add single parity bit t each clumn Add a final parity clumn Used in early errr cntrl systems Last clumn cnsists f check bits fr each rw Bttm rw cnsists f check bit fr each clumn Errr-detecting capability One errr Three errrs Tw errrs Fur errrs (undetectable) 1, 2, r 3 errrs can always be detected; Nt all patterns > errrs can be detected Arrws indicate failed check bits

7 Other Errr Detectin Cdes Many applicatins require very lw errr rate Need cdes that detect the vast majrity f errrs Single parity check cdes d nt detect enugh errrs Tw-dimensinal cdes require t many check bits The fllwing errr detecting cdes used in practice: Internet Check Sums CRC Plynmial Cdes Internet Checksum Several Internet prtcls (e.g. IP, TCP, UDP) use check bits t detect errrs in the IP header (r in the header and data fr TCP/UDP) A checksum is calculated fr header cntents and included in a special field. Checksum recalculated at every ruter, s algrithm selected fr ease f implementatin in sftware Let header cnsist f L, 16-bit wrds, b 0, b 1, b 2,..., b L-1 The algrithm appends a 16-bit checksum b L

8 Checksum Calculatin The checksum b L is calculated as fllws: Treating each 16-bit wrd as an integer, find x = b 0 + b 1 + b b L-1 mdul The checksum is then given by: b L = - x mdul Thus, the headers must satisfy the fllwing pattern: 0 = b 0 + b 1 + b b L-1 + b L mdul The checksum calculatin is carried ut in sftware using ne s cmplement arithmetic Internet Checksum Example Use Mdul Arithmetic Assume -bit wrds Use md 2-1 arithmetic b 0 =1100 = 12 b 1 =1010 = 10 b 0 +b 1 =12+10=7 md15 b 2 = -7 = 8 md15 Therefre b 2 =1000 Use Binary Arithmetic Nte 16 =1 md15 S: = 0001 md15 leading bit wraps arund b 0 + b 1 = =10110 = = =0111 =7 Take 1s cmplement b 2 = =1000

9 Plynmial Cdes Plynmials instead f vectrs fr cdewrds Plynmial arithmetic instead f check sums Implemented using shift-register circuits Als called cyclic redundancy check (CRC) cdes Mst data cmmunicatins standards use plynmial cdes fr errr detectin Plynmial cdes als basis fr pwerful errr-crrectin methds Binary Plynmial Arithmetic Binary vectrs map t plynmials Additin: (i k-1,i k-2,, i 2, i 1, i 0 ) i k-1 x k-1 + i k-2 x k i 2 x 2 + i 1 x + i 0 (x 7 + x 6 + 1) + (x 6 + x 5 ) = x 7 + x 6 + x 6 + x Multiplicatin: = x 7 +(1+1)x 6 + x = x 7 +x since 1+1=0 md2 (x + 1) (x 2 + x + 1) = x(x 2 + x + 1) + 1(x 2 + x + 1) = (x 3 + x 2 + x) + (x 2 + x + 1) = x 3 + 1

10 Binary Plynmial Divisin Divisin with Decimal Numbers divisr 3 35 ) qutient dividend remainder Plynmial Divisin x 3 + x + 1 ) x 6 + x 5 divisr Nte: Degree f r(x) is less than degree f divisr dividend = qutient x divisr +remainder x 3 + x = 3 x x x 6 + x + x 3 x 5 + x + x 3 x 5 + x 3 + x 2 x + x 2 x + x 2 + x = q(x) qutient x dividend = r(x) remainder Plynmial Cding Cde has binary generating plynmial f degree n k g(x) = x n-k + g n-k-1 x n-k g 2 x 2 + g 1 x + 1 k infrmatin bits define plynmial f degree k 1 i(x) = i k-1 x k-1 + i k-2 x k i 2 x 2 + i 1 x + i 0 Find remainder plynmial f at mst degree n k 1 q(x) g(x) ) x n-k i(x) r(x) x n-k i(x) = q(x)g(x) + r(x) Define the cdewrd plynmial f degree n 1 b(x) = x n-k i(x) + r(x) n bits k bits n-k bits

11 Plynmial example: k =, n k = 3 Generatr plynmial: g(x)= x 3 + x + 1 Infrmatin: (1,1,0,0) i(x) = x 3 + x 2 Encding: x 3 i(x) = x 6 + x 5 x 3 + x 2 + x x 3 + x + 1 ) x 6 + x 5 x 6 + x + x 3 x 5 + x + x 3 x 5 + x 3 + x 2 x + x 2 x + x 2 + x Transmitted cdewrd: b(x) = x 6 + x 5 + x b = (1,1,0,0,0,1,0) x ) The Pattern in Plynmial Cding All cdewrds satisfy the fllwing pattern: b(x) = x n-k i(x) + r(x) = q(x)g(x) + r(x) + r(x) = q(x)g(x) All cdewrds are a multiple f g(x)! Receiver shuld divide received n-tuple by g(x) and check if remainder is zer If remainder is nnzer, then received n-tuple is nt a cdewrd

12 Shift-Register Implementatin 1. Accept infrmatin bits i k-1,i k-2,,i 2,i 1,i 0 2. Append n k zers t infrmatin bits 3. Feed sequence t shift-register circuit that perfrms plynmial divisin. After n shifts, the shift register cntains the remainder Divisin Circuit + Encder fr g(x) = x 3 + x + 1 0,0,0,i 0,i 1,i 2,i 3 g 0 = 1 g 1 = 1 g 3 = 1 Reg 0 + Clck Input Reg 0 Reg 1 Reg = i = i = i = i Check bits: r 0 = 0 r 1 = 1 r 2 = 0 r(x) = x Reg 1 Reg 2

13 Undetectable errr patterns (Transmitter) b(x) + (Receiver) R(x)=b(x)+e(x) (Channel) e(x) Errr plynmial e(x) has 1s in errr lcatins & 0s elsewhere Receiver divides the received plynmial R(x) by g(x) Blindspt: If e(x) is a multiple f g(x), that is, e(x) is a nnzer cdewrd, then R(x) = b(x) + e(x) = q(x)g(x) + e(x) R(x) = q(x) + e(x) g(x) g(x) The errr is nt detected if g(x) divides e(x) Designing gd plynmial cdes Select generatr plynmial s that likely errr patterns are nt multiples f g(x) Detecting Single Errrs e(x) = x i fr errr in lcatin i + 1 If g(x) has mre than 1 term, it cannt divide x i Detecting Duble Errrs e(x) = x i + x j = x i (x j-i +1) where j>i If g(x) has mre than 1 term, it cannt divide x i If g(x) is a primitive plynmial, it cannt divide x m +1 fr all m up t the max. value f m (i-j) Fr example, x 15 + x 1 +1 will nt divide x k +1 fr any value f k belw 32,768

14 Designing gd plynmial cdes Detecting Odd Numbers f Errrs Suppse all cdewrd plynmials have an even # f 1s, then all dd numbers f errrs can be detected As well, b(x) evaluated at x = 1 is zer because b(x) has an even number f 1s This implies x + 1 must be a factr f all b(x) Pick g(x) = (x + 1) p(x) where p(x) is primitive Standard Generatr Plynmials CRC-8: CRC = cyclic redundancy check = x 8 + x 2 + x + 1 ATM CRC-16: = x 16 + x 15 + x = (x + 1)(x 15 + x + 1) Bisync CCITT-16: = x 16 + x 12 + x CCITT-32: HDLC, XMODEM, V.1 IEEE 802, DD, V.2 = x 32 + x 26 + x 23 +x 22 + x 16 + x 12 + x 11 + x 10 + x 8 +x 7 + x 5 + x + x 2 + x + 1

15 Hamming Cdes Class f errr-crrecting cdes A binary linear cde (k,n) takes a grup f k infrmatin bits and prduces n-bits cdewrd. Capable f crrecting all single-errr patterns Fr each m > 2, there is a Hamming cde f length n = 2 m 1 with n k = m parity check bits Redundancy m n = 2 m k = n m m/n 3/7 /15 5/31 6/63 m = 3 Hamming Cde Infrmatin bits are b 1, b 2, b 3, b Equatins fr parity checks b 5, b 6, b 7 b 5 = b 1 + b 3 + b b 6 = b 1 + b 2 + b b 7 = + b 2 + b 3 + b There are 2 = 16 cdewrds (0,0,0,0,0,0,0) is a cdewrd

16 Hamming (7,) cde Infrmatin Cdewrd Weight b 1 b 2 b 3 b b 1 b 2 b 3 b b 5 b 6 b 7 w(b) Parity Check Equatins Rearrange parity check equatins: 0 = b 5 + b 5 = b 1 + b 3 + b + b 5 0 = b 6 + b 6 = b 1 + b 2 + b + b 6 0 = b 7 + b 7 = + b 2 + b 3 + b + b 7 In matrix frm: b 1 b 2 0 = b 3 0 = b = H b t = 0 0 = b 5 b 6 All cdewrds must satisfy these equatins Nte: each nnzer 3-tuple appears nce as a clumn in check matrix H b 7

17 Chapter 3 Digital Transmissin Fundamentals RS-232 Asynchrnus Data Transmissin Recmmended Standard (RS) 232 Serial line interface between cmputer and mdem r similar device Data Terminal Equipment (DTE): cmputer Data Cmmunicatins Equipment (DCE): mdem Mechanical and Electrical specificatin

18 Pins in RS-232 cnnectr 1 13 (a) 1 25 (b) DTE Prtective Grund (PGND) Transmit Data (TXD) Receive Data (RXD) Request t Send (RTS) Clear t Send (CTS) Data Set Ready (DSR) Grund (G) Carrier Detect (CD) Data Terminal Ready (DTR) Ring Indicatr (RI) DCE Synchrnizatin Synchrnizatin f clcks in transmitters and receivers. clck drift causes a lss f synchrnizatin Example: assume 1 and 0 are represented by V vlts and 0 vlts respectively Crrect receptin Incrrect receptin due t incrrect clck (slwer clck) Data Data T T S S Clck Clck

19 Synchrnizatin (cnt d) Incrrect receptin (faster clck) Hw t avid a lss f synchrnizatin? Asynchrnus transmissin Synchrnus transmissin Data T S Clck Asynchrnus Transmissin Avids synchrnizatin lss by specifying a shrt maximum length fr the bit sequences and resetting the clck in the beginning f each bit sequence. Accuracy f the clck? Data bits Line idle Start bit Stp bit 3T/2 T T T T T T T Receiver samples the bits

20 Synchrnus Transmissin Sequence cntains data + clck infrmatin (line cding) i.e. Manchester encding, self-synchrnizing cdes, is used. R transitin fr R bits per secnd transmissin R transitin cntains a sine wave with R Hz. R Hz sine wave is used t synch receiver clck t the transmitter s clck using PLL (phase-lck lp) Vltage time