IMPROVEMENTS TO VOLTAGE SAG RIDE-THROUGH PERFORMANCE OF AC VARIABLE SPEED DRIVES

Transcription

1 IMPOVENTS TO VOLTAGE SAG IDE-THOUGH PEFOMANCE OF AC VAIABLE SPEED DIVES aj Narayanan, Dn Platt, Sarath Perera Integral Energy Pwer Quality Centre Schl f Electrical, Cmputer and Telecmmunicatins Engineering University f Wllngng NSW 2522 Abstract Vltage sags riginating in ac supply systems can cause nuisance tripping f variable speed drives (VSDs) resulting in prductin lss and restarting delays. In ac VSDs having an uncntrlled rectifier frnt-end, the effects f vltage sags n the dc link causing dc under-vltage r ac vercurrent faults initiate the tripping. This paper suggests mdificatins in the cntrl algrithm in rder t imprve the sag ride-thrugh perfrmance f ac VSDs. The prpsed strategy recmmends maintaining the dc link vltage cnstant at the nminal value during a sag by utilising tw cntrl mdes, viz. (a) by recvering the kinetic energy available in the rtating mass at high mtr speeds and (b) by recvering the magnetic field energy available in the mtr winding inductances at lw speeds. By cmbining these tw mdes, the VSD can be cnfigured t have imprved vltage sag ride-thrugh perframance at all speeds. 1. INTODUCTION Slid State AC Variable Drives have already becme an integral part f many prcess plants and their usage is n the rise in industrial, cmmercial and residential applicatins [1]. It is prjected that, abut 5-6% f the electrical energy generated will be prcessed by slid state pwer electrnic devices by the year 21 cmpared t the present day levels f 1-2% [2]. Hwever, VSDs are vulnerable t vltage sags [3-4]. Vltage sag is a mmentary reductin f vltage and is usually characterised by its magnitude and duratin with typical values f magnitude between.1-.9 p.u. and duratin ranging frm.5 cycles t 1 minute [5-7]. Vltage sags are reprted t be the mst frequent cause f disrupted peratins f many industrial prcesses [3]. This paper cncentrates n AC VSDs with a threestage tplgy (Fig. 1) viz., a dide bridge rectifier frnt-end, a dc link capacitr and a PWM inverter [3, 8-9]. 3 ph AC Supply C AC Mtr Figure 1. AC VSD with a VSI cnfiguratin In VSDs having an uncntrlled rectifier frnt-end, variatin in the incming ac supply vltage is usually reflected in the dc link behaviur. In the case f a balanced three-phase sag, the dc link vltage reduces, leading t an under-vltage trip. Als when the ac supply returns t nrmal cnditins, the VSD can trip due t the ac side ver-current as a result f Lad high charging current f the dc bus capacitr [3]. In the case f an unbalanced sag, the ripple in the dc bus vltage increases and the VSD can trip especially when the sag magnitude and the lad trque are very high. It is reprted that, a sag f magnitude mre than 2% (i.e. ac vltage falls belw.8 p.u.) and duratin mre than 12 cycles is fund t trip VSDs [2]. The impact f unbalanced sag is less severe n the VSD perfrmance and hence the ride-thrugh behaviur when subjected t a balanced three-phase sag alne is analysed here. 2. CONVENTIONAL STATEGIES 2.1 Types f available strategies Three types f vltage sag mitigatin techniques are reprted in literature. They are, (a) hardware mdificatins (eg. increasing ac side inductrs, dc bus capacitance) (b) imprvement in pwer supply cnditins (eg. use f alternative pwer supplies such as a mtr-generatr set, Uninterruptable Pwer Supply) and (c) mdifying cntrl algrithm. In this paper, strategies invlving imprvements in the cntrl strategy alne are cnsidered due t the fllwing advantages, (a) n additinal space is required and (b) since nly sftware mdificatins are invlved and hence cst increase is relatively negligible. 2.2 Cntrl algrithm based strategies One cntrl algrithm based technique which ensures maximum trque availability t the mtr suggests cmpensating the mdulatin index and statr frequency crrespnding t the instantaneus dc link vltage during a sag [1]. Hwever, the dc link

2 characteristics are nt imprved and the drive can still trip when a sag ccurs. Anther strategy suggests maintaining the supply utput f the VSD synchrnised with the inductin mtr flux and perate the mtr at zer slip during a sag s that the machine can be restarted when nrmal ac supply returns [9,11]. Since nly a minimal pwer is drawn frm the dc link, the rate f dc vltage reductin is lw. Hwever, the sag ride-thrugh perfrmance f the VSD depends n the dc link vltage at the instant f ac supply recvery. Finally, anther cntrl strategy recmmends maintaining the dc bus vltage at a required level by recvering the kinetic energy available in the rtating mass during a sag [12]. With this type f cntrl, the mtr decelerates twards zer speed at a rate prprtinal t the amunt f energy regenerated and the shaft lad n the mtr. But, since the kinetic energy decreases prprtinal t the square f the speed, the sag ride-thrugh perfrmance f the VSD under this strategy is highly speed dependent and it wrks well nly at high mtr speeds. If the vltage sag persists even after the mtr has cme t standstill, the capacitr vltage will start t reduce and the VSD will trip due t either under-vltage r ver-current faults. 3. EFFECT OF VOLTAGE SAG ON AC VSDs Here, the impact f a symmetrical three-phase sag n the VSDs cntrlling a synchrnus reluctance mtr (SM) and an inductin mtr (IM) will be verified. Field rientatin cntrl (FOC) is cnsidered. The VSDs were mdeled in MATLAB TM with details as discussed belw. 3.1 Mathematical mdeling f AC VSDs In field riented cntrl f ac mtrs, the three phase mtr currents are transfrmed int tw rthgnal cmpnents in a synchrnus frame f reference which mves with respect t the statr crdinates, and they are defined as i sq, the trque prducing cmpnent (quadrature axis current) and i sd, the flux prducing cmpnent (direct axis current) [13]. The main difference in the cntrl f IMs as cmpared t the SMs is due t the rientatin f the flux axis. In the case f an SM, the synchrnus frame f reference is the same as the rtr axis, which can be kept track by a rtr psitin sensr whereas, in the case f IMs, mre cmplicated cmputatins are invlved. The functinal blck diagrams f SM and IM VSDs under field rientatin are shwn in Figures 2 and 3 respectively. In bth cases, the speed reference ( ref ) and the magnetising current reference (i mref ) frm the main cntrl inputs. The peratin f bth VSDs is almst identical and the functins f varius cntrl blcks are as fllws: The Trque / Cnversin blck calculates the trque prducing current set pint (i sqset ) frm the set trque reference ( ). The Cntrl blck calculates the statr vltage set pints in field crdinates (V sdref and V sqref ). The C-rdinate Transfrmatin blck transfrms the selected vltage references (V sdref and V sqref ) frm the synchrnus crdinates t the statr c-rdinates. The Switching Vectr Selectin blck selects the apprpriate perating sequence fr the inverter switches, based n the vltage vectr psitin in the cmplex plane. ref Cntrl Trque Cnversin i sd T M, isqref Cntrl V sdref V sqref Crdinate Transfrmatin e -jε V realref V imagref SM Mdel e -jε i s V s Switching Vectr Selectin 3ϕ Supply Figure 2 Functinal blck diagram f an SM VSD Figure 3 Functinal blck diagram f an IM VSD 3.2 Behaviur f VSDs n a sag cnditin Here, the impact f vltage sag n the behaviur f bth SM and IM VSDs f 5.5 kw rating will be discussed. A symmetrical three-phase vltage sag f.5 p.u. and duratin 1 secnd was applied when the mtrs were running at a steady-state speed f 12 rad/s perating with a lad trque (T L ) f 18 Nm (half the rated lad). The inverter switching frequency was kept at 5 khz. The bservatins are as fllws: Behaviur f SM VSD during a sag i m ref ref Capacitr vltage (V bus ) 2 i m Flux Cntrl Cntrl Trque Cnversin i m T M, isqref Cntrl C AC Mtr Capacitr charging current (I in ) (a) (V bus ) (b) (I in ) Figure 4. DC bus characteristics f SM VSD in the presence f a three-phase vltage sag V sdref V sqref Crdinate Transfrmatin e -jρ V realref V imagref Inductin Mtr Mdel e -jρ i s V s Switching Vectr Selectin S 3ϕ Supply C AC Mtr S

3 The cntrl system has ensured that the SM speed, trque and flux were unaffected during the sag cnditin. Hwever, the dc bus characteristics, viz. the capacitr vltage (V bus ) and the capacitr charging current (I in ), are affected the mst during the sag (Fig. 4). The duble-ended arrw indicates the sag perid. It is bserved frm the abve figures that initially there is n flw f capacitr charging current (I in ) because the rectifier dides are reverse biased and the capacitr discharges the stred energy t the mtr. Once V bus becmes less than the ac supply peaks, the capacitr is charged unifrmly by all the three phases during the sag. When the ac supply returns t nrmal, a very high current pulse is bserved in I in with its magnitude increasing with the sag magnitude, but it is usually many times the current rating f the rectifier dides. This high current pulse results in the versht f V bus which gradually returns t nrmal by discharging t the inverter lad (Figure 4 (a)) Behaviur f IM VSD during a sag Capacitr Vltage (V bus ) Capacitr charging current (I in ) 85% f the nminal dc vltage [11]. Similarly, the ac ver-current trip is usually set in the range f 2% t 25% f the rated mtr current. 4. POPOSED CONTOL STATEGY Since the nuisance tripping f the VSD during a vltage sag is triggered by the dc bus characteristics, the prpsed strategy, which is an extensin f the cntrl strategy prpsed in [12], recmmends maintaining the dc link vltage at the nminal level by recvering the kinetic as well as magnetic field energy present in the ac mtr in rder t imprve the sag ride-thrugh perframnce. 4.1 Energy levels present in an ac VSD The typical levels f energy present in an ac VSD cntrlling a 5.5 kw mtr are given belw: Kinetic energy at rated speed = ½ J 2 = 2835 J (1) Magnetising energy = ½ LI 2 = 4.12 J (2) Fr a 5% ripple, the dc link capacitr C is chsen as 1 µf, and Energy stred in C = ½ CV 2 = 172 J (3) (a) V bus (b) I in Figure 5. DC bus characteristics f IM VSD in the presence f a three-phase vltage sag When subjected t the three-phase sag, the behaviur f the IM VSD was fund t be identical t that f the SM VSD. The speed and trque perfrmances are nt affected whereas the impact f the sag is bserved in the dc link characteristics. The capacitr vltage (V bus ) and the capacitr charging current (I in ) are shwn in Figures 5 (a) and (b) respectively. 3.3 easns fr VSD tripping during a sag Frm Figures 4 and 5, it can be bserved that, the dc bus vltage reaches a lw level depending n the magnitude f the sag and the lad, which can cause the VSD t trip due t an under-vltage fault. When the sag cnditin is ver, very high capacitr recharging current (I in ) results and in spite f being limited by the circuit impedances, it is usually several times the current handling capacity f the rectifier dides. In such a case, the VSD can trip due t the ver-current. In rder t prtect the VSD hardware, the undervltage trip setting is typically kept between 7% and 4.2 Cntrl sequence Frm the numerical quantities given in Sectin 4.1 it is evident that there is a cnsiderable amunt f energy available in the rtating mass and a small amunt in the winding inductances. Bth these surces can be utilised t maintain the dc bus vltage at a desired level during a sag. Even thugh the available magnetisatin energy is relatively small, nce this energy is recvered, there will be n currents in the winding inductances and hence n energy drain frm the link capacitr. In rder t establish an efficient and simple cntrl system, it is better t attempt energy recvery frm ne surce at a time. The fact that the mtr requires magnetic field in rder t functin as a generatr makes kinetic energy the first chice f energy surce that can be recvered. When the mtr functins as a generatr, its speed falls mre rapidly than nrmal casting. When the mtr speed reaches very lw values, the stred kinetic energy reaches negligible prprtins and the mtr cannt deliver the energy required by the dc bus. There is n advantage in reducing the speed belw sme limit. Hence, a cutff speed limit is defined (here 1% f the mtr base speed) belw which, this strategy wuld attempt t recver the energy available in the machine inductances.

4 4.3 Cntrl Sequence and Flw-Charting The flwchart illustrating the VSD cntrl during a vltage sag cnditin is shwn in Figure 6. Cntrl: Nrmal Operatin Bus Vltage Cntrl: ecver Kinetic Energy Figure 6. VSD cntrl sequence during vltage sag cnditin It can be bserved that, there are three distinct situatins invlved with respect t the cntrl f the VSD. They are summarised as fllws: Cntrl Situatin 1 (): (N Vltage sag) VSD peratin with nrmal speed cntrl. Cntrl Situatin 2 (): (Vltage sag and mtr speed > cut-ff speed) DC bus vltage cntrl by recvering lad kinetic energy. Cntrl Situatin 3 (CS3): (Vltage sag and mtr speed < cut-ff speed) DC bus vltage cntrl by recvering magnetic field energy. 4.4 Prpsed additinal cntrl lps In rder t maintain the dc link vltage at the required level during the sag, additinal cntrl lps are necessary within the VSD cntrl system Kinetic energy recvery Kinetic energy f the rtating mass can be recvered by perating the mtr as a generatr. Electrically this can be achieved by reversing the flw f energy frm the ac mtr t the dc bus by perating the mtr at the rated flux. This peratin is explained by the pwer balance equatin (4). V bus I ut = 2 3 (V sd i sd + V sq i sq ) (4) where I ut is the dc utput current. Frm equatin (4), it can be nted that, by maintaining the flux (i sd ) cnstant, if i sq is reversed, the flw f the dc current I ut can be reversed frm N N Incming 3 φ Supply Vltage Is Sag> 1 % Yes Is < 1% Yes CS3 Bus Vltage Cntrl: ecver Magnetising Energy Actual ( ) the mtr t the dc bus which will bst the capacitr vltage. This is the basis f the cntrl utilised in Cntrl Situatin 2. In a sag cnditin, the recvery f kinetic energy must be cntrlled s that nly the required amunt f energy is recvered frm the mtr t maintain the capacitr vltage at the desired value. This can be achieved by the use f a clsed lp PI cntrller, which mnitrs the capacitr vltage against the set reference and prduces a suitable reverse trque reference. A new PI cntrller (Bus Vltage Cntrller 1) is cnfigured in the VSD cntrl system fr this purpse. Figure 7 shws the sequence f peratin f the cntrl system during a sag at high mtr speeds. ref VBusref ref Cntrller Bus Vltage Cntrller 1 Zer Trque eference ated magnetising current reference Bus Vltage Cntrller 2 CS3 CS3 Trque Cnversin Figure 7 Cntrl lps used t recver kinetic energy Since the basis f speed and trque cntrl peratin is identical fr IM and SM VSDs, this cntrl scheme is applicable in bth the cases Magnetic field energy recvery ref ref Cntrller Bus Vltage Cntrller 1 ated magnetising current reference Trque i sqref Cnversin Figure 8 Cntrl lps used t recver magnetic field energy If a vltage sag ccurs when the mtr speed is belw the cut-ff limit (Cntrl Situatin 3), the magnetising energy stred in the mtr inductances can be recvered t bst the bus capacitr vltage. This energy recvery can be achieved by lwering the magnetising current (which is i sd fr an SM and i sqref

5 i m fr an IM). There is n trque applied during this cntrl situatin (i.e. i sq =). Frm equatin (4), it can be realised that this peratin results in the reversal f flw f the current I ut frm the mtr t the dc bus, which will bst the capacitr vltage V bus. In rder t achieve a cntrlled recvery f this magnetising energy, anther PI cntrller (Bus Vltage Cntrller 2) which mnitrs V bus against the set reference is emplyed t cntrl (reduce) the flux reference. Figure 8 shws the sequence f peratin. 5. ESULTS Abve cntrl strategies were implemented fr a case where the VSDs were subjected t a 5% three-phase sag. Fllwing sectins illustrate the results. and the results are analysed as fllws: 5.1 SM VSD respnse (rad/s) isd (A) Mtr speed ( ) ref = 6 rad/s Cut-ff speed = 15.7 rad/s (a) -2 Magnetising current (i sd ) = 9A (c) i sd T M (Nm) Capacitr vltage (V bus ) V busref = 587 V V bus 5 Mtr trque (T M ) T LT = 54 Nm T L = 18 Nm (b) T M Capacitr charging current (I in ) (d) I in Figure 9. Behaviur f SM VSD during dc bus vltage cntrl The vltage sag was applied t the SM VSD when the mtr was perating at a mderate speed f 6 rad/s. The characteristics f SM speed (), trque (T M ), magnetising current (i sd ), capacitr charging current (I in ) and the capacitr vltage (V bus ) are shwn in Figure 9. The duble-ended arrw indicates the sag cnditin and the kinetic and magnetising energy recvery perids are indicated as and respectively. It can be seen that the bus vltage is maintained at a level clse t the set reference by initially recvering the kinetic energy as lng as the mtr speed is abve the cut ff speed and then by recvering the energy available in the inductances (by reducing i sd ). The mtr speed is fund t drp mre rapidly due t the regenerative peratin and then cast at a slwer rate during the energy recvery frm the mtr windings. Oscillatins are bserved in the mtr trque respnse because f the nnlinear relatinship between trque and the bus vltage, i.e. the trque requirement increases as the mtr speed decreases. Once the supply returns t nrmal, the mtr flux reaches its rated level and the mtr starts t accelerate twards the set speed. The capacitr charging current (I in ) is fund t be within acceptable limits n nrmal ac supply recvery. 5.2 IM VSD respnse When cntrlled by the prpsed strategy, the respnse f the IM VSD was fund t be similar t that f SM VSD at high mtr speeds (i.e. Cntrl Situatin 2). The mtr was cntrlled under regeneratin mde and the dc link vltage was maintained arund the set level (587 V). The mtr speed was fund t reduce twards zer. Hwever, belw the cut-ff speed, while trying t recver energy frm the winding inductances, the peratin f the cntrl system was fund t be different frm that f SM. The bservatins and the analysis during Cntrl Situatin 3 are as given belw: Observatins while recvering magnetisatin energy The respnse f the IM VSD, viz. speed (), magnetisatin current (i m ), statr d-axis current (i sd ), capacitr utput current t the inverter (I ut ), capacitr vltage (V bus ) and the capacitr charging current (I in ) during the sag cnditin are shwn in Figure 1. When the sag is sensed, the magnetising current (i m ) is fund t reduce t zer within a few millisecnds. When the mtr flux decreases, a high negative current pulse (f abut 8 A) is bserved in i sd characteristics. Als, it is bserved that, the dc current I ut, instead f being fed back int the capacitr, has been drawn ut f the capacitr by the mtr. This has resulted in the reductin f capacitr vltage (V bus ) rather than being maintained at the set level. As a result, when nrmal ac supply returns, large current pulses are bserved in the capacitr charging current (I in ). During the sag perid, the mtr speed is fund t have casted twards zer

6 and reversed further which ccurs nly in the case f lads such as hists r cranes whereas with frictinal lads, the mtr stps after reaching zer speed. (rad/s) i sd (A) Mtr speed ( ) ref = 12 rad/s (a) Statr d-axis current (i sd ) i mref = 9A (I ut ) i m (A) Magnetising current (i m ) i mref = 9A -1 (b) i m Capacitr utput current (I ut ) dim isd = im + T dt (5) L dim ( 1+ σ r ) dim disd = = Lm dt dt (5(a)) Lm (1 + σ r ) i sq = Tim( m ) = ( m ) (6) i rd Lm dim = (7) dt Lm im i rq = ( m ) (8) i rd (A) 1 tr d-axis current (i rd ) (c) i sd Capacitr Vltage (V bus ) (d) I ut Capacitr charging current (i m ) Figure 11. i sd respnse during flux change V bus (f) I in Figure 1. IM VSD espnse during attempted recvery f magnetising energy At the end f the sag, the flux returns t nrmal rated value and the mtr starts t accelerate twards the set speed. The mtr perates in regeneratin mde until the mtr reaches zer speed and thereafter nrmal mtring peratin starts. Because f this regeneratin, the capacitr vltage V bus is fund t increase t a higher value than nrmal. This excess vltage can be cntrlled using the pre-charge resistrs available in a standard VSD. Obviusly, it is clear frm the simulatin results that, the energy recvery frm the magnetising inductances has nt wrked with an IM VSD and the reasns fr this behaviur are analysed further easns fr the inability t recver magnetising energy frm IM The statr and rtr currents f an inductin mtr in field c-rdinates are given as fllws [13]: As per equatin (5), the rtr flux f an inductin mtr (i m ) is cntrlled by i sd. During steady-state flux cnditins, the average value f i sd is the same as that f i m, but a little excess (d isd ), as given by equatin (5(a)), is drawn frm the dc bus. The crrespnding energy is dissipated in the rtr circuit (cmpare equatins (5(a)) and (7)). This is verified by the respnse f i sd and i rd (refer Figures 1(c) and 11). Again, it can be realised frm equatin (5) that, if the mtr flux is reduced t zer in a duratin shrter than the rtr time cnstant (T ), i sd wuld increase beynd its nminal level cnsuming mre pwer frm the dc link leading t a faster discharge f the dc bus capacitr. This explains the behaviur f the IM VSD during cntrl situatin CS3. Hence, during the sag, it is nt a gd idea t reduce the inductin mtr flux ver a duratin shrter than the rtr time cnstant. An ptimum dc bus vltage cntrl can be achieved by reducing the flux t zer in a duratin marginally lnger than the rtr time cnstant and this can be achieved by an pen lp flux cntrl scheme. The advantage f this cntrl is that, the energy drawn frm the dc bus capacitr wuld be less than during cnstant flux cntrl and wuld cntinue t reduce further. Hence, the dc bus vltage wuld reduce at a lwer rate, which will enable the VSD t ridethrugh sags f lnger duratins at lw mtr speeds until zer speed.

7 6. CONCLUSIONS The prpsed strategy was fund t wrk satisfactrily in the case f the SM VSD. It was fund that the dc link characteristics have imprved and the VSD can ride thrugh sags ver a wide speed range. Hwever, in the case f an IM VSD, it is bserved that this strategy can verride a sag nly at high mtr speeds. It was verified that the magnetic field energy gets dissipated acrss the rtr in the case f an IM. Thus, an pen lp flux reductin at a rate higher than the rtr time cnstant will imprve the sag ride-thrugh perfrmance f an IM VSD at lw mtr speeds. The transitin between varius cntrl lps during the different cntrl situatins was fund t be smth. The main advantage f this strategy is that the input rectifier is nt in cnductin during a vltage sag and hence the perfrmance f the VSD is independent f the magnitude f the sag. Due t the same reasn, the VSD lad is decupled frm the mains and des nt exacerbate the supply situatin n the mains. ACKNOWLEDGENTS The financial supprt received frm the Integral Energy Pwer Quality Centre is gratefully acknwledged by the first authr. EFEENCES [1] Puttgen, H.B., uaud, D., Wung, P., ecent Pwer Quality elated Small t Intermediate ASD Market Trends, PQA 91, (First Internatinal Cnference n Pwer Quality: End-Use Applicatins and Perspective), Oct 15-18, 1991, Paris, France. [2] Sarmient, H. G., Estrada, E., A Vltage Sag Study in an Industry with Adjustable Drives, Prc. Industrial and Cmmercial Pwer Systems Technical Cnference, Irvine, CA, USA, May 1994, pp [3] Cllins Jr., E.., Mansr A., Effects f Vltage Sags n AC Mtr Drives, Prc. IEEE Annual Textile, Fiber and Film Industry Technical Cnference Greenville, SC, USA, May 1997; pp 1-7. [4] Mansr, A., Cllins Jr., E.., Mrgan,. L., Effects f Unsymmetrical vltage sags n Adjustable Drives, Prc. The 7 th Annual Cnference n Harmnics and Quality f Pwer, Las Vegas, NV, USA, Octber 1996, pp [5] Tang, L., Lamree, J., McGranaghan, M., Mehta H., Distributin System Vltage Sags: Interactin with Mtr and Drive Lads, IEEE Pwer Engineering Sciety Transmissin and Distributin Cnference, Chicag, IL, USA, April 1994, pp 1-6. [6] Melhrn, C. J., Vltage Sags: Their Impact n the Utility and Industrial Custmers, Prc. IEEE Transactins n Industry Applicatins, V 34, n 3, May/June 1998, pp [7] Dugherty, J.G., Stebbins, W.L., Pwer Quality: A Utility and Industry Perspective, Annual Textile, Fiber & Film Industry Technical Cnference, Greenville, SC, USA, May 1997, pp 1-1. [8] Vas, P., Drury, W., Electrical Machines and Drives: Present and Future, Industrial applicatins in Pwer Systems, Cmputer Science and Telecmmunicatins, Bari, Italy, v 1, May 1996, pp [9] David, A., Lajie-Mazenc, E., Maintaining the Synchrnism f an AC Adjustable Drive during Shrt Supply Interruptins fr an Optimal and Autmatic Sft estart, IEEE Internatinal Sympsium n Industrial Electrnics, June 1-3, 1993, Budapest, Hungary, (Cat. N. 93TH54-5) pp [1] David, A., Lajie-Mazenc, E., Sl, C., ide thrugh Capability f AC Adjustable Drives in regards t Vltage Dips n the Distributin Netwrk 5th Eurpean Cnference n Pwer Electrnics and Applicatins, Brightn, UK, September 1993, v 6, n 377, pp [11] David, A., Lajie-Mazenc, E., Sl, C., Sft estart f an Adjustable Drive After a Shrt Discnnectin Withut Any Mechanical Sensr, IEE Internatinal Cnference n Electrical Machines And Drives, Oxfrd, UK, Sept. 93, pp [12] Hltz, J., Ltzkat W., Cntrlled AC Drives with ide-thrugh Capability at Pwer Interruptin, Industrial Applicatins Sciety Annual Meeting, Trnt, Ontari, Can., v 1, Octber 1993, pp [13] Lenhard, W., Cntrl f Electric Drives, Springer, [14] Vas, P., Vectr Cntrl f AC Machines, Oxfrd Science Publicatins, 199.