PRESIDENCY UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING EE 310: VLSI System Laboratory. Contents

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1 PRESIDENCY UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING EE 310: VLSI System Laboratory Contents Experiment No Name of The Experiments. Page Experiment-1 INTRODUCTION TO CIRCUIT SIMULATION USING SPICE 1 Experiment-2 Experiment-3 Experiment-4 Experiment-5 Experiment-6 Experiment-7 Experiment-8 Experiment-9 ANALYSIS OF CMOS INVERTER USING PSPICE SIMULATION OF CMOS NAND GATE USING PSPICE SIMULATION OF CMOS NOR GATE USING PSPICE INTRODUCTION TO LAYOUT DESIGN USING MICROWIND LAYOUT DESIGN OF A CMOS INVERTER USING MICROWIND LAYOUT DESIGN OF A 2-INPUT CMOS NOR GATE FOR EQUAL RISE TIME AND FALL TIME LAYOUT DESIGN OF A 2-INPUT CMOS NAND GATE FOR EQUAL RISE TIME AND FALL TIME VLSI DESIGN USING SCHEMATIC CAPTURE Page 1

2 PRESIDENCY UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING EE 310: VLSI Systems Laboratory EXPERIMENT 1: INTRODUCTION TO CIRCUIT SIMULATION USING SPICE Objectives: To familiarize with SPICE simulator. To learn how to simulate and analyze simple circuit using spice To learn how to measure the rise time, fall time for a circuit. Introduction: SPICE (Simulation Program with Integrated Circuit Emphasis) is a very powerful and probably the most widely used simulator for electrical and electronic circuits. This experiment aims at introducing you to some of the capabilities of the SPICE program. It can perform nonlinear dc, nonlinear transient, linear ac analysis and other types of simulations. The circuits may contain resistors, capacitors, inductors, mutual inductors independent voltage and current sources, four types of dependent sources, transmission lines, and four most common semiconductor devices: diodes, BJTs, JFETs, and MOSFETs. This experiment will use SPICE s dc and transient analysis capabilities to analyze circuits based on resistor, capacitor and inductor. Rules of writing code for circuit simulation: Use the following as a template to writing a description (Line starts with * is considered as a comment): Title(first line is ignored as a comment) * 1.Circuit description: *2.Model specification: *3.Input signals: *4.Simulation modes: *5.Generating outputs *6.End of simulation:. end Page 2

3 1.Circuit Description: General Form: Devicename n1 n2 Value eg: r k r k Devicename is rxxx for a registor, cxxx for a capacitor.n1, n2 are the node numbers of the device terminals.value is the resistance (in ohms) or capacitance (in Farads) of the device. 2.Model specification: For resistor and capacitor model name is not necessary. 3.Input signals DC Source : General Form (for DC): Sourcename n1 n2 dc value (for AC): Sourcename n1 n2 pulse (V1, V2, TD, TR, TF, PW, PER) eg. vdd 4 0 dc 5 vclock 1 0 pulse(0,5,1ns,2ns,100ns,200ns) Where,sourcename is the name of the source,n1 and n2 are the positive and negative node of the voltage source, value is the voltage, V1 is Initial voltage, V2 is the pulsed voltage,td is delay time, TR is rise time,tf is fall time, PW is pulse width,per is the pulse period 4.Simulation Modes SPICE can perform various types of analysis; we are concerned just with two: the transient analysis and the dc analysis modes. General form(for transient analysis):. tran tstep tstop tstart (For DC analysis):. dc Source name vstart vstop vincr eg..tran 1ns 0 100ns.dc vin Page 3

4 Where,tstep is the increment time (in seconds ),tstop is the finish time,tstart is the initial time (defaults to zero),sourcenme is the name of the voltage source to be varied,vstart is the initial value,vstop is the final value,vincr is the increment or step value. 5.Generating Output General Form:. plot Mode out1 out2.out8. print Mode out1 out2 out8 eg :.plot dc v(2) v(5) v(7) i(vname). plot tran v(1) v(2) (0,5) Where,Mode specifies the analysis mode, and out1 out2 is the list of nodes to be monitored and can have one of the following three forms:1) V (n1) specifies the voltage at node n1 with respect to ground. 2)V (n1, n2), specifies the voltage difference between node n1 and n2. 3) i(vname), specifies the current flowing in the independent voltage source named vname. Filter Circuit: 50Ω V1 1nF Fig:1 Page 4

5 Code for analyzing fig 2.1 Codes for inverter: V1 1 0 DC 5V R C n.DC V tran 1ns 0 100ns.plot dc v(2). plot tran v(2).end Procedure: 1) Write the above code for the circuit of fig1 in PSPICE and test the functionality of the circuit by transient analysis. 2) Run the above program in dc analysis mode and observe output voltage. This is the transfer characteristic of the circuit. 3) From the transient analysis determine the values of rise time and fall time of the output voltage. Report: 1. What is rise time and fall time for the output of a system? 2. Write a SPICE source file for the simple filter circuit shown fig1 and produce a transient analysis of the circuit over a period of 1us with an increment of 10ns.Determine the rise and fall times from the plot. Page 5

6 PRESIDENCY UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING EE 310: VLSI Systems Laboratory EXPERIMENT NO. 2: ANALYSIS OF CMOS INVERTER USING PSPICE Objectives: To learn how to simulate and analyze MOSFET circuit Characteristics analysis of a CMOS inverter. To learn how to measure the rise time, fall time for a CMOS inverter. THE CMOS INVERTER Consider the circuit of the CMOS inverter below. When the input is high the pulldown device (Mpd) is on but V gs of the p-channel device is zero and hence the pullup device (Mpu) is off such that the output pulls all the way to ground. When the input is low, V gs of the p-channel device is V dd and hence it is on. The pull down is off and the output rises to V dd. 1 Vdd MPU 2 Vin MPD 3 CLoad 0 Fig.2.1 Rules for writing MOSFET statement: General Form: Device name is n1 n2 n3 n4 model name 1 w.model model name NMOS (P1=V1 P2=V Pn=Vn).MODEL model name PMOS (P1=V1 P2=V Pn=Vn) Page 6

7 eg. mpu penh l=3u w=10u mpd nenh l=3u w=4u.model IRF250 NMOS (level=3 w=4u l= 3u vto=1.0 tox=470e-10 nsub=38e14 + cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=0.33 kp=30e-6 ).MODEL IRF150 PMOS (level=3 w=10u l=3u vto=-1.0 tox=470e-10 nsub=8.7e14 + cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33 kp=12e-6) Where,Devicename is mxxx,the ordering of the nodes is drain, gate, source, and substrate, l and w are channel length and width (in meters ) respectively Code for analyzing fig 2.1 Codes for inverter: V1 1 0 DC 5V V2 2 0 PULSE (0 5 3ns 3ns 3ns 20ns 40ns) CL PF MPU IRF150 MPD IRF250.MODEL IRF250 NMOS (level=3 w=4u l= 3u vto=1.0 tox=470e-10 nsub=38e14 + cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=0.33 kp=30e-6 ).MODEL IRF150 PMOS (level=3 w=10u l=3u vto=- 1.0 tox=470e-10 nsub=8.7e14 + cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33 kp=12e- 6).DC V TRAN 1ns 80ns.PROBE V(2,0) V(CL) ID(MPD) ID(MPU).END Page 7

8 Procedure: 4) Write the above code for CMOS INVERTER in PSPICE and test the functionality of the gate by transient analysis. 5) Run the above program in dc analysis mode and observe output voltage. This is the transfer characteristic of the inverter. From the curve measure the inversion voltage. 6) From the transient analysis determine the values of rise time and fall time of the output voltage. Observe the transistor currents along with input and output voltages. The smaller current spikes during logic transition cause switching power loss. 7) Change the width (w) of NMOS to 10u and run the program. Observe the dc transfer characteristic and measure the inversion voltage and from the transient analysis determine the values of rise time and fall time of the output voltage. You do not need to observe transistor currents in this step. 8) Change the width (w) of NMOS back to 4u and that of PMOS to 20u and run the program. Observe the dc transfer characteristic and measure the inversion voltage and from the transient analysis determine the values of rise time and fall time of the output voltage. Notice the change in three cases. Report: 1) What is pull down and pull up device? 2) Include the results and figures obtained in procedure. 3) Comment on the variation of output with the change of width of the PMOS and NMOS. Page 8

9 PRESIDENCY UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING EE 310: VLSI Systems Laboratory EXPERIMENT NO. 3: SIMULATION OF CMOS NAND GATE USING PSPICE Objectives: To learn how to simulate and analyze MOSFET circuit Characteristics analysis of a CMOS NAND gate. To learn how to measure the rise time, fall time for a CMOS NAND gate. To see the variation of rise time and fall time with the variation of width of the MOSFET CMOS NAND GATE: NAND and NOR gate are two basic gates. Since all other logics gates can be performed using one of them, they are also referred to as universal logic gates.fig3.1 shows a 2 input CMOS NAND gate, where 2 PMOS are connected in parallel and 2 NMOS are connected in series. In this experiment we show the transient analysis of a CMOS NAND gate and the variation of output with the change in the width of the transistor. Page 9

10 Code to simulate fig 3.1 Codes for NAND gate: Vdd 1 0 DC 5V Vin1 2 0 PULSE (0 5 3ns 3ns 3ns 10ns 40ns) Vin1 2 0 PULSE (0 5 3ns 3ns 3ns 20ns 40ns) MP IRF150 MP IRF150 Mn IRF250 Mn IRF250.MODEL IRF250 NMOS (level=3 w=4u l= 3u vto=1.0 tox=470e-10 nsub=38e14 + cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=0.33 kp=30e-6 ).MODEL IRF150 PMOS (level=3 w=10u l=3u vto=- 1.0 tox=470e-10 nsub=8.7e14 + cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33 kp=12e- 6).TRAN 1ns 80ns.PROBE V(2) V(3) V(5).END Procedure : 9) Write the above code for CMOS NAND gate in PSPICE and test the functionality of the gate by transient analysis. 10) From the transient analysis determine the values of rise time and fall time of the output voltage. 11) Change the width (w) of NMOS to 10u and run the program. From the transient analysis determine the values of rise time and fall time of the output voltage. 12) Change the width (w) of NMOS back to 4u and that of PMOS to 20u and run the program. From the transient analysis determine the values of rise time and fall time of the output voltage. Report : 4) What is CMOS NAND gate? What logic function does the CMOS NAND gate perform? 5) Comment on its characteristics of interest. 6) Include the results and figures obtained in procedure. Page 10

11 PRESIDENCY UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING EE 310: VLSI Systems Laboratory EXPERIMENT NO. 4: SIMULATION OF CMOS NOR GATE USING PSPICE Objectives: Characteristics analysis of a CMOS NOR gate. To learn how to measure the rise time, fall time for a CMOS NAND gate. To see the variation of rise time and fall time with the variation of width of the MOSFET A comparison between NOR and NAND gate. CMOS NOR GATE: Fig 4.1 shows a 2 input CMOS NOR gate, where 2 PMOS are connected in series and 2 NMOS are connected in parallel. In this experiment we show the transient analysis of a CMOS NOR gate and the variation of output with the change in the width of the transistor. Code to simulate fig 4.1 Fig. 4.1 Page 11

12 Codes for NAND gate: Vdd 1 0 DC 5V Vin1 2 0 PULSE (0 5 3ns 3ns 3ns 10ns 40ns) Vin1 2 0 PULSE (0 5 3ns 3ns 3ns 20ns 40ns) MP IRF150 MP IRF150 Mn IRF250 Mn IRF250.MODEL IRF250 NMOS (level=3 w=4u l= 3u vto=1.0 tox=470e-10 nsub=38e14 + cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=0.33 kp=30e-6 ).MODEL IRF150 PMOS (level=3 w=10u l=3u vto=- 1.0 tox=470e-10 nsub=8.7e14 + cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33 kp=12e- 6).TRAN 1ns 80ns.PROBE V(2) V(3) V(5).END Procedure: 13) Write the above code for CMOS NOR gate in PSPICE and test the functionality of the gate by transient analysis. 14) From the transient analysis determine the values of rise time and fall time of the output voltage. 15) Change the width (w) of NMOS to 10u and run the program. From the transient analysis determine the values of rise time and fall time of the output voltage. 16) Change the width (w) of NMOS back to 4u and that of PMOS to 20u and run the program. From the transient analysis determine the values of rise time and fall time of the output voltage. Report : 7) What is CMOS NOR gate? logic function does the CMOS NAND gate perform? 8) Include the results and figures obtained in procedure. 9) Comment on the variation of output with the change of width of the PMOS and NMOS. 10) 11) Compare a CMOS circuit designed with NOR gates with one based on NAND gates. Which is better and why? Page 12

13 PRESIDENCY UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING EE 310: VLSI Systems Laboratory EXPERIMENT NO. 5: INTRODUCTION TO LAYOUT DESIGN USING MICROWIND Objectives: To familiarize with the environment of Micro wind. To design the mask layout of a CMOS inverter. To familiarize with DRC. Introduction: Micro wind is a tool for designing and simulating circuits at layout level. The tool features full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics, 2D cross section, 3D process viewer), and an analog simulator. In this experiment we learn how to design circuit in layout level using Micro wind.here the use of different icon for designing in micro wind are described step by step. Procedure of Designing: 1.Manual Design In Micro Wind, the default icon is the drawing icon shown above. It allows box editing. The palette is located in the lower right corner of the screen. A red color indicates the Page 13

14 current layer. Initially the selected layer in the palette is polysilicon. The two first steps are illustrated in Figure 2. Fix the first corner of the box with the mouse. While keeping the mouse button pressed, move the mouse to the opposite corner of the box. Release the button. This creates a box in polysilicon layer as shown in Figure 2. The box width should not be lower than 2, which is the minimum width of the polysilicon box. Fig. 2. Creating a polysilicon box. Now, draw two more boxes as in Figure 3. Try to keep close to the shape and size shown in Figure. Page 14

15 Fig. 3. Creating three polysilicon boxes. Change the current layer into N+ diffusion by a click in the palette on the Diffusion N+ button. Be sure that the red layer is now the N+ Diffusion. Draw a n-diffusion box at the bottom of the drawing as in Figure 4. N-diffusion boxes are represented in green. The intersection between the N+ diffusion and the polysilicon creates the channel of the MOS device. Fig. 4. Creating the N-channel and P-Channel devices. Page 15

16 Change the current layer into P+ diffusion by a click in the palette on the button P+ Diffusion. Draw a p-diffusion box at the top of the drawing as in Figure 4. P-diffusion boxes are represented in yellow. The intersection between the P+ diffusion and the polysilicon creates the channel of the pmos device. Change the current layer into N Well by a click on the corresponding button in the palette. Draw a well all around the p+ diffusion, as in Figure 5. Use keyboard arrows (up key) to view the upper part of the layout. 2.Process Simulation Fig. 5. Creating the well for the P-Channel Device. Click on this icon to access «process simulation». The cross-section is given by a click on the mouse at the first point and the release of the mouse at the second point. In the example below (Figure 6), the cross-section of the n-channel MOS device appears on the left, and the cross-section of the p-channel MOS device on the right. Page 16

17 Fig. 6. The cross-section of the nmos and pmos devices. 3.Contacts and Metal Interconnects The diffusion areas must be joined using a metal layer. The metal layer is isolated from the diffusions by a thick silicon dioxide SiO2 layer. The contact layer is used to drill a hole in the oxide in order to join the metal and the diffusions. You could draw the contact box manually by selecting the layer «Contact» and drawing a 2 x 2 box. A fast solution is to use the predefined macros at the top of the palette. Various contacts built according to design rules are proposed. Page 17

18 Contact poly/metal Contact diffn/metal Contact diffp/metal Contact via/metal Fig. 7. The contact macros. Choose the diffn/metal contact icon in the palette. The contact outline will appear. Fix the contact inside the n+ diffusion area. Click again on the diffn/metal contact and place it at the upper corner of the n-well box. This contact is used to polarize the well at VDD. The diffusion N+ in the nwell makes an ohmic contact and prepares for the VDD polarization using metal layers. Finally, click on the diffp/metal icon and fix the contact inside the p+ diffusion area. Select the «metal» layer in the palette. Draw a metal bridge between the n+ and p+ contacts. The CMOS inverter layout is almost completed (Figure 8). The remaining task is to define where the supply, the ground, the input and the output are. Page 18

19 Fig. 8. The metal bridge and the inverter are completed. DRC Check: Click on the above icon. The Design Rule Checker (DRC) scans the design and verifies a set of design rules. The errors are highlighted in the display window, with an appropriate message giving the nature of the error. Details about the position and type of error(s) appear on the screen. Only an error-free layout can be sent to fabrication. Page 19

20 Save & Quit Click on F2 or File -> Save. The design is saved under the current name. The MSK appendix is automatically added to the user s filename. To leave MICROWIND, click on File->Leave Microwind in the main menu. Report: Same report should be submitted for experiment 5 & 6. Page 20

21 PRESIDENCY UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING EE 310: VLSI Systems Laboratory EXPERIMENT NO. 6: LAYOUT DESIGN OF A CMOS INVERTER USING MICROWIND Objectives: To familiarize with the environment of Microwind. To design the mask layout of a CMOS inverter. To check the functionality of the inverter and measure the rise time, fall time and inversion voltage. Procedure: 1. File->Select foundry->cmos035.rul 2. Zoom in to fit minimum grid to 1 lambda 3. From Palette->Polysilicon and N+ diffusion for NMOS. N well, P+ Diffusion, Polysilicon for PMOS. Minimum dimension for Polysilicon = 2, P+ Diffusion/N+ Diffusion = 4 lambda. Page 21

22 4. Use contact N+ Diff/Metal 1 for N+ Diffusion and P+ Diff/Metal 1 for P+ Diffusion of source and drain. 5. In each step run DRC for design rule checking and necessary correction. 6. Connect substrate and N-well to most negative and most positive potential respectively to reduce parasitic effect using appropriate contacts. 7. Connect the drains of the two transistors using metal Connect the source of the PMOS transistor to high logic level and that of the NMOS transistor to ground. 9. Connect clock to Polysilicon and visible node to the output. 10. Simulate and see the waveform and calculate delay/ rise time/ fall time. Page 22

23 11. Click and observe 2D Cross-sectional view. PMOS Cross-sectional View Page 23

24 NMOS Cross-sectional View Report: 1. Design the inverter with dimensions shown in the following table and run simulation to observe the functionality, determine the values of rise time and fall time of the output voltage and determine inversion voltage. (Hint : first design with highest dimensions i.e. W n = 6, L n =16, W p = 12, L p =6 with no design rule violation and then reduce the dimensions to start from serial 1. It is easier to reduce feature size than to increase it.) Serial NMOS PMOS Gate Width () Gate Length () Gate Width () Gate Length () Fix width and length of NMOS and PMOS to such a value that approximately equal rise time and fall time is obtained. Provide simulation results. 3. Include the results obtained in the above procedures and provide explanation of the findings. Extract the PSPICE netlist from the inverter layout. Construct the circuit from the netlist. Provide the netlist and the circuit diagra Page 24

25 PRESIDENCY UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING EE 310: VLSI Systems Laboratory EXPERIMENT NO. 7: LAYOUT DESIGN OF A 2-INPUT CMOS NOR GATE FOR EQUAL RISE TIME AND FALL TIME Objectives: To design the mask layout of a 2-input CMOS NOR gate. To check the design by design rule checker. To check the functionality of the gate and measure the rise time and fall time by simulating the layout by the built-in simulator. Theory: We know to make the rise time and fall time equal the effective beta for the load network and for the driver network must be equal. We will apply this principle in our design and consider the worst case. The circuit diagram of a 2-input CMOS NOR gate is shown below. Page 25

26 2 input CMOS NOR gate 1 βpeffect 1 1 βp1 βp2 For load network : If we assume p1 = p2 = p then peffect = p /2. For driver network : If we consider worst case and n1 = n2 = n then neffect = n. Now to make rise time and fall time equal neffect = peffect or, n = p /2 or, 2 n = p or, μ 2 n Wn D Ln μp Wp D Lp or, 4W n /L n = W p /L p if we assume n = 2 p Design : L n = L p = 2 W n = 4 W p = 16 Page 26

27 Procedure: 12. File->Select foundry->cmos035.rul 13. Zoom in to fit minimum grid to 1 lambda 14. From Palette->Polysilicon and N+ diffusion for NMOS. N well, P+ Diffusion, Polysilicon for PMOS. Minimum dimension for Polysilicon = 2, P+ Diffusion/N+ Diffusion = 4 lambda. 15. Use contact N+ Diff/Metal 1 for N+ Diffusion and P+ Diff/Metal 1 for P+ Diffusion of source and drain. 16. In each step run DRC for design rule checking and necessary correction. 17. Connect substrate and N-well to most negative and most positive potential respectively to reduce parasitic effect using appropriate contacts. 18. Connect the sources of the two NMOS transistors and drains of the same transistors, the drain of PM2 using metal Connect the source of PM2 transistor to the drain of the PM1 using metal Connect the source of the PM1 transistor to high logic level and that of the NMOS transistors to ground. 21. Connect the gates of PM1 and NM2 and the gates of PM2 and NM1 using polysilicon. 22. Connect clock to Polysilicon and visible node to the output. 23. Simulate and see the waveform and calculate delay/ rise time/ fall time. 24. Click and observe 2D Cross-sectional view. Report: 1) Design the layout of 2-input NOR gate in Microwind using the above aspect ratios of the transistors. 2) Check your circuit for design rule violation. 3) Simulate the circuit from Microwind and check the functionality. Also check whether the design meets your requirement or not. 4) Include the printouts of the waveshapes. 5) Discussion. Page 27

28 PRESIDENCY UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING EE 310: VLSI Systems Laboratory EXPERIMENT NO. 8: LAYOUT DESIGN OF A 2-INPUT CMOS NAND GATE FOR EQUAL RISE TIME AND FALL TIME Objectives: To design the mask layout of a 2-input CMOS NAND gate. To check the design by design rule checker. To check the functionality of the gate and measure the rise time and fall time by simulating the layout by the built-in simulator. Theory : We know to make the rise time and fall time equal the effective beta for the load network and for the driver network must be equal. We will apply this principle in our design and consider the worst case. The circuit diagram of a 2-input CMOS NAND gate is shown below. Page 28

29 2 input CMOS NAND gate For driver network: 1 βneffect 1 1 βn1 βn2 If we assume n1 = n2 = n then neffect = n /2. For load network: If we consider worst case and p1 = p2 = p then peffect = p. Now to make rise time and fall time equal neffect = peffect or, or, n /2 = p n = 2 p or, μnε D W L n n μpε 2 D W L p p or, W n /L n = W p /L p if we assume n = 2 p. Design : L n = L p = 2 W n = W p = 4 Procedure: 25. File->Select foundry->cmos035.rul 26. Zoom in to fit minimum grid to 1 lambda Page 29

30 27. From Palette->Polysilicon and N+ diffusion for NMOS. N well, P+ Diffusion, Polysilicon for PMOS. Minimum dimension for Polysilicon = 2, P+ Diffusion/N+ Diffusion = 4 lambda. 28. Use contact N+ Diff/Metal 1 for N+ Diffusion and P+ Diff/Metal 1 for P+ Diffusion of source and drain. 29. In each step run DRC for design rule checking and necessary correction. 30. Connect substrate and N-well to most negative and most positive potential respectively to reduce parasitic effect using appropriate contacts. 31. Connect the sources of the two PMOS transistors and drains of the same transistors, the drain of NM1 using metal Connect the source of NM1 transistor to the drain of the NM2 using metal Connect the sources of the PMOS transistors to high logic level and that of the NM2 transistors to ground. 34. Connect the gates of PM1 and NM2 and the gates of PM2 and NM1 using polysilicon. 35. Connect clock to Polysilicon and visible node to the output. 36. Simulate and see the waveform and calculate delay/ rise time/ fall time. 37. Click and observe 2D Cross-sectional view. Report : 1) Design the layout of 2-input NAND gate in Microwind using the above aspect ratio of the transistors. 2) Check your circuit for design rule violation. 3) Simulate the circuit from Microwind and check the functionality. Also check whether the design meets your requirement or not. 4) Include the printouts of the waveshapes. 5) Discussion. Page 30

31 PRESIDENCY UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING EE 310: VLSI Systems Laboratory EXPERIMENT NO. 9: VLSI DESIGN USING SCHEMATIC CAPTURE. Objectives: To familiarize with DSCH program To design a 2 input NAND gate using DSCH.. Introduction The DSCH program is a logic editor and simulator. DSCH is used to validate the architecture of the logic circuit before the microelectronics design is started. DSCH provides a user-friendly environment for hierarchical logic design, and fast simulation with delay analysis, which allows the design and validation of complex logic structures. This Experiment use the CAD program called DSCH to show a simple flavor of digital system design using schematic entry. PROCEDURE: 1) Start the DSCH program by double clicking the DSCH icon. As shown in Figure -1 the software window is composed of the parts below : a) The tool box with buttons corresponding to some commands of the main menu. Keep the mouse one second on the button to see the small help message concerning the button. b) 3.Useful message for each step of operation are displayed at the right upper corner of the window. c).the main part is the window used for schematic design. d) The symbol library contains a set of basic symbols ready to drag in the design window. Page 31

32 Fig -1 : The screen of DSCH shown with the schematic entry of a 2-input nand gate. 2) Click the symbol icon in the main menu. A logic library will appear at the right side of the window. 3) Drag the nmos transistor and the pmos transistor from the logic library and use line and connect to wire the transistors to implement a 2- input nand gate. 4) Add signal clock1and clock2 from the logic library by dragging the Clock 0/1 at the two inputs of the gate. Make the period of clock 2 double than that of clock 1 by double clicking the signals and entering the necessary values. 5) Add a light button from the logic library at the output of the gate by dragging the light 0/1 symbol from the logic library. Simulate your design by pressing the simulate button at the main menu and verify its function. Note that you will be able to simulate the function only. No information regarding rise time or fall time etc. can be obtained from this simulator. 6)Drag the one bit full adder from the logic library repeatedly and design a 4 -bit full adder as shown in figure -2. 7)Add two key board to simulate input of 4-bit A and B signal. At the output add a hex display. Page 32

33 8)Simulate the function of your design by entering various 4-bit number at A and B and observe the output. REPORT : 1. Give a print out of your schematic. In your design choosew/l=10/1.2 for both the nmos and the pmos. 2. In DSCH click << File -> Make verilog file >> and click on <<save>>. The verilog text file named filename.txt is saved. Give a print out of your verilog file. 3. In DSCH click << File -> Make spice file -> create >>. A spice file of the circuit is created. Give a print out of your spice file. 4. Give a print out of your schematic entry of the 4-bit full adder 5. Give a print out of the hierarchy verilog file and the flat verilog file. What are the difference between these two form of verilog description. 6. Give a print out of the SPICE file of the 4-bit adder 7. Design a 1-bit full adder by using schematic entry of 2-input XOR, AND and OR gate form the logic library and simulate it function. Give a printout of the schematic of your design. Page 33

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