A Simplified Circuit to Model RC Interconnect

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1 A Simplified Circuit to Model C Interconnect Patricia enault, Pirouz Bazargan-Sabet ASIM/LIP6, rue Cuvier - Paris Abstract: In very deep submicron technologies, the parasitic capacitor and resistance can have a significant impact on propagation delay and functional failure. Several methods consist evaluatg the put delay or givg an approximation of the put signal. These methods are really simple and are easily used timg analysis. However, they are unusable functional failure analysis such as crosstalk noise analysis. In this paper we propose to model rc-circuits with a simplified circuit composed by a resistor, a capacitor and several current sources. The simplified circuit can easily be tegrated a crosstalk noise evaluation tool. Its accuracy is demonstrated on several large rc-circuits. Keywords: C-Interconnect, Modellg, Verification Tool. Introduction Multi-million transistor circuits are made usg the latest processes. The features of these technologies clude an creased number of metal levels, thner metal width, creased wire height versus width ratio and smaller wire spacg. These new features troduce new cause of failure. This is the reason why designers spend up to 8 % of a design on the verification step. Therefore, some new verification tools are needed to check the robustness of VLSI circuits agast these causes with a reasonable computation time. It is well known that some up to lately neglected physical effects submicron technologies, such as parasitic capacitor and resistance, can significantly affect the behaviour of the circuit (timg and/or functional failure). Nowadays, the design methodologies [] and tool, such as rer [], have to take to account these parasitic elements []. In real-size circuit, the C-circuits can have a really important number of parasitic elements (near or resistances and ground capacitors) and have a complex topology with crosstalk couplg capacitor. Thus, the parasitic Ccircuits can not be tegrated to verification tools. We propose to reduce the complexity of the C-circuit modelg the C-circuits with a simplified circuit wich can be tegrated to verification tools. The method is composed by two step. First, we compute the put waveform accordg to the put waveform. Then, we determe the parameters of the simplified model. In this article we expose the method used to compute the put waveforms accordg to the put waveform. The two ma methods used to reduce rc terconnect trees are the Elmore delay metric [] and the first three moments method [5]. Despite it beg more than 5 years old, the Elmore delay metric is today widely used current physical design tool. The popularity of the metric is maly due to its efficiency and ease of use. ecently, the first three moments method gives the explicit expression for the delay as a function of the first three moments of the impulse response. These methods give an approximation of the delay due to terconnect. However, this delay can not be used to determe the crosstalk noise. The crosstalk noise is the noise duce on a steady state signal called victime by its neigbourg wire called aggressors. The active aggressors are the aggressors, which are makg a transition, and the silent aggressors the aggressors, which are a steady state. In addition, the secondary victims are the signals coupled with the aggressors. Many models have been proposed to estimate the peak value of the noise produced on a victim [6] [] [7]. Some of them take to account the resistance-capacitance of the terconnect, others focus on studyg the noise produced by the simultaneous transition of several aggressors. Now, we expose our model that ignores the rc of the terconnect but gives a satisfyg estimation of the peak produced on the victim by several aggressors usg a simple approach [8]. Note that we called victim the studied signal and aggressors the signals coupled with the victim. The active aggressors are the aggressors, which are makg a transition, and the silent aggressors the aggressors, which are a steady state. In addition, the secondary victims are the signals coupled with the aggressors.this model takes to consideration some second order effects such as the existence of silent aggressors and secondary victims and is composed by three successive approximations: replacg signal s drivers by a simple resistance replacg silent aggressors and secondary victims by equivalent capacitors replacg active aggressors by an equivalent current

2 source i k (t) =I k e t/τi k Then, the fal equivalent circuit of a victim coupled with n aggressors is shown figure. V i v i n Fig. : Fal equivalent circuit C V When the put signal makes a transition, we know that the put waveform is: x (t) = 6 a i.e t τ i + V DD () where a i are called the coefficients and τ i the time constant. The figure shows the electrical simulation of the rc-circuit with six nodes when the resistors are equal to 5Ω and the capacitors to pf and pf. We can see that the capacitor values modify the signal slope and the time where the signal is near zero. And the victim s waveform is expressed as 5 pf pf x v (t) = v n I k k= τ ik τ v τ ik.(e t/τv e t/τi k ) () where τ v = v C v As we have seen, for each victim, determg which of its aggressors may commute the same time is a key pot the noise analysis. With the put stability period and the propagation delay through the gates, we determed the noise configuration [9]. A noise configuration is defed as a subset of aggressors that may commute the same time. An event-driven approach, based on the evaluation of stability periods, is used to make distction between active and silent aggressors. The experience shows that the error compared to an electrical simulation remas less than 5%. However, this method doesn t take to account the rc-circuit of terconnection. In this paper, we propose to model the rc-circuits with couplg capacitance order to add them the crosstalk noise evaluation tool. The next section presents the simplified circuit used to represent the victim and aggressors. In the section, we show how this model can be tegrated to the noise evaluation tool. Section details the method used to calculated the parameters of the simplified circuit. Some results are shown section 5. The last section exposes the concludg remarks and the future works.. Victim model Let s consider a simple rc-circuit composed by six resistors and capacitors (Fig ) Time (ps) Fig. : Electrical simulation We propose to model the put signal with a delay and an exponential function. The exponential function is obtaed with a resistor lv and a capacitor C lv. The victim model is represented figure. lv Fig. : Victim model Figure 5 shows an electrical simulation of the victim model. When the put signal makes a transition from V SS to V DD the put signal can be expressed as ˆx (t) = t [, ] V DD.( e (t ) τv ) t [, + [ () 5 C C C C C Fig. : C-circuit with six nodes C. Aggressor model In [8] the active aggressors a i are replaced by an equivalent current source defed as I ai e t τa i where I ai is the current maximum and τ ai the time constant. This approximation is really simple and the current generated by several

3 5 lv (t δ ai ) τa i I e ai Fig. 8: for a rc-circuit composed by one aggressor Time (ps) Fig. 5: Output signal of the simplified circuit aggressors can be added. We have chosen to use a similar approximation. However, order to take to account the rc-circuit, we have to modify this model. Let s consider a victim composed by n nodes coupled with an aggressor (see figure 6). n n describe [8]. The current source is I ai e t δa i τa i. Figure 8 shows the simplified circuit of a victim coupled with one aggressor. The put signal can be expressed as ˆx (t) = t [,δ a ] I aτ a.( e t δa τa ) t [δ a,δ a + ] C lv I a τ a [( τ a.e τa ).e t (δa+ ) τv C lv τ a τ v + τ v.e t δa τa ] t [δ a +, + [ τ a τ v () The simplified circuit of a rc-circuit composed by n aggressors is shown figure 9. a lv I e a i δ (t a ) δan τ a τ an I e an (t ) Fig. 6: Victim coupled with an aggressor Figure 7 shows the electrical simulation of a steady-state victim composed by and 6 nodes coupled with an aggres- Fig. 9: for a rc-circuit composed by n aggressors nodes nodes Integration a crosstalk evaluation tool Let s consider an put signal i coupled with n active aggressors. The simplified circuit is shown figure. v and C v represent the victim driver. The resistor and capacitor of the aggressor drivers are take to account the current sources. v Cv lv I e a i δ (t a ) δan τ a τ an I e an (t ) Time (ps) Fig. 7: Crosstalk noise due to the transition of the aggressor sor which makes a transition from V SS to V DD. We can see that the noise is significant after some delay. Thus, we propose to add a delay δ a to the current source Fig. : of an put signal i coupled with n active aggressors We have seen the troduction that the stability period can be computed with the gate delay and the stability periods of the put signals. But, the modelization of the rccircuit adds some delay on the aggressor terconnection.

4 Thus, to determe which aggressors make a transition the same time, we have to take to consideration the delay δ a the static stability analysis. Fally, the simplified circuit for the crosstalk noise analysis is shown figure. V DD Voltage v Cv v lv I e a t τ a I e an t τ an Time Fig. : for crosstalk noise analysis We have G v.x v + C v.x v = G lv.x G lv.x + C lv x = G lv.x v + where G v = v + lv et G lv = x can be written as lv x (t) =K.e r.t + K.e r.t + I ai.e t τ ai (5) K ai e t τ ai (6) where τ, τ are the time constants and depend of the values of the resistors and capacitors. K, K and K ai are some coefficient. In order to determe the crosstalk noise of the signal, we determe with the Newton-aphson method the time t bruit which x (t bruit )=. Then, the noise peak is V bruit = K.e r.t bruit + K.e r.t bruit + Determg the parameters K ai e t bruit τ ai. Victim parameters Let s consider the put signal of a rc-circuit composed by n nodes. When the put signal makes a transition from V SS to V DD, the put signal is x (t) = (7) a i e hi.t + V DD (8) The put signal obtaed with the simplified circuit is : ˆx (t) = t [, ] V DD.( e (t ) τv ) t [, + [ where τ v = lv C lv Figure gives an example of the put signal obtaed with the itial and simplified circuit. (9) Fig. : Output signal obtaed with the itial and simplified circuit We have to determe τ v and such as ˆx is a good approximation of x. We note d the distance between two functions and defed as d(f,g) = + (f(t) g(t)).dt () g is a good approximation of f if the distance between f and g is mimal. We seek to defe ˆx such as d(ˆx,x ) is mimal. d(ˆx,x ) = = + + (x (t) ˆx (t)) dt ( a i e hi.t + V DD ) dt + ( a i e hi.t V DD.e (t ) τv ) dt () In order to fd the mimal value of d(ˆx,x ) accordg to and τ v we try to solve this equation system With d(ˆx,x ) = F (,τ v )= τ v d(ˆx,x ) = F (,τ v )= F (,τ v ) = V DD.V DD F (,τ v ) = V DD.V DD n a i +h i τ v e hi () a i ( + h i τ v ) e hi () This equation system is not lear. So we use the Newton- aphson method with partial derivation to solve this equation system. With an itial value of the solution (,τ v ) we determe (,τ v ),, (n,τ vn ) which converges to the solution. With an element (i,τ vi ), the next element is computed solvg the next matrix equation F (i,τ vi ) F (i,τ vi ) ( ) τ v F (i,τ vi ) F F (i,τ vi ) = τ v (i,τ vi ) F (i,τ vi ) τ v ()

5 where τ v = i+ i = τ vi+ τ vi. Aggressor parameters Let s consider the put signal obtaed when the coupled aggressors are makg a transition from V SS to V DD. x (t) = a i e hi.t (5) The put expression of the simplified circuit is ˆx (t) = t [,δ a ] I aτ a.( e t δa τa ) t [δ a,δ a + ] C lv I a τ a [( τ a.e t (δa +) τa ).e τv C lv τ a τ v + τ v.e t δa τa ] t [δ a +, + [ τ a τ v (6) Figure shows an example of put signal of itial and simplified circuit. xm Voltage tm Time Fig. : Output signal of itial rc-circuit and of simplified circuit. Method to fd the parameters with an electrical simulation We have seen how to determe the parameters for the victim and for the aggressors with the put signal defed as the sum of exponential function. In a real size rc-circuit, the computation time necessary to fd the exact formula of the put signal can be really important. Thus, we propose a technique to determe the parameters for both victim and aggressor with the result of an electrical simulation. With an electrical simulation, we obta a set of pot that represent the put signal : x is defed for i {,,n} x (t i ). In order to approximate a function, we use the distance defed as d(ˆx,x )= N (x (t i ) ˆx (t i )) (8) Then, we can compute the victim and aggressor parameters replacg ˆx with the put expression obtaed with the simplified circuit and usg the Newton-aphson method. 5 esults In this section we compare the results obtaed with the itial rc-circuit and the simplified circuit. Figure shows the electrical simulation of the itial and simplified circuit. The itial circuit is composed by nodes with aggressor. Its put makes a transition. We can see that the simplified circuit curve is near zero before the delay and after has a form of an exponential. The curves of the itial and simplified circuit are really closed. Here, we used the same distance criteria to determe a good approxitaion of x. For the case of a victim coupled with an aggressor the peak value is particularly important. Thus, we propose to mimize the distance between ˆx and x with the next constrat : The peak noise obtaed with the simplified circuit must occur at the same time and have the same value that the peak obtaed with the itial circuit. 5 We obta this equation system F (δ a,τ a,i a )= d(ˆx,x ) = δ a F (δ a,τ a,i a )=x (t max ) = F (δ a,τ a,i a )=ˆx (t max ) x (t max )= (7) The Newton-aphson method usg partial derivative solves this system. e 8 e 8 e 8 e 8 5e 8 6e 8 Time (s) Fig. : versus itial rc-circuit Figure 5 shows the put signal of a rc-circuit composed by nodes with one aggressor when the victim put signal is stable to V SS and the aggressor put signal makes a transition from V SS to V DD and the simplified circuit.

6 e 9 e.5e e Time (s) Fig. 5: versus itial rc-circuit We can see that the simplified circuit put is null for t [,δ a ]. Then, befor the peak, the curves obtaed with the itial and simplified circuit are closed. The peak obtaed with the two curves has the same value. But, after the peak, the simplified circuit gives a satisfyg approximation of the itial circuit. The table presents the results obtaed with the itial circuit (a victim coupled with two aggressors which are makg a transition the same time) and simplified circuit. The error is the difference of the peaks obtaed with the simplified and itial circuit divided by V DD. Peak(simpl. circuit) Peak(it. circuit) Error = V DD (9) Peak value when V DD =5V Number Simplified Initial Error of node circuit (V) circuit (V) %..9.% % % % % % Table : Peak value and error obtaed with the proposed method compared to an electrical simulation We can see that the error is equal to.56% for a -nodes circuit and remas less than %. 6 Conclusion and future works Signal tegrity is becomg a major issue the verification process of high performance designs. C-circuit is one of the factors that may cause timg or functional failure the circuit. In this paper, we have presented a model to represent rccircuit. This model is really simple and can easily be tegrated a crosstalk noise evaluation tool. The experience shows that the error of the proposed model rema less than %. The method used to determe the simplified circuit parameters is based on the analytic put signal expression or on the results of an electrical simulation. In addition, we can apply this model on the results of methods, which determe the put waveform accordg of the put transition, such as the first three moments methods. In the futur, some new parasitic elements will have a significant impact on verification tools : the ductance of terconnect. A more accurate model has to be develop takg to consideration the L of the terconnect and a method for computg its parameters. eferences []. Saleh, D. Overhauser, and S. Taylor, Full-chip of udsm designs, ICCAD, IEEE/ACM, 998, pp [] H. Zhou and D. Wong, An optimal algorithm for river rg with crosstalk contrats, ICCAD, IEEE/ACM, 996, pp. 5. [] P. B. Morton and W. Dai, An efficient sequential quadratic programmg formulation of optimal wire spacg for crosstalk noise avoidance rg, Proceedgs of the ISPD, 999. [] W. C. Elmore, The transient response of damped lear networks with particular regard to wideband amplifiers, Journal of applied physics, vol. vol. 9, January 98. [5] B. Tutuianu, F. Dartu, and L. Pileggi, An explicit rccircuit delay approximation based on the first three moments of the impluse response, DAC, IEEE/ACM, 996. [6] P. Chen and K. Keutzer, Towards true crosstalk noise analysis, Proceedgs of the ICCAD, 999. [7] A. B. Kahng, S. Muddu, and D. Vidhani, Noise and delay uncertaly studies for coupled rc terconnects, Proceedgs of the ASIC/SOC, 999. [8] P. enault, P. Bazargan-Sabet, and D. L. Du, A mos transistor model for peak voltage calculation of crosstalk noise, Proceedgs of the ICECS,. [9] P. Bazargan-Sabet and P. enault, Usg symbolic simulation to exhibit worst case crosstalk noise configuration, Proceedgs of the LATW,.

Digital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC.

Digital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC. Digital Integrated Circuits The Wire * Fuyuzhuo *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk Introduction The Wire transmitters receivers schematics physical 2 Interconnect Impact