FX5 SAPPORO-INTEGRATED

Transcription

1 POWR SYSTM RST IRUIT PG FX SPPORO-INTGRT RV : RUN POWR SW PG R-SOIMM PG, / MHZ R II M S Turion Rev.F ual-ore/ ual-ore W LOK IS PG FN & THRML M PG TT HRGR /TT NTOR PG PG PU VR PG / PG.V_SUS/V_SUS/V_SUS RGULTOR PG V_N &.V_LW_SUS RGULTOR PG.V_SUS/.V_R_VTT.V_RUN R-SOIMM PG, R-MMORY VI MXX -PIN FG PG Panel N. PG TVout N. PG RT N. PG -ROM PG ST - H PG / MHZ R II MHZ R II LVS TVOUT VG I ST IH ( Sg socket) PG,,, HT_LINK RS FG PG,,,, _LINK S G PIx PIx PIx US. (P) US. (P) US. (P) US. (P,P)(XT SI) US. (P,P)(XT K) US. (P,P) MHz PI (GX) MINI-R WWN PG MINI-R x WLN & WPN PG XPRSS-R R PG xternal USX PG xternal USX PG FX M/ P S/PIF UIO/MP PG, M PG US. (P) SPI LP PG,,, -in- ard Reader R PG,, M () PG udio Jacks igital MI PG PG amera SNIFFR FLSH SIO M K Flash TMK PG Pins VTQFP PG SPI PS/ Touchpad/ Keyboard PG SIO xpander US. Hub() Pins VTQFP PG IR PG USR INTRF PG QUNT OMPUTR Schematic lock iagram RJ/Magnetics PG Size ocument Number Rev FX ate: Thursday, November, Sheet of

2 INX Pg# escription Schematic lock iagram Front Page - Turion - RII SO-IMMX - RST - S lock Generator L onn. & K-SS RT&TV N - -IN- R RR ST (H&_ROM) MINI-PI WWN xpress ard & Smart ard US SIO (M) SIO () FLSH,RT&K TP&IR udio O(ST)&MP UIO N igital MI/amera FN & Thermal LN (M) LN JK SWITH&L System Reset ircuit harger IN,TT NTOR.V_LW_SUS,N_VOR.V_SUS,.V_R_VTT,.V_RUN VHOR(MX).V_LW,V_LW RUN Power Switch MI P & SRW HOL SMUS LOK POWR LOK hipset Power lock PI evice ardbus (OZ) ocking Mediaard & (R) LOM () PI- Lane Lane Lane Lane I hips ISL estination (S/Y) MINI R- WWN MINI R- WLN MINI R- WPN XPRSS R US Port# RQ# / GNT# - PIRQ (S/Y) N/ N/ RQ# / GNT# - PIRQ# (Media ard), PIRQ# () & SRIRQ. RQ# / GNT# - PIRQ#. estination (S/Y) Right side Pair Top as viewed in the front Right side Pair ot. as viewed in the front Rear Side Top Rear Side ottom Power States Power Rail V_LW V_LW.V_LW.V_LW_SUS V_SUS.V_SUS.V_SUS.V_R_VTT V_RUN.V_RUN.V_RUN.V_RUN.V_RUN V_VR N_VOR LV.V_WLN.V_LN PM Table State ontrol Signal Power Plan S/M S/M S/M S/M V_LW V_LW.V_LW.V_LW_SUS V_SUS.V_SUS.V_SUS.V_R_VTT S/ M-off V_RUN.V_RUN.V_RUN.V_RUN.V_RUN.V_RUN V_OR N_OR S/ M-off S/ M-off S Left side Pair Tot as viewed in the front amera S S OFF xpress ard S S/ OFF OFF rd Mini ard US(WPN) S S on battery OFF OFF OFF Left side Pair ot. as viewed in the front WWN QUNT OMPUTR Index, NI, Power & Ground Size ocument Number Rev FX ate: Thursday, November, Sheet of

3 PROSSOR HYPRTRNSPORT INTRF VLT_x N VLT_x R NT TO TH LT_RUN POWR SUPPLY THROUGH TH PKG OR TH I. IT IS LY NT TH OR TO OUPLING NR TH PU PKG LYOUT: Place bypass cap on topside of board NR HT POWR PINS THT R NOT NT IRTLY TO OWNSTRM HT VI, UT NT INTRNLLY TO OTHR HT POWR PINS PL LOS TO VLT POWR PINS.V_RUN.V_RUN U VLT_ VLT_ VLT_ VLT_ VLT_ VLT_ VLT_ VLT_.U/.V/.U/.V/.U/.V/.U/.V.U/.V P/V P/V Place R and R less than mils from PU.V_RUN HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_LKIN HT_LKIN# HT_LKIN HT_LKIN# N P M M L M K K H H G H F F F N N L M L L J K G H G G F J K J J L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_LKIN_H L_LKIN_L L_LKIN_H L_LKIN_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_LKOUT_H L_LKOUT_L L_LKOUT_H L_LKOUT_L T T V U V V Y W T R U U V U W W Y Y Y W HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_LKOUT HT_LKOUT# HT_LKOUT HT_LKOUT# XS NPO R R HT_TLIN HT_TLIN# P L_TLIN_H P L_TLIN_L L_TLOUT_H T L_TLOUT_L R HT_TLOUT HT_TLOUT# HT_TLIN N L_TLIN_H L_TLOUT_H R HT_TLOUT HT_TLIN# P L_TLIN_L L_TLOUT_L R HT_TLOUT# thlon S Processor Socket T T Place T and T less than mils from PU QUNT OMPUTR THL HT I/F Size ocument Number Rev FX ate: Thursday, November, Sheet of

4 V_VTT_SUS_PU IS NT TO TH V_VTT_SUS POWR SUPPLY THROUGH TH PKG OR TH I. IT IS LY NT TH OR TO OUPLING NR TH PU PKG.V_SUS Place apacitors for.v_pu_m_vrf_sus < " from the RST..V_PU_M_VRF_SUS trace length < ", trace width > mils and mils spacing from any adjacent signals in X, Y, Z directions. Processor R Memory Interface R.U/V K/F U PU_VTT_SUS_SNS R R R R [..].V_PU_M_VRF_SUS R M_T M_T R [..] R should be routed as mils V_R_VRF F * N R M_T M_T F R and mils spacing from any R M_T M_T R R M_T M_T adjacent signals in X, Y, Z Y R R R M_T M_T W R directions..u/v N/V K/F R M_T M_T Y R R M_T M_T F R PU_VTT_SUS_SNS R M_T M_T R PU_VTT_SUS_SNS F R M_T M_T F R R M_T M_T R R M_T M_T F R.V_SUS R M_T M_T Y R.V_R_VTT R M_T Y U M_T R R M_T M_T W R R M_T M_T W W R R MMVRF VTT R M_T M_T R./F VTT R M_T M_T Y Y R VTT_SNS VTT R M_T M_T R VTT F R M_T M_T R M_ZN VTT W F R M_T M_T R M_ZP MMZN VTT F R M_T M_T F R MMZP VTT R M_T M_T R VTT R M_T M_T R R M_T Y R VTT M_T R R M_T./F M_T R, R_S_IMM# V M_S_L M_LK_H Y M_LK_R R M_T M_T Y R, R_S_IMM# J M_S_L M_LK_L M_LK_R# R M_T M_T W R, R_S_IMM# V M_S_L M_LK_H M_LK_R R M_T M_T W R, R_S_IMM# T M_S_L M_LK_L F M_LK_R# R M_T M_T R R M_T M_T R, R_S_IMM# Y M_S_L M_LK_H F M_LK_R R M_T M_T R, R_S_IMM# J M_S_L M_LK_L F M_LK_R# R M_T M_T Y R, R_S_IMM# W M_S_L M_LK_H M_LK_R G PL THM LOS TO R M_T M_T H R, R_S_IMM# U M_S_L M_LK_L M_LK_R# G R M_T M_T H R PU WITHIN " R M_T M_T R, R_K_IMM H M_K M_OT W M_OT, R M_T M_T R, R_K_IMM J M_K M_OT W M_OT, G R M_T M_T J R, R_K_IMM J M_K M_OT V M_OT, G R M_T M_T H R, R_K_IMM J M_K M_OT U M_OT, R M_T M_T F R, R M[..] R M R M R M_T M_T F K R R M[..], R M M_ M_ J R M R M_T M_T K R R M M_ M_ J R M R M_T M_T V R R M M_ M_ W R M R M_T M_T F K R R M M_ M_ L R M R M_T M_T L R R M M_ M_ L R M R M_T M_T R R R M M_ M_ U R M R M_T M_T L R R M M_ M_ L R M R M_T M_T L R R M M_ M_ M R M R M_T M_T G L R R M M_ M_ L R M R M_T M_T G M R R M M_ M_ N R M R M_T M_T M R R M M_ M_ N R M R M_T M_T F M R R M M_ M_ N R M R M_T M_T M R R M M_ M_ N R M R M_T M_T H N R R M M_ M_ P R M R M_T M_T N R R M M_ M_ P R M R M_T M_T R R M_ M_ T R M_T M_T H R R M_T M_T R, R S K M_NK M_NK K R S, R M_T M_T R, R S R M_NK M_NK T R S, R M_T M_T H R, R S T M_NK M_NK U R S, G R M_T M_T H R R M_T M_T G R, R RS# T M_RS_L M_RS_L U R RS#, R M_T M_T H R, R S# U M_S_L M_S_L V R S#, R M_T M_T F R, R W# U M_W_L M_W_L U R W#, M_T M_T G *P/V_N R M R M R M M_M M_M Y R II: M/TRL/LK R M R M M_M M_M thlon S Y R M R M M_M M_M R M Processor Socket R M M_M M_M F R M R M M_M M_M R M R M M_M M_M R M R M M_M M_M R M R M[..] M_M M_M R M[..] R QS R QS R QS R QS R: T R QS R QS thlon S R QS R QS R QS Processor Socket R QS R QS R QS R QS R QS R QS R QS[..] R QS R QS[..] R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS#[..] R QS# R QS#[..] To SOIMM socket (Far) R QS R QS# R QS R QS# R QS R QS# R QS R QS# R QS R QS# R QS R QS# R QS R QS# R QS R QS# F F F F M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L W W Y W G G G G G H R QS R QS# R QS R QS# R QS R QS# R QS R QS# R QS R QS# R QS R QS# R QS R QS# R QS R QS# To SOIMM socket (near) QUNT OMPUTR THL RII MMORY Size ocument Number Rev FX Thursday, November, ate: Sheet of

5 THL ontrol and ebug The M SI feature has errata, and will not be mplemented..v_sus R R R *_N *_N PU_SI_R PU_SI_R for PU rev.f. If for rev.g, populate R, R and depopulate R. heckferrite bead with an approximate impedance of, a maximum resistance of m, and a current rating of at least m..v_run LMPGSN_ L U/.V/.U/.V/ LYOUT: ROUT V TR PPROX. mils WI (US x mil TRS TO XIT LL FIL) N mils LG. This trace should be kept at least mil from all other signal..v_pu_v_run.u/.v P_V F F U V V THRMTRIP_L PROHOT_L F H_THRMTRIP# PU_PROHOT# R.V_SUS R H_THRMTRIP# PU_LK PU_LK# p_v p_v.keep trace to resistor less then mils from cpu and trace to ac caps less than mils.pulk and PULK# mismatch <mils. R /F_ PU_LKIN_S_P PU_LKIN_S_N Place R and R <.". Route PU_HTRF/ with mils trace width and mils spacing from other signals in X, Y, Z directions To Power T T PU_V_RUN_F_H PU_V_RUN_F_L PU_VIO_SUS_F_H PU_VIO_SUS_F_L PU_VIO_SUS_F_H PU_VIO_SUS_F_L.V_RUN R R PU_VIO_SUS_F_H PU_VIO_SUS_F_L P/V/XR./F./F T T LT_RST# PU_PWRG LT_STOP# PU_LKIN_S_P PU_LKIN_S_N PU_SI_R PU_SI_R F F F PU_HTRF P PU_HTRFR F W Y RST_L PWROK LTSTOP_L SI SI HT_RF HT_RF V_F_H V_F_L VIO_F_H VIO_F_L LKIN_H LKIN_L VI VI VI VI VI VI PU_PRSNT_L PSI_L PU_PRSNT# T PU_PSI# VI VI VI VI VI VI PSI_L is a Power Status Indicator signal. This signal is asserted when the processor is in a low powerstate. PSI_L should be connected to the power supply controller, if the controller supports skipmode, or diode emulation mode. PSI_L is asserted by the processor during the and S states. PU_RY G RY.V_SUS.V_SUS R R.V_SUS PU_TMS PU_TK PU_TRST# PU_TI F TMS TK TRST_L TI RQ_L TO PU_RQ# PU_TO ROUT S Ohm IFFRNTIL PIR PL IT LOS TO PU WITHIN " PU_PROHOT# S LY *K_N K R.K Q MMST--F S this pin is.v,need it level-shift. _PU_PROHOT# H_THRM P/V/NPO T T T T T T T T T T T T T PU_TST_H_YPSSLK_H PU_TST_L_YPSSLK_L PU_TST_PLLTST PU_TST_PLLTST PU_TST_P PU_TST_P PU_TST_P PU_TST_P PU_TST_SNSHIFTN PU_TST_NLOG_T PU_TST_IRKM H_THRM H_THRM PU_TST_GT PU_TST_RIN G H F W W Y TST_H TST_L TST TST TST TST TST TST TST TST TST TST TST TST TST TST TST TST_H TST_L TST TST TST TST TST TST_H TST_L TST TST TST TST PU_TST_H_FLKOUT_P R PU_TST_L_FLKOUT_N PU_TST_SNLK PU_TST_TSTUP PU_TST_SNSHIFTN PU_TST_SNN F PU_TST_SNLK J PU_TST_H_PLLHRZ_P H PU_TST_L_PLLHRZ_N F PU_TST_SINGLHIN PU_TST_URNIN# K PU_TST_NLOGOUT PU_TST_IG_T./F T T T T T T T T T T T PU_PWRG R K PU_PWRG H_THRM Place < mils from PU. T T T T PU_RSV_M_LK_P PU_RSV_M_LK_N PU_RSV_M_LK_P PU_RSV_M_LK_N P P N N RSV RSV RSV RSV RSV RSV RSV RSV H PU_M_RST# PU_M_RST# PU_RSV_VISTR PU_RSV_VISTR T T T T, LT_STOP# R K () LT_STOP# T T T T PU_RSV_M_LK_P PU_RSV_M_LK_N PU_RSV_M_LK_P PU_RSV_M_LK_N R R P R RSV RSV RSV RSV MIS RSV RSV RSV RSV RSV RSV RSV RSV RSV H G R W R H H PU_RSV_VN_F_P PU_RSV_VN_F_N PU_RSV_OR_TYP PU_RSV_ PU_RSV_ PU_RSV_ PU_RSV_ PU_RSV_ PU_RSV_ T T T T T T T T T LT_RST# LT_RST# M NPT S SOKT Processor Socket R K Note:Place R on the Top of the board that is acessible, and that shorting across this resistor will toggle the Hyper Transport reset signal..v_sus PU_TST_SINGLHIN R *_N PU_TST_URNIN# R PU_PRSNT# R K/F PU_TST_H_YPSSLK_H R /F.V_SUS PU_TST_SNN R PU_RQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO *_N R *_N R *_N R *_N R *_N R HT NTOR JHT GN GN Resreved GN Resreved GN RQ_L GN RY GN TK GN TMS GN TI GN TRST_L GN TO GN VIO GN VIO RST_L GN *HT conn_n.v_run.v_run R R *.K_N *.K_N Q *MMST_N PU_RST# LT_RST# PU_TST_SNLK PU_TST_SNLK PU_TST_SNSHIFTN PU_TST_SNSHIFTN PU_TST_P PU_TST_P PU_TST_L_YPSSLK_L PU_TST_PLLTST PU_TST_PLLTST R *_N R *_N R *_N R *_N R *_N R *_N R /F R R THL TRL & UG QUNT OMPUTR Size ocument Number Rev FX Thursday, November, ate: Sheet of

6 V_OR V_OR V_OR V_OR.V_SUS.V_SUS.V_SUS.V_SUS.V_R_VTT.V_R_VTT Size ocument Number Rev ate: Sheet of QUNT OMPUTR FX THL PWR & GN Thursday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTR FX THL PWR & GN Thursday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTR FX THL PWR & GN Thursday, November, upg Top View OTTOMSI OUPLING F thlon Sg PROSSOR POWR N GROUN thlon S Processor Socket thlon S Processor Socket OUPLING TWN PROSSOR N IMMs PL LOS TO PROSSOR S POSSIL uf/v/->xs.uf/.v ->XS.uF/V ->XR pf/v ->NPO U/V/->XS.U/.V/->XS.uF/.V ->XS.uF/V ->XR pf/v ->NPO N/V ->XR For MI place spilt GN VIO. hange,,, from.u to u.() N/V N/V.U/.V/.U/.V/.U/.V.U/.V P_V P_V.U/.V.U/.V.U/.V.U/.V U/V/ U/V/.U/.V.U/.V U/V/ U/V/ U/V/ U/V/.U/.V.U/.V U/V/ U/V/.U/.V.U/.V P_V P_V P_V P_V U/V/ U/V/ P_V P_V.U/.V/.U/.V/ P_V P_V.U/V.U/V U/V/ U/V/ P_V P_V VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS H VSS H VSS H VSS H VSS J VSS J VSS J VSS J VSS J VSS J VSS J VSS J VSS K VSS K VSS K VSS K VSS K VSS K VSS K VSS L VSS L VSS L VSS L VSS L VSS L VSS L VSS M VSS M VSS M VSS M VSS N VSS N VSS N VSS N VSS N VSS P VSS P VSS P VSS P VSS R VSS R VSS R VSS R VSS T VSS T VSS T VSS T VSS V VSS V VSS V VSS W VSS Y VSS Y VSS N VSS T VSS T VSS U VSS U VSS U VSS U VSS U VSS U VSS U VSS U VSS V VSS V VSS V VSS V VSS P UF GROUN UF GROUN P_V P_V V V V G V H V J V J V J V K V K V K V K V L V L V L V L V L V M V M V M V M V N V N V N V P V P V R V R V R V R V T V T V T V T V T V T V U V U V U V U V V V V V V V V V V V W V Y V J V K V L V M V P V T V U V V VIO H VIO J VIO K VIO K VIO K VIO K VIO L VIO M VIO M VIO M VIO M VIO N VIO P VIO P VIO P VIO P VIO R VIO T VIO T VIO T VIO T VIO U VIO V VIO V VIO V VIO V VIO Y U POWR U POWR U/V/ U/V/.U/V.U/V U/V/ U/V/ U/V/ U/V/ N/V N/V.U/V.U/V U/V/ U/V/ P_V P_V N/V N/V U/V/ U/V/.U/.V.U/.V.U/.V.U/.V P_V P_V.U/.V/.U/.V/ P_V P_V P_V P_V P_V P_V.U/.V.U/.V.U/.V.U/.V.U/.V.U/.V N/V N/V U/V/ U/V/ U/V/ U/V/.U/.V/.U/.V/ P_V P_V P_V P_V P_V P_V P_V P_V U/V/ U/V/.U/.V.U/.V U/V/ U/V/

7 MM_SLK MM_ST MM_ST M_LK_R# M_LK_R MM_SLK R M R QS R M R QS# R M R M R M R R R R QS R R R M R M R M R QS R QS# R M R M R S R R W# R R M R M R M R R S# R QS# R R M R M R R R R R R QS# R M R R M M_LK_R M_LK_R# R R R R R R QS R R R QS R R R R R R R R R R R R R R QS R QS# R R R R R R R R QS# R M_OT R R M_OT R M_LK_R M_LK_R# R QS# R S R QS# R QS R R R RS# R R R R R M R M R QS R QS# R M R R M R M R M R R R QS R R M R R M R M R M R QS# R M R QS R R S R R W# R R M R M R M R R S# R QS R QS# R R M R R R R M R R R QS# R M R R M R R R R M R R R R R R QS R R R R QS R R R R R R R R R R R R R R R QS# R QS R R R R R R R QS# R M_OT R R R M_OT R R S R QS# R QS R QS# R R R RS# R R R R R R M R R QS R R R R M R R R R R R R R R M R M R M R S R R R R R R M R M R M R S M_LK_R# M_LK_R M_LK_R# M_LK_R M_LK_R M_LK_R# M_LK_R# M_LK_R M_LK_R# M_LK_R R M R M R M R M.V_R_RF R QS#[..] R [..] R M[..], R M[..] R QS[..] R_S_IMM#, R_S_IMM#, R QS#[..] R [..] R M[..], R S, R M[..] M_OT, M_LK_R R RS#, R QS[..] R_S_IMM#, R_S_IMM#, R S, R RS#, R_K_IMM, R S, R_K_IMM, R S, M_LK_R# M_LK_R MM_ST,,, MM_SLK,,, R S#, R S, R W#, R_K_IMM, M_OT, R S#, R W#, R S, R_K_IMM, M_OT, M_LK_R# M_OT, M_LK_R M_LK_R# M_LK_R# M_LK_R R_S_IMM#, R_S_IMM#, R_S_IMM#, R_S_IMM#,.V_SUS.V_SUS.V_RUN.V_SUS.V_SUS.V_RUN.V_SUS.V_SUS.V_RUN.V_R_RF.V_R_RF.V_R_RF Size ocument Number Rev ate: Sheet of QUNT OMPUTR FX RII SOIMMX Thursday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTR FX RII SOIMMX Thursday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTR FX RII SOIMMX Thursday, November, is required to route to Top SoIMM for MTto function. h. SOIMM needs to be populated for Intel MT support. OT TOP LOK, LOK, SMbus address SMbus address K, K, PL LOS TO PROSSOR WITHIN. INH PL LOS TO PROSSOR WITHIN. INH () () R K R K R K/F R K/F.U/V.U/V.U/V.U/V.U/.V/.U/.V/.P/V.P/V.P/V.P/V VRF VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS K V N _ V V V /P W# V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS Q Q VSS M VSS Q Q VSS Q Q VSS M VSS K K# VSS Q Q VSS VSS Q Q VSS N M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS K V V V V RS# S# V OT V N VSS Q Q VSS M VSS Q Q VSS Q Q VSS VSS M VSS Q Q VSS Q Q VSS NTST VSS QS# QS VSS Q Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS Q Q VSS Q Q VSS K K# VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS S S VSS P R SRM SO-IMM (P) JIM Tyco-- P R SRM SO-IMM (P) JIM Tyco--.U/.V/.U/.V/.P/V.P/V.U/.V/.U/.V/.U/.V/.U/.V/.U/V.U/V.U/V.U/V.U/.V/.U/.V/ VRF VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS K V N _ V V V /P W# V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS Q Q VSS M VSS Q Q VSS Q Q VSS M VSS K K# VSS Q Q VSS VSS Q Q VSS N M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS K V V V V RS# S# V OT V N VSS Q Q VSS M VSS Q Q VSS Q Q VSS VSS M VSS Q Q VSS Q Q VSS NTST VSS QS# QS VSS Q Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS Q Q VSS Q Q VSS K K# VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS S S VSS P R SRM SO-IMM (P) JIM FOX_S-NRN-F P R SRM SO-IMM (P) JIM FOX_S-NRN-F.U/V.U/V.U/V.U/V.U/V.U/V.U/.V/.U/.V/.U/V.U/V.U/V.U/V.U/V.U/V.U/.V/.U/.V/.U/V.U/V.U/.V/.U/.V/.U/V.U/V R K/F R K/F.U/.V/.U/.V/ R K R K.U/.V/.U/.V/.U/V.U/V.U/V.U/V.U/.V/.U/.V/.U/V.U/V.U/V.U/V.U/V.U/V.U/V.U/V R K R K R K R K.U/V.U/V.U/.V/.U/.V/.U/.V/.U/.V/.U/V.U/V.U/V.U/V N/V N/V.U/V.U/V.U/V.U/V.U/V.U/V.P/V.P/V.U/.V/.U/.V/

8 .V_R_VTT, R_K_IMM, R_K_IMM, R_K_IMM, R_K_IMM, M_OT, M_OT, M_OT, M_OT, R S, R S, R S, R W#, R S#, R RS#, R S, R S, R S, R W#, R S#, R RS# R S R S R S R W# R S# R RS# R S R S R S R W# R S# R RS# R R R R R R R R R R R R R R R R R R R R, R_S_IMM#, R_S_IMM#, R_S_IMM#, R_S_IMM# R R R R, R_S_IMM#, R_S_IMM#, R_S_IMM#, R_S_IMM# R R R R.V_R_VTT *.U/.V/_N *.U/.V/_N.U/V.U/V.U/V.U/V.U/V.U/V.U/V.U/V.U/V *.U/V_N *.U/V_N.U/V.U/V.U/V.U/V.U/V *.U/V_N.U/V.U/V.U/V *.U/V_N.U/V.U/V.U/V *.U/V_N.U/V Layout Note: Place one cap close to every pullup resistors terminated to.v_r_vtt, R M[..], R M[..] R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M RP RP RP RP RP RP RP R R PR- PR- PR- PR- PR- PR- PR- RP PR- RP PR- RP PR- RP PR- RP PR- RP PR- R R RP PR-.V_SUS.V_SUS.V_SUS.V_SUS.V_SUS *.U/V_N *.U/V_N *.U/V_N *.U/V_N *.U/V_N.V_R_VTT.V_R_VTT.V_R_VTT.V_R_VTT.V_R_VTT.V_SUS.V_SUS.V_SUS.V_SUS.V_SUS *.U/V_N *.U/V_N.U/V *.U/V_N *.U/V_N.V_R_VTT.V_R_VTT.V_R_VTT.V_R_VTT.V_R_VTT.V_SUS.V_SUS.V_SUS.V_SUS.V_SUS *.U/V_N *.U/V_N *.U/V_N *.U/V_N *.U/V_N.V_R_VTT.V_R_VTT.V_R_VTT.V_R_VTT.V_R_VTT QUNT OMPUTR RII TRMINTI Size ocument Number Rev FX ate: Thursday, November, Sheet of

9 U HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_OUT HT_OUT# HT_LKOUT HT_LKOUT# HT_LKOUT HT_LKOUT# R R R R U U U U W W Y T R U U V U V V W W Y W HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXLKP HT_RXLKN HT_RXLKP HT_RXLKN PRT OF HYPR TRNSPORT PU I/F HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXLKP HT_TXLKN HT_TXLKP HT_TXLKN P P P P M M M M L L G G J J F F N N L M K K J K G H F F F L L J J HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_IN HT_IN# HT_LKIN HT_LKIN# HT_LKIN HT_LKIN# VHT_PKG HT_TLOUT HT_TLOUT# R./F R./F HT_RXLP HT_RXLN P HT_RXTLP P HT_RXTLN HT_RXLP HT_RXLN RST HT_TXTLP HT_TXTLN HT_TXLP HT_TXLN N P HT_TXLP HT_TXLN HT_TLIN HT_TLIN# R /F_ QUNT OMPUTR RST-HT LINK I/F Size ocument Number Rev FX ate: Thursday, November, Sheet of

10 U WWN WLN WPN xpress ard PI_RX PI_RX- PI_RX PI_RX- PI_RX PI_RX- PI_RX PI_RX- G G J J J J L L L L M M M M P P R R U U P P R R GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GPP_RXP GPP_RXN GPP_RXP GPP_RXN GPP_RXP GPP_RXN GPP_RXP GPP_RXN PRT OF GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN PI I/F GFX PI I/F GPP GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN J H K K K L L L N N P P P R R R V W W W U U V V PI_TXP_ PI_TXN_ PI_TXP_ PI_TXN_ PI_TXP_ PI_TXN_ PI_TXP_ PI_TXN_ Place these caps close to connector.u/v.u/v.u/v.u/v.u/v.u/v.u/v.u/v PI_TX PI_TX- PI_TX PI_TX- PI_TX PI_TX- PI_TX PI_TX- WWN WLN WPN xpress ard LINK_NRX_STX_P LINK_NRX_STX_N LINK_NRX_STX_P LINK_NRX_STX_N LINK_NRX_STX_P LINK_NRX_STX_N LINK_NRX_STX_P LINK_NRX_STX_N LINK_NRX_STX_P LINK_NRX_STX_N LINK_NRX_STX_P LINK_NRX_STX_N LINK_NRX_STX_P LINK_NRX_STX_N LINK_NRX_STX_P LINK_NRX_STX_N V W Y Y W W S_RXP S_RXN S_RXP S_RXN S_RXP S_RXN S_RXP S_RXN PI I/F S S_TXP S_TXN S_TXP S_TXN S_TXP S_TXN S_TXP S_TXN Y Y LINK_NTX_SRX_P LINK_NTX_SRX_N LINK_NTX_SRX_P LINK_NTX_SRX_N LINK_NTX_SRX_P LINK_NTX_SRX_N LINK_NTX_SRX_P LINK_NTX_SRX_N.U/V.U/V.U/V.U/V.U/V.U/V.U/V.U/V LINK_NTX SRX_P LINK_NTX SRX_N LINK_NTX SRX_P LINK_NTX SRX_N LINK_NTX SRX_P LINK_NTX SRX_N LINK_NTX SRX_P LINK_NTX SRX_N R R *K N *.K/F N P_IST P_TXIST N(P_IST) N(P_TXIST) P_LRP(P_PL) P_LRN(P_NL) R R /F_ K/F_.V_V R: N FOR RS RST R: Ohm FOR RS R: N FOR RS R: KOhm FOR RS QUNT OMPUTR RST-PI LINK I/F Size ocument Number Rev FX ate: Thursday, November, Sheet of

11 .V_RUN L.V_RUN L KHS-T L KHS-T KHS-T, LT_STOP#.V_VQ.V_PLLV.V_HTPV.V_RUN U/.V/ U/.V/ U/.V/.V_RUN.V_RUN R.K.U/V/ Q MMST.U/V/.U/.V/ R K U/V LT_STOP#_N VG_R VG_GRN VG_LU R,R,R close to N.V_V L KHS-T.V_VPLL.U/.V/.V_RUN.V_RUN R L KHS-T TV_ TV_Y TV_VS R,R,R close to N L_LK G_LK_ G_T_ (),,, PLTRST#, N_PWRG.V_V.V_RUN_VI /F_.V_VQ Workaround ciecuit for RST pop R and depop R Pop R and depop R RT_VSYN RT_HSYN.V_PLLV.V_HTPV TV_ TV_Y TV_VS S_N_PI_RST# and R_N ohm() () R R L_ L_ L_ L_ L_ L_ L_LK- L_- L_- L_- L_- L_- L_- LPV LVR LVR L_LK L_LK L_LK- lose RSTT. L_ L_- L_ L_- L_ L_- T T L_ L_- L_ L_- L_ L_- T T L_LK L_LK- L_LK L_LK- RS: LVR=.V RS: LVR=.V R LLOW_LTSTOP LLOW_LTSTOP reserve ohm to connect "LVS_L" to L conn directly MRQ# R K HTTSTLK N_LV LK_HTRF_M N_LV *K_N *R_N HTRFLK LVS_IG I_PWM MRQ#_ SUS_STT# LVS_L G I_PWM PNL_KN SUS_STT# TVLKIN LVS_LN PNL_KN () LK_N_M ().V_PLLV OSIN.V_PLLV R *K/F_N *P_N PLLV(OSOUT) N_LV R LK_N_GFX F R *K/F_N LK_N_GFX LK_N_GFX# GFX_LKP I_PWM LK_N_GFX# GFX_LKN R K.V_RUN PNL_KN LK_N_SLINK G S_LKP G L_LK LK_N_SLINK# S_LKN R *.K_N MRQ#_ by default L_T MRQb FT_GPIO L_LK I_LK FT_GPIO R K/F R.K LO_ROM# _T L_T I_T FT_GPIO R *K/F_N FT_GPIO R *K/F_N N_THRM THRMLIO_P FT_GPIO R.K FT_GPIO SUS_STT# THRMLIO_N FT_GPIO R *K/F_N FT_GPIO.V_RUN R K TMS_HP FT_GPIO R *K/F_N R.K FT_GPIO _T TMS_HP FT_GPIO R *K/F_N MIS. _T TSTMO LO_ROM#: LO ROM STRP NL N_VOR_NTRL STRP_T N_THRM High, LO ROM STRP ISL.V_RUN Place < mils from PU RST Low, LO ROM STRP NL R.K/F *P/V_N *P/V_N *P/V_N *P/V_N R R /F /F_ R R /F /F_ R /F_ R /F U/V P/V/NPO *_N.U/.V/.U/V/.U/V R.U/V dded ().U/V R U V V G VSSN H VSSN VI VSSI VQ VSSQ _R Y_G OMP_ R F GRN G LU VSYN HSYN /F_ RST SL S PLLV(PLLV) PLLVSS HTPV HTPVSS VPLL_(V) F VPLL_(V) F VSSPLL_(VSS) G VSSPLL_(VSS) SYSRST# LT_STOP#_N POWRGOO LTSTOP# RT/TVOUT LOKs PM PLL PWR *P/V_N *P/V_N PRT OF *P/V_N *P/V_N TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN H TXOUT_LP TXOUT_LN G TXOUT_LP TXOUT_LN TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXLK_LP TXLK_LN H TXLK_UP TXLK_UN G LPV LPVSS LVR_ LVR_ LVR_(LVR_) LVR_(LVR_) LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR F LVSSR F LVSSR *P/V_N *P/V_N.U/V.U/.V/.U/V.U/.V/ *P/V_N *P/V_N L KHS-T L KHS-T.V_RUN.U/V L.V_RUN KHS-T.U/.V/ U GN V W SL S *TN-SU-._N R *K N R *.U/V_N *K/F_N L_LK N_VOR_NTRL R *K/F_N.V_V.V_PLLV L KHS-T FOR RS LY.U/V/ FT_GPIO FT_GPIO FT_GPIO[:] FT_GPIO PU by internal P by external Side-Port Memory isable Side-Port Memory nable (efault) ypassing PROM, use Using PROM Strapping default values Set PI- GPP mode to Select PI- GPP mode onf. Use default values Use the memory data bus for debug bus output RST-LVS QUNT OMPUTR Size ocument Number Rev FX ate: Thursday, November, Sheet of

12 M P G F H G J H J Y F L M M J P T N R R T T U U W Y V W M F M VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS U RST PR OF GROUN.V_RUN VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS F G Y P R M J G J L L L L M M M M N N L P P P R R R W Y U H W Y G H R Y T T V R H.V_RUN ohm() L FJHS ohm().v_v heck Trace.V_RUN.V_RUN U/.V/ U/.V/.V_RUN L.V_RUN L an Remove L share.v_v(). L.V_VR U/V SS TIG U/.V/ TIG TIG.U/V/ U/V SS.U/.V/ U/.V/ SS.V_V U/V.V_V_MM U/.V/ mil Width mil Width mil Width U/V mil Width U/.V/ U/V.U/V/ U/V U/V U/V U/V.V_V U/V U/V VHT_PKG U/V U/V U/V U/V U PRT OF V V V_HT V V_HT V V_HT V V_HT V V_HT V V_HT V V_HT V V V V VHT_PKG V_PKG V_PKG J V_ V_ J V_ V_ V_ V_ VR_ V_ VR_ V_ V_ V_ V_(V_) V_ V_(V_) V_ U V_(V_) V_ W V_(V_) V_ V_(V_) V_ V_(V_) V_ V_(V_) V_ V_(V_) V_ V_ V_ V_MM(V_VO) V_ V_MM(V_VO) V_ V_MM(V_VO) V_ V_MM(V_VO) V_ V_MM(V_VO) V_ V_MM(V_VO) V_ V_MM(V_VO) V_ V_MM(V_VO) V_ V_MM(V_VO) V_ V_MM(V_VO) V_ V_ V_ V_ V_ RST POWR G M F L M L L L M R M N N N J H P P R R U U P L J G U U mil Width U/.V/ U/V U/V U/V U/.V/ U/.V/.V_V U/.V/ N_VOR U/.V/ U/.V/.U/V.U/V.U/V.U/V.U/V.U/V.U/V hagne,,,,,, from uf to.uf() N RST POWR STTS Power Signal S S VHT VR V V V V V VI PLLV S S/S OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF G OFF OFF OFF OFF OFF OFF OFF OFF OFF HTPV VR OFF OFF OFF OFF OFF OFF LPV OFF OFF OFF LVR LVR OFF OFF OFF OFF OFF OFF RST-POWR QUNT OMPUTR Size ocument Number Rev FX ate: Thursday, November, Sheet of

13 .V_MM_VQ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_M MM_M MM_RS# MM_S# MM_W# MM_S# MM_K MM_OT MM_LKP MM_LKN L KHS-T.U/.V/ Place This P near to SRM with.". M M M N N N N P P P M P R L L F K L K L K K J K J J J N P F F H H U UM LM RS S W S K OT LK LK# VL VSSL VSS_ VSS_ VSS_ VSS_ VSS_ VSSQ_ VSSQ_ VSSQ_ VSSQ_ VSSQ_ VSSQ_ VSSQ_ VSSQ_ VSSQ_ VSSQ_ Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q UQS UQS# LQS LQS# N N N N N N VRF V_ V_ V_ V_ V_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ G G H H H H F F F L R R R J J M R G G G G MM_QS_P MM_QS_N MM_QS_P MM_QS_N MM_ MM_VRF MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_LKP MM_LKN.U/.V/.U/V.U/V.V_MM_VQ.U/V R /F.U/V.U/V MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_RS# MM_S# MM_W# MM_S# MM_K MM_OT MM_LKP MM_LKN MM_M MM_M MM_QS_P MM_QS_N MM_QS_P MM_QS_N UF PR OF W MM_(N) MM_Q/VO_VSYN(VO_VSYN) MM_(N) MM_Q/VO_HSYN(VO_HSYN) MM_(N) MM_Q/VO_(VO_) MM_(N) MM_Q/VO_(VO_) W MM_(N) MM_Q(N) MM_(N) MM_Q/VO_(VO_) MM_(N) MM_Q/VO_(VO_) MM_(N) MM_Q/VO_(VO_) MM_(N) MM_Q/VO_(VO_) MM_(N) MM_Q/VO_(VO_) MM_(N) MM_Q/VO_(VO_) Y MM_(N) MM_Q/VO_(VO_) MM_(N) MM_Q(N) MM_(N) MM_Q/VO_(VO_) MM_Q/VO_(VO_) MM_(N) MM_Q/VO_(VO_) MM_(N) MM_(N) MM_RSb(N) Y MM_Sb(N) MM_Wb(N) V MM_Sb(N) MM_K(N) Y MM_OT(N) W MM_KP(N) V MM_KN(N) MM_M(N) MM_M/VO_(VO_) S_MM/VO_I/F MM_QSP/VO_IKP(VO_IKP) MM_QSN/VO_IKN(VO_IKN) MM_QSP(N) MM_QSN(N) RST MM_OMPP(N) MM_OMPN(N) MM_VRF(N) IOPLLV(N) IOPLLVSS(N) IOPLLV(N) Y W Y MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_Q MM_OMP_P and MM_OMP_N trace width >=mils and mils spacing from other Signals in X,Y,Z directions MM_OMP_P MM_OMP_N MM_VRF.V_IOPLLV R R.V_IOPLLV L KHS-T.U/.V/./F./F.V_MM_VQ L.V_V KHS-T.U/V dded ()..U/.V/.V_RUN HYTF- Place Those P near to SRM with.". -Mbit R Mbit**bank t least mils wide and locate after R SRM.V_MM_VTT.V_MM_VQ R.U/V K/F.U/V R K/F MM_VRF.V_MM_VQ.U/V R.U/V K/F R K/F MM_VRF.V_RUN_NL.V_RUN.V_R_VTT hange Q control pin to.v_run_nl(). L TIG Q FN.V_MM_VQ U/.V/ U/.V/.V_MM_VTT U/.V/SR U/.V/SR MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_ MM_RS# MM_S# MM_W# MM_S# MM_K MM_OT RP PR- RP PR- RP PR- RP PR- RP PR- RP PR- RP PR- RP PR- R R R R R R.U/V.U/V.U/V.U/V.U/V.U/V.U/V.U/V.U/V.U/V.U/V.U/V.V_MM_VQ.V_MM_VQ.V_MM_VQ.V_MM_VQ.V_MM_VQ.V_MM_VQ Local Frame uffer(m) RII Power QUNT OMPUTR RST-Side port memory Size ocument Number Rev FX ate: Thursday, November, Sheet of

14 Reserved For MI LL LRP LRN LI.V_RUN L FMHHM-T PI Power.V_RUN L TIG R M S LIRTI RSISITOR VLU S OHM %.K % ohm U/.V/ PU_PWRG_Q P/V () S OHM % OHM %.K % mil Width mil Width Y.KHZ R M U/V K_X_R R P/V U/V U/V.V_PI_PV.V_PI_VR.V_LW LLOW_LTSTOP Ti Recommend Vendor: NSK.V_RUN Part Number: NXG.KFU PPM. R K Q NW--F H_PSLP# should be put down, reserve R for verifing,,, LK_PI_S LK_PI_S# K_X PLTRST# LINK_NRX_STX_P LINK_NRX_STX_N LINK_NRX_STX_P LINK_NRX_STX_N LINK_NRX_STX_P LINK_NRX_STX_N LINK_NRX_STX_P LINK_NRX_STX_N LINK_NTX SRX_P LINK_NTX SRX_N LINK_NTX SRX_P LINK_NTX SRX_N LINK_NTX SRX_P LINK_NTX SRX_N LINK_NTX SRX_P LINK_NTX SRX_N U/.V/ V_LW.V_PI_VR FOR S, NT TO PU_PG/LT_PG FOR S, NT TO SSMUXSL/GPIO R K U/V R K Put close S. hnage reserve level shift circuit. dd Q, R and change Q, R, R circuits.() Q MMST- PU_PWRG R K.V_RUN R K PU_PWRG T T T T, LT_STOP# () J PI_RLKP J PI_RLKN.U/V LINK_NRX STX_P P.U/V LINK_NRX STX_N PI_TXP P.U/V LINK_NRX STX_P PI_TXN M.U/V LINK_NRX STX_N PI_TXP M.U/V LINK_NRX STX_P PI_TXN K.U/V LINK_NRX STX_N PI_TXP K.U/V LINK_NRX STX_P PI_TXN H.U/V LINK_NRX STX_N PI_TXP H PI_TXN R R R *.U/V_N.V_RUN T LT_RST# R.K R /F /F_.K/F_ /F_.U/V.U/V.U/V.U/V.U/V.U/V G _RST# T PI_RXP T PI_RXN T PI_RXP T PI_RXN M PI_RXP M PI_RXN M PI_RXP M PI_RXN PI_LRP PI_LRN PI_LRP PI_LRN PI_LI PI_LI U U TI recommand have internal pull-up K_X U PI_PV PI_PVSS F PI_VR_ F PI_VR_ F PI_VR_ G PI_VR_ G PI_VR_ G PI_VR_ G PI_VR_ J PI_VR_ J PI_VR_ L PI_VR_ L PI_VR_ L PI_VR_ N PI_VR_ X S S xmm XTL X () PU_PG/LT_PG W INTR/LINT W NMI/LINT W INIT# SMI# R SLP#/LT_STP# IGNN#/SI T R *K_N M#/SI Y FRR# STPLK#/LLOW_LTSTP H PU_STP#/PSLP_V# PSLP_O#/GPIO W PRSLPVR LT_RST#/PRSTP#/PROHOT# () S PILK Part of PILK PILK PILK PILK PILK PILK SPIF_OUT/PILK/GPIO PI XPRSS INTRF PU PI INTRF PIRST# /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM #/ROM #/ROM #/ROMW# # FRM# VSL#/ROM IRY# TRY#/ROMO# PR/ROM STOP# PRR# SRR# RQ# RQ# RQ# RQ#/GPIO RQ#/GPIO GNT# GNT# GNT# GNT#/GPIO GNT#/GPIO LKRUN# LOK# INT#/GPIO INTF#/GPIO INTG#/GPIO INTH#/GPIO L L L L LFRM# LRQ# LRQ#/GNT#/GPIO MRQ#/RQ#/GPIO SRIRQ LP RT PI LKS RTLK RT_IRQ#/GPIO VT RT_GN U T U V W U V T J W Y W W Y J J H J H H H G G F J G H G F Y G J G H H F H G G F PI_LK_R R PI_LK PI_LK_R PI_LK PI_LK R PI_LK PI_LK_R R LK_PI_ LK_PI_ T PI_LK_R R PI_LK PI_LK_R LK_PI_LOM PI_LK R PI_LK_R LK_PI_PR LK_PI_LOM R LK_PI_PR, R *K_N dded k_n() PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_FRM# PI_VSL# PI_IRY# PI_TRY# PI_PR PI_STOP# PI_PRR# PI_SRR# PI_RQ# PI_RQ# PI_RQ# PI_RQ# PI_RQ# PI_GNT# PI_GNT# PI_GNT# _V_ PI_GNT# LKRUN# PI_PLOK# PI_PIRQ# F PI_PIRQ# F PI_PIRQ# F PI_PIRQ# G LP_L G LP_L H LP_L H LP_L F LP_LFRM# J LP_LRQ# H W MRQ# F IRQ_SRIRQ F RT_LK PI_[..] PI #, PI #, PI #, PI #, PI_FRM#, PI_VSL#, PI_IRY#, PI_TRY#, PI_PR, PI_STOP#, PI_PRR#, PI_SRR#, PI_RQ# PI_RQ# T T PI_GNT# PI_GNT# T _V_ LKRUN#,, T PI_PIRQ# PI_PIRQ# T PI_PIRQ# PI_[..], LP_L LP_L LP_L LP_L LP_LFRM# T WPN_RIO_IS_MINI# MRQ# IRQ_SRIRQ, RT_LK T PULL HIGH PULL LOW () hange Media ard INT()..U/V U/V *_N RQ# : LN RQ# : ard US GNT# : LN GNT# : ard US US PI PLL PIRQ# : Media ard PIRQ# : LN PIRQ# : PIRQ# : PI_GNT# PI_RQ# PI_LK PI_LK LK_PI_ PI_ PI_ PI_ PI_ PI_ US LG RST FULT US SHORT RST YPSS PI PLL () US PI LK YPSS PI LK US I PLL FULT FULT FULT YPSS I PLL Note: S has K internal PU FOR PI_[:] R () R R *K/F_N PI_ PI_ PI_ PI_ PI_ PI_.V_RUN RT_LL hange R from k to ohm(). PI_LK LK_PI_LOM LK_PI_PR R /F R.K US FULT PI STRPS US PROM PI STRPS R *.K_N LKRUN# FULT *.U/V_N R *.K_N V W SL S dded one pull down () *P/V_N R *.K_N PI_RST#, PI_ OOT FIL TIMR ISL FULT OOT FIL TIMR NL U GN *TN-SU-._N *P/V_N *P/V_N *P/V_N *P/V_N *P/V_N *P/V_N R *.K_N R *.K_N R *K_N R *.K_N Reserved k pull down() H_PSLP# R *K_N R *K_N R QUNT OMPUTR SM-PI/PI/LP Size ocument Number Rev FX ate: Thursday, November, Sheet of

15 .V_SUS.V_LW_R.V_RUN R R R *.U/V_N R.K R.K R R R R R R R R R R R R.U/V S_Z_M_ITLK S_Z_O_ITLK S_Z_M_SOUT S_Z_O_SOUT *K_N US_O_# *K_N US_O_# *K_N US_O# HT_RST# *.K_N S_TST *.K_N S_TST *.K_N S_TST SM_LRT# S_SMLK S_SMT ST_T# SIO_XT_SMI# SIO_XT_SI# S_PM# S_PI_WK# SIO_XT_WK# SYS_RST# *K_N SHUTOWN#/GPIO HT_RST# hange R pull up power rail () () Z_ITLK Z_SOUT LK_S_M hange SIO_XT_SMI# pin form U. to U.. dded TP in U. (T).() *K_N *K_N *K_N *K_N *K_N *K_N K *K_N R R *P/V_N R *P/V_N R *P/V_N R *K_N *P/V_N S_PM# SIO_XT_WK# SIO_SLP_S# SIO_SLP_S# SIO_PWRTN# S_PWRG SUS_STT# SIO_GT SIO_RIN# SIO_XT_SI# T T S_PI_WK# SIO_XT_SMI# elay ms after S powerok S_RSMRST# epop R, R () () SMK--F () R * N *P/V_N LK_S_M SPKR T _SOUT S_Z_O_SIN S_Z_M_SIN T () T I_RST_MO S_Z_M_SYN US_O# XP_R_S_WK US_O_# US_O_# For S, depopulate R For S, populatet R S_Z_O_SYN S_Z_M_RST# S_Z_O_RST# T T T T T T T T S_PM# SIO_XT_WK# SIO_SLP_S# SIO_SLP_S# SIO_PWRTN# SUS_STT# S_TST S_TST S_TST SIO_GT SIO_RIN# SIO_XT_SI# S_STT SYS_RST# S_PI_WK# SIO_XT_SMI# SM_LRT# S_RSMRST# GPIO GPIO GPIO GPIO GPIO SHUTOWN#/GPIO SPKR S_SMLK S_SMT ST_T# US_O# US_O_# US_O_# Z_ITLK Z_SOUT _SIN Z_SYN Z_RST# _ITLK_R _SOUT S_Z_O_SIN S_Z_M_SIN US_I# _SYN I_RST_MO ddedpull down resistor to follow k. () R *K_N R *P/V_N R *P/V_N R *P/V_N R *P/V_N Z_SYN Z_RST# PI_PM#/GVNT# Part of RI#/XTVNT# F SLP_S# SLP_S# PWR_TN# PWR_GOO SUS_STT# F TST TST G TST F GIN G KRST# LP_PM#/GVNT# LP_SMI#/XTVNT# S_STT/GVNT# F SYS_RST#/GPM# WK#/GVNT# LINK/GPM# G SMLRT#/THRMTRIP#/GVNT# U RSMRST# M_OS ST_IS#/GPIO ROM_S#/GPIO GHI#/ST_IS#/GPIO W_PWRG/GPIO SMRTVOLT/ST_IS#/GPIO SHUTOWN#/GPIO SPKR/GPIO SL/GPO# S/GPO# SL/GPO# F S/GPO# _SL/GPIO _S/GPIO SSMUXSL/ST_IS#/GPIO LL#/GPIO US_O#/SLP_S/GPM# US_O#/Z_OK_RST#/GPM# US_O#/GVNT# US_O#/GVNT# US_O#/R_RST#/GPM# US_O#/GPM# US_O#/GPM# US_O#/GPM# US_O#/GPM# US_O#/GPM# N Z_ITLK M Z_SOUT K Z_SIN/GPIO L Z_SYN K Z_RST# L _ITLK/GPIO L _SOUT/GPIO L Z_SIN/GPIO J Z_SIN/GPIO J Z_SIN/GPIO M _SYN/GPIO L _RST#/GPIO N N N N N T N N N S S S xmm OS / RST ZLI US O GPIO PI / WK UP VNTS US INTRF US PWR USLK US_ROMP US_TST US_TST US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- VTX_ VTX_ VTX_ VTX_ VTX_ VRX_ VRX_ VRX_ VRX_ VRX_ V VSS VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ () US_ROMP H G G H G H G H G H F F F F F F F G G H H J J J J J J R T T R.K/F USP USP- USP USP- USP USP- USP USP- USP USP- USP USP- USP USP- USP USP- USP USP- USP USP-.U/V * N.U/V LK_S_M WWN Left op WPN xpress ard amera Left Top ack ot. ck Tot. Side ot. Side Top US power *P/V_N.U/V PL, N LOS TO U.V_RUN R.K Q NW--F S_SMT R.V_RUN Q NW--F S_SMLK U/.V/.U/V/ R U/V *_N *_N Use Plane Shape for.v_v_us and.v_v U/V.V_V_US U/V.U/V.V_V L MM_ST MM_SLK QUNT OMPUTR SM PI/US/ U/V R.K L TIG mil Width SKT-Y-S mil Width.V_SUS MM_ST,,, MM_SLK,,, Size ocument Number Rev FX ate: Thursday, November, Sheet of

16 _SOUT RT_LK PI_LK, LK_PI_PR PI_LK PI_LK PULL HIGH PULL LOW ST Power.V_RUN SKT-Y-S.V_RUN SKT-Y-S.V_ST_V.V_RUN TIG_ L.V_ST_V K internal PU for RT_LK,xternal PU/P is not required. S has K internal P for _SOUT L L _SOUT US UG STRPS IGNOR UG STRPS FULT *SKT-Y-S_N L RT_LK INTRNL RT FULT XTRNL RT mil.v_run.v_run.v_run.v_run.v_run.v_run PI_LK US INT. PLL US XT. MHZ FULT.V_XTLV_ST mil.v_pllv_st mil epop L, L and pop L L(). *TIG N L U/.V/ R *K_N U/V.U/V R *K_N R *K_N *U/.V/_N U/V U/.V/ U/V R *K_N LK_PI_PR U/V PU IF=K FULT PU IF=P RQUIR STRPS.V_V_ST.U/V.U/V R *K_N R K.U/V R K R *K_N PI_LK H, H = PI ROM H, L = SPI ROM R K L, H = LP ROM L, L = FWH ROM R *K_N SIO_SPI_S#,.V_RUN_ R K PI_LK FULT SPI_S#.V_RUN Fot ST issue where the interface is being dropped down to PIO mode when ST is used in an I configuration. Will fix for this issue implemented in. U *SH_N R ST_T#.V_LW () *.U/V_N.V_PLLV_ST.V_XTLV_ST.V_V_ST elete, R, R. dd,,r,r. hange U.() R *K_N *.U_N U GN IN N OUT RST#/F GN *TPS_N R R *_N.V_ST_V R *.K_N R *.K_N.U/V.U/V K/F SPI_S# *U_N T T T T.U/V.U/V T T T T ST_TX_ ST_TX-_ ST_TX_ ST_TX-_ ST_L ST_X ST_X H ST_RX- J ST_RX H ST_TX J ST_TX- H ST_RX- J ST_RX H ST_TX J ST_TX- H ST_RX- J ST_RX ST_TX ST_TX- ST_RX- ST_RX ST_TX ST_TX- ST_RX- ST_RX H ST_TX H ST_TX- H ST_RX- J ST_RX J ST_TX H ST_TX- F PLLV_ST_ J PLLV_ST_ U ST_L ST_X ST_X ST_T#/GPIO XTLV_ST V_ST_ V_ST_ V_ST_ V_ST_ F V_ST_ F V_ST_ G V_ST_ G V_ST_ H V_ST_ H V_ST_ J V_ST_ J V_ST_ J V_ST_ J V_ST_ J V_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ F VSS_ST_ F VSS_ST_ F VSS_ST_ F VSS_ST_ G VSS_ST_ G VSS_ST_ G VSS_ST_ G VSS_ST_ G VSS_ST_ G VSS_ST_ G VSS_ST_ G VSS_ST_ G VSS_ST_ G VSS_ST_ H VSS_ST_ H VSS_ST_ S ST clock Option P_V Y P_V MHZ_ST R M ST_X ST_X T / J SPI_I/GPIO J SPI_O/GPIO G SPI_LK/GPIO G SPI_HOL#/GPIO G SPI_S#/GPIO LN_RST#/GPIO G ROM_RST#/GPIO M FNOUT/GPIO T FNOUT/GPIO V FNOUT/GPIO N FNIN/GPIO P FNIN/GPIO W FNIN/GPIO TMP_OMM TMPIN/GPIO TMPIN/GPIO TMPIN/GPIO TMPIN/TLRT#/GPIO V VIN/GPIO L VIN/GPIO M VIN/GPIO V VIN/GPIO M VIN/GPIO VIN/GPIO P VIN/GPIO M VIN/GPIO V V VSS S SPI_IN S SPI_O S SPI_LK SPI_S# PI_WLN_T# US_WLN_T# PI_WWN_T# US_WWN_T# PI_WPN_T# P P US_WPN_T# P R T RT_T_T# T MINILK_RQ# N M S_WWN_PI_RST# S_WLN_PI_RST# S_WPN_PI_RST# S_GPIO LF_I LF_I LF_I mil ().V_RUN LF_I LF_I LF_I.V_V_HWM MINILK_RQ# S SPI_IN S SPI_O S SPI_LK T T PI_WLN_T# US_WLN_T# PI_WWN_T# US_WWN_T# PI_WPN_T# T US_WPN_T# SPKR_T# RT_T_T# MINILK_RQ# S_WWN_PI_RST# S_WLN_PI_RST# S_WPN_PI_RST# T MINILK_RQ# PI_WLN_T# PI_WPN_T# PI_WWN_T# US_WWN_T# US_WPN_T# US_WLN_T# SPKR_T# RT_T_T# S_WWN_PI_RST# S_WLN_PI_RST# S_WPN_PI_RST#.V_RUN QUNT OMPUTR SM H/POWR.V_RUN S S xmm I_IORY I_IORY Part of I_IRQ I_IRQ I_ I_ I_ I_ Y I_ I_ I_K# I_K# I_RQ I_RQ I_IOR# I_IOR# I_IOW# I_IOW# W I_S# I_S# W I_S# I_S# I_ I_[..] I_/GPIO I_ I_/GPIO I_ I_/GPIO F I_ I_/GPIO G I_ I_/GPIO H I_ I_/GPIO J I_ I_/GPIO J I_ I_/GPIO H I_ I_/GPIO G I_ I_/GPIO G I_ I_/GPIO F I_.V_LW_R I_/GPIO F I_ I_/GPIO I_ I_/GPIO I_ I_/GPIO I_ R I_/GPIO SPI_S# *K_N SRIL T SRIL T POWR R R R SPI ROM HW MITOR R K K K *K_N R *K_N R *K_N T T SPKR_T# S_N_PI_RST#, R ohm and ddded Test padt.() L SKT-Y-S.U/V/.U/V HWM_GN R R R R R R R R R R R Remove R() *K_N () ate: Friday, November, Sheet of.v_run K K K K K K K K K R K R K R K Size ocument Number Rev FX

17 V_VRF.V_VK V_VRF.V_V_S_R.V_LW_R.V_S_R.V_SUS_.V_RUN V_RUN.V_VK.V_SUS.V_LW_SUS.V_RUN.V_RUN.V_RUN.V_RUN.V_RUN.V_LW.V_LW_R V_LW V_LW.V_LW_SUS.V_SUS.V_SUS.V_S_R.V_V_S_R Size ocument Number Rev ate: Sheet of QUNT OMPUTR FX SM STRPS Thursday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTR FX SM STRPS Thursday, November, Size ocument Number Rev ate: Sheet of QUNT OMPUTR FX SM STRPS Thursday, November, ohm/ ohm/ mil Width mil Width mil Width Put very close P/V/ P/V/ U/V U/V.U/V/.U/V/ U/.V/ U/.V/ U/V U/V.U/V.U/V.U/V.U/V U/V U/V Q FN Q FN.U/V.U/V U/V U/V.U/V.U/V Q NW Q NW.U/V/.U/V/ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ W VSS_ V VSS_ V VSS_ V VSS_ V VSS_ V VSS_ U VSS_ T VSS_ R VSS_ R VSS_ P VSS_ P VSS_ P VSS_ N VSS_ N VSS_ M VSS_ M VSS_ L VSS_ L VQ_ VQ_ VQ_ VQ_ VQ_ L VQ_ L VQ_ M VQ_ P VQ_ P VQ_ T VQ_ V VQ_ W VQ_ W VQ_ W VQ_ W VQ_ VQ_ VQ_ VQ_ VQ_ PU_PWR V_VRF S_.V_ H US_PHY_.V_ V_ N V_ M V_ N V_ R V_ U V_ R V_ M V_ N V_ U VSS_ J VSS_ J VSS_ G VSS_ F S_.V_ G S_.V_ H S_.V_ H VK_.V VSSK VSS_ G VSS_ J VSS_ J VSS_ J V_ U V_ V V_ V S_.V_ VQ_ VQ_ VQ_ VQ_ H VQ_ J VSS_ U S_.V_ S_.V_ F S_.V_ J S_.V_ J S_.V_ K US_PHY_.V_ US_PHY_.V_ US_PHY_.V_ VSS_ Y VSS_ VQ_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ F VSS_ VSS_ M VSS_ M US_PHY_.V_ VK_.V VQ_ J VQ_ J PI_VSS_ PI_VSS_ PI_VSS_ PI_VSS_ G PI_VSS_ G PI_VSS_ G PI_VSS_ H PI_VSS_ J PI_VSS_ J PI_VSS_ K PI_VSS_ L PI_VSS_ L PI_VSS_ L PI_VSS_ L PI_VSS_ L PI_VSS_ M PI_VSS_ M PI_VSS_ M PI_VSS_ N PI_VSS_ N PI_VSS_ P PI_VSS_ P PI_VSS_ P PI_VSS_ P PI_VSS_ P PI_VSS_ P PI_VSS_ T PI_VSS_ T PI_VSS_ T PI_VSS_ T PI_VSS_ T PI_VSS_ U PI_VSS_ V PI_VSS_ V PI_VSS_ V PI_VSS_ V PI_VSS_ V PI_VSS_ V PI_VSS_ V VSS_ R VSS_ T VSS_ V VSS_ W VSS_ PI_VSS_ F PI_VSS_ J PI_VSS_ V Part of S S xmm POWR U S Part of S S xmm POWR U S.U/V.U/V.U/V.U/V L FJHS L FJHS U/V U/V R * N R * N U/.V/ U/.V/.U/V.U/V.U/V.U/V.U/V.U/V U/.V/ U/.V/ U/V U/V U/V U/V U/V U/V U/V U/V.U/V.U/V.U/V.U/V.U/V.U/V U/V U/V.U/V.U/V Q NW Q NW.U/V.U/V RVTG RVTG L SKT-Y-S L SKT-Y-S U/V U/V.U/V.U/V U/V U/V.U/V.U/V.U/V.U/V R * N R * N U/.V/ U/.V/.U/V.U/V.U/V.U/V U/V U/V.U/V.U/V L *SKT-Y-S_N L *SKT-Y-S_N.U/V.U/V L SKT-Y-S L SKT-Y-S R K/F R K/F.U/V.U/V U/.V/ U/.V/.U/V.U/V.U/V.U/V R K R K PJP POWR_JP PJP POWR_JP L FJHS L FJHS.U/V.U/V.U/V.U/V.U/V.U/V R K R K U/.V/ U/.V/.U/V.U/V U/V U/V.U/V.U/V.U/V.U/V.U/V.U/V.U/V.U/V.U/V.U/V

18 .V_RUN L FMHHM.V_LK.V_LK( mils) () U/.V/ P/V.U/V.U/V P/V.U/V P/V P/V.U/V () - PL LL SRIL TRMINTI RSISTORS LOS TO U - PUT OUPLING PS LOS TO lock Gen.POWR PIN () () L.V_RUN KHS-T.U/V U/.V/.V_RUN L KHS-T VS_LK_V.V_LK U.V_RUN L KHS-T LOK_NL# KG_SMT ohm/ m ohm/ m Remove R pull up Resistor(). SMbus address These are for backdrive issue. ().V_LW U/V U/V ().V_RUN VS_LK_VRF.U/V GN_PU GN_SR GN_SR GN_SR Parallel Resonance rystal GN_SR P/V GN_ GN_TIG GN_RF R GNHTT *M/F_N XTLIN_LK P/V XIN XTLOUT_LK_ R XTLOUT_LK Y XOUT.MHZ Ioh = * Iref (.m) Voh ohm Place R less than mils from lock Gen. LK_SLK LK_ST LKRF () R RP.K PR-.K FS R.K FS R.K FS R.K Q LK_ST.U/V R /F VPU V_SR V_SR V_SR V_SR V_ V_TIG V_RF VHTT RST_IN# N SMLK SMT IRF SLGTTR R.K R V GN PULKT PULK PULKT PULK SRLKT SRLK TIGLKT TIGLK TIGLKT TIGLK TIGLKT TIGLK TIGLKT TIGLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK LKRQ# LKRQ# LKRQ# MHz_ MHz_ FS/RF FS/RF FS/RF HTTLK R.K R.V_RUN.V_LK_V PULK_R PULK_R# N_GFX N_GFX# PI_XPR PI_XPR# PI_MINI PI_MINI# N_SLINK N_SLINK# PI_MINI PI_MINI# PI_MINI PI_MINI# PI_S PI_S# R_LK_RQ_R# MINILK_RQ_R# MINILK_RQ_R# R.K R LK_S FS FS FS HTRFLK R R R /F R /F T T R /F R /F R /F R /F R /F R /F R /F R /F R /F R /F R R R R /F R /F R /F R /F R /F R /F R./F./F_./F_ R_LK_RQ# MINILK_RQ# MINILK_RQ# *P/V_N *P/V_N LK_S_M *P/V_N R /F *P/V_N R./F R./F R./F R./F R./F R./F LK_N_M LK_S_M LK_HTRF_M MINILK_RQ_R# R R./F R./F R./F K R./F R./F R./F R./F.V_RUN R./F PU_LK PU_LK# LK_N_GFX LK_N_GFX# LK_PI_XPR LK_PI_XPR# LK_PI_MINI LK_PI_MINI# LK_N_SLINK LK_N_SLINK# LK_PI_MINI LK_PI_MINI# LK_PI_MINI LK_PI_MINI# LK_PI_S LK_PI_S# NW--F *.K_N *.K_N *.K_N MINILK_RQ_R# R K R *_N R_LK_RQ_R# R K KG_SMLK.V_LW.V_RUN R.K Q NW--F R *_N LK_SLK XT LK FRQUNY SLT TL(MHZ) FS FS FS PU Hi-Z X.... PI.. US SRLK HTT [:].. Hi-Z X/ X/... Hi-Z.... OMMNT Reserved Reserved Reserved Reserved Reserved Reserved..... Normal THL operation heck M clock LKRQ# TROL SR LKRQ# TROL SR LKRQ# TROL SR QUNT OMPUTR LOK GNRTOR Size ocument Number Rev FX ate: Thursday, November, Sheet of

19 J L_LK- LV L_LK.V_RUN L_- L_ L_- L_.U/V.U/V.U/V L_- L_ L_LK- L_LK lose onnectot. lose onnectot. L_- L_ L_- L_ L_- L_ L LMSN L_LK L LMSN L_T () L LMS G_PWR_SR_L G_PWR_SR PWR_SR.V_RUN V_LW V_LW L LMPGSN LV mil mil mil Q L L_TST SIV-T- G_PWR_SR_L L_SMLK L_SMT LMSN () () R KLIT K *U_N *U_N L LMSN L_SMLK L LMSN L_SMT lose onnectot. lose onnectot. L LMS V_LW () LMP STT# INV_PWR_SR_ T () J_FI-TS-VF-R () dress : H --ontrast H --acklight SMUS ddress.u/v/,, RUN_ Q NW--F This is a fix for an errata( P_RSX) Q SS_NL V_LW N_LV_Q N_LV.V_RUN LV.V_RUN Q FN R R K K N_PWRG_V R *K_N V_LW.U/V R KLIT LV_ R KLIT K I_PWM SS_NL Q.U/V Q NW--F.V_SUS.U/V *P/V_N *P/V_N.U/V.U/V/.U/V/ R K INV_PWR_SR R R R * N K RVTG N_LV_Q V_RUN R K LV_TST_N RVTG Q TU Q R K NW--F, N_PWRG N_PWRG N_PWRG_V Q NW--F QUNT OMPUTR L N&K-SS Size ocument Number Rev FX Thursday, November, ate: Sheet of

20 L VG_R R LMS P T M_SN#_R.V_RUN L VG_GRN GRN LMS R _.U/V VG_LU L R LU LMS RT_V_R R R R JVG /F /F /F *U_N *P/V_N *P/V_N *P/V_N *P/V_N *P/V_N *P/V_N.V_RUN.V_RUN U_V GRN P T M_I# U_V RP RP PR-.K PR-.K *U_N Q SS_NL SMK--F FOX_Z-N-F.V_RUN V_RUN G_T_ R K U_V.V_RUN LU U R R G_LK_ VGHSYN_R RT_HSYN *U_N RT_VSYN R VGVSYN_R VGHSYN_ VGVSYN_ R JTV */F_N P/V P/V.V_RUN TV_Y.V_RUN *P/V_N SVIO_VS TV_VS L R V_RUN LMSN K_ R () *U_N */F_N P/V P/V SP_IF_.U/V R K Populate R & e-populate R Place,, close Place ll of those Inductors R when component VIO is enable. to JTV < mils * N aps close to JTV < mils *P_N U_SPIF_OUT R.U/V Setting R,G, trace impedance to ohm. HTGGW U HTGGW Place near U and U < mil TV_ R */F_N SVIO_ SVIO_VS SVIO_Y SP_IF SP_IF SP_IF SP_IF_ R /F_.U/V R _ U HTGGW *P/V_N L LMSN P/V *P/V_N L LMSN Q SS_NL P/V R _ *P/V_N *P/V_N *P/V_N *P/V_N V_RUN L LM L LM JVG_HS JVG_VS P/V Place near JVG connector < mil P/V FOX_MHL-GN-F RT_V dded FS() () SMK--F RT&TV N.V_RUN.V_RUN QUNT OMPUTR Place,, close to JVG < mils SVIO_ SVIO_Y Size ocument Number Rev FX. *U_N *U_N ate: Friday, November, Sheet of

21 .V_R.V_R.V_R U/.V/.U/V.U/V.U/V.U/V.U/V U Place the power caps close to the relation pins..v_run.v_r U/.V/.U/V.U/V.U/V Place the power caps close to the relation pins. V_PI V_PI V_PI V_PI V_PI V_PI V_V.U/V U/.V/ R _ V_RIN.U/V.U/V.U/V/.U/V/ V_ROUT V_ROUT V_ROUT V_ROUT V_ROUT V_M, PI_[..] GN PI_ GN PI us PI_ GN PI_ GN PI_ GN PowerOnReset for Vccore PI_ GN PI_ GN PI_ GN PI_ GN PI_ GN PI_.V_R PI_ PI_ GN.V_R PI_ GN PI_ GN PI_ GN R PI_ GN K PI_ R Route to GPIOG (pin ) on the.v_r.v_r PI_ K SIO companion chip, with PI_ the signal named _HWSPN# PI_ PI_ GRST# should be asserted only PI_ U/V/ PI_ HWSPN# R when system power supply is on. R PI_ K K PI_ PI_ Memory Stick nable PI_ MSN PI_ X ard nable PI_ XN PI us PI_ PI_ Serial ROM disable PI_ UIO S ard nable, PI_PR PR MM ard nable, PI # /# UIO, PI # /# UIO, PI # /#, PI # PI_ /# UIO () R ISL UIO PI_RQ# RQ# PI_GNT# GNT# UIO/SRIRQ# IRQ_SRIRQ,, PI_FRM# FRM#, PI_IRY# IRY#, PI_TRY# TRY# PI us, PI_VSL# VSL# Interrupt, PI_STOP# STOP# INT# PI_PIRQ#, PI_PRR# PRR# Media card Interrupt, PI_SRR# SRR# INT# PI_PIRQ#,,,,, PI_RST# LK_PI_PR orelogic LOKRUN# SYS_PM# LKRUN# R *_N The IH schematics need to include a pull-up resistor to implement LKRUN#, and the IH schematics must have a pull-down, or constantly drive thesignal low, in order to disable LKRUN#. LK_PI_PR R *_N *P/V_N GRST# PIRST# PILK PM# LKRUN# RT_V PI / OTHR Refer to LL M schematic X TST R K T P QUNT OMPUTR IN TROLLR Size ocument Number Rev FX. Thursday, November, ate: Sheet of

22 mils.v_r.v_run_phy L LMPGSN U modify U/.V/.U/V.U/V P/V () V_PHY V_PHY V_PHY V_PHY TPIS Place these caps as close to the U as possible. S LOS S POSSIL TO R TPIS.U/V/ P/V _XI Y.MHz/.pF/ppm XI TPN R R./F_./F_.U/V TPN P/V _XO R XO TPP TPP *TPP/TPN,TPP/TPN pair trace : s close as possible. TPN *TPP/TPN,TPP/TPN pair trace : Same length electrically. TPN *Termination resistor for TP/- TP/- : s close as possible to its cable driver (device pin out). RIOH_FILO TPP.U/V FIL TPP RIOH_RXT R K/F RXT RIOH_VRF.U/V VRF I/S R R P/V./F_./F_ R.K/F Place these caps as close to the U as possible. MIO MIO MIO MIO ircuit area : s small as possible. X_T X_T X_T X_T X_T X_T X_T X_T L *LWHNSQ_N S LOS S POSSIL TO NTOR. FOX_UV-WSU-F MIO MIO MIO MIO S/X/MS_T S/X/MS_T S/X/MS_T S/X/MS_T S/X/MS_T S/X/MS_T S/X/MS_T S/X/MS_T TPN TPP TPN TPP R _ R _ R _ R _ TP TP- TP- TP MIO X_WP# S/X/MS_M MIO S/X/MS_M.V_R MIO X_L MIO X_L L MIO *LWHNSQ_N X_# R S_WP#(XR/#) MIO S_# MIO S_# R_MS_INS# MIO MS_INS# S_WP#(XR/#) SS SS *K_N close to the hip X_SW# MIO S/X/MS_LK MIO M_PWR_TRL_.V_R RSV MIO MIO T P S/X/MS_T R *.K_N RT_V S/X/MS_T R *.K_N R *.K_N S/X/MS_T R *.K_N S/X/MS_T () R *.K_N S/X/MS_M QUNT OMPUTR I Size ocument Number Rev FX. Thursday, November, ate: Sheet of

23 .V_RUN_R.V_RUN_R.V_RUN_R R.U/V.U/V.U/V K S_# S_# S_WP#(XR/#) X_T X_T X_T S/X/MS_T X_T S/X/MS_T S/X/MS_T S/X/MS_T S/X/MS_T S/X/MS_M S/X/MS_LK S/X/MS_T S/X/MS_T S/X/MS_T R IN R RR S/X/MS_T S/X/MS_T X_WP# S/X/MS_LK S/X/MS_M S/X/MS_M S/X/MS_T X_L S/X/MS_T X_L X_# S/X/MS_LK S_WP#(XR/#) X_SW#.U/.V/ lose pin S(/WP/GN) S() S(WP) X-(V) X-() X-() X-() S-(T) X-() S-(T) X-() X-() S-(GN/VSS) MS-(VSS) X-() MS-(S) S-(LK) MS-(V/T) X-() MS-(SIO/T) S-(V/V) TI-SOL - MS-(T) X-(GN) MS-(INS) S-(VSS) MS-(T) X-(-WP) MS-(SLK) S-(M) MS-(V) X-(W) MS-(VSS) S-(T) X-(L) S-(T) X-(L) X-() X-(R) X-(R/-) X-() X-(GN) *P/V_N R MS_INS#.V_R M_PWR_TRL_ N GN TPSV U/V/ X_SW# S_WP#(XR/#) X_T X_T U IN N OUT.V_RUN_R.U/V T will be tested by 'nd source after proto build. X_T X_T S/X/MS_T S/X/MS_T S/X/MS_T S/X/MS_T S/X/MS_M X_WP# X_L X_L X_# S/X/MS_LK QUNT OMPUTR R RR N Size ocument Number Rev FX. Thursday, November, ate: Sheet of

24 ST ST_TX ST_TX- ST_RX- ST_RX For Yesubi pop ohm.v_run ().U/V.U/V V_H ST_RX-_ ST_RX_ GN RXP RXN GN TXN TXP GN.V_.V_.V_ GN_ GN_ GN_ V_ V_ V_ GN_ RSV GN_ V_ V_ V_ GN RXP RXN GN TXN TXP GN.V_.V_.V_ GN GN GN V_ V_ V_ GN RSV GN V_ V_ V_ ST ST_RX-_ ST_RX_.V_RUN V_H.U/V.U/V ST_TX ST_TX- ST_RX- ST_RX () PLTFORM_I dded one H detect pin.() O onnector. R *_N,,, PLTRST# R I_RST_MO I_RST_MO I_ I_.V_RUN I_ I_ I_ I_ I_ R I_.K I_IOW# I_IORY I_IRQ I_ V_RUN I_ I_S# I_L# R /F V_RUN R *_N V_RUN V_RUN I_ I_ I_ I_ I_ I_ I_ I_ I_RQ I_IOR# I_K#_R R I_ R K I_S# I_K# V_RUN FOX_QT-S-F Pin. able select H=Slave,L=Master Tyco_- V_H R *U/V/_N *U/V/_N *U/V/_N *.U/V/_N.V_RUN *U/V/_N For Yesibu ll N *.U/V/_N P/V/ *.U/V/_N *P/V/_N I_[..] I_RQ I_IOW# I_IOR# I_IORY I_K# I_IRQ I_ I_ I_S# I_ I_S# I_[..] I_RQ I_IOW# I_IOR# I_IORY I_K# I_IRQ I_ I_ I_S# I_ I_S# U/.V/ V_RUN U/V/.U/V Place closed to MO connector P/V.U/V V_LW V_LW V_LW V_H V_RUN H_N R K R K H_N# Q NW--F R K H_N Q NW--F Q SIV.U/V/.U/V/ () R K R */_N ST T onn. Nut TH TH H-P- H-P- ST PWR dded one level shift circuit() QUNT OMPUTR ST (H&_ROM) Size ocument Number Rev FX. ate: Monday, November, Sheet of

25 Miniard WLN connector ().V_RUN.V_WLN.V_WLN.V_WLN.V_RUN MINILK_RQ# *.U/V_N,, PI_WK# OX_WLN_TIV OX_T_TIV MINILK_RQ# LK_PI_MINI# LK_PI_MINI HOST_UG_RX _TX PI-xpress TX and RX direct to connector PI_TX- PI_TX PI_RX- PI_RX R R MINILK_RQ# PI_WLN_T# Non-iMT T P T P T P RSV_IH_L_LK RSV_IH_L_T RSV_IH_L_RST# () WLN_RIO_OFF# R *P/V/_N () HOST_UG_TX PLTRST_SYS#,,, S_WLN_PI_RST# () MM_SLK,,, MM_ST,,, T T () US_WLN_T# _RX L_WLN_OUT# T_TIV# () ().V_WLN Suport for WoW WLN_RIO_OFF# Place caps close to connector J. WLN_RIO_IS# Prevent backdrive when WoW is enabled. WLN Power Switch () V_LW V_LW.V_LW.V_WLN.V_RUN ().V_RUN.V_RUN WLN_V_NL JMINI Pin UG PINS ebug Pin Name HOST_UG_TX HOST_UG_RX _TX _RX Pin.V_RUN Place caps close to connector J. () Miniard WPN connector.v_run.v_run.v_run R.K R.K R R R *_N *_N *_N *P/V/_N PR *K_N.U/V J MOLX_-.U/V.U/V RVTG PQ *FN_N R / PR *K_N PQ *NW--F_N.U/V J.U/V.U/V PQ *NW--F_N R *_N.U/V.U/V.U/V/ J UIM_ UIM_ GN PRn PRp GN GN PTn PTp GN RSRV_ RSRV_ RSRV_ RSRV_ RSRV_ RSRV_ RSRV_ RSRV_ MOLX_-.V_ GN.V_ UIM_PWR UIM_T UIM_LK UIM_RST UIM_VPP WK# RSRV_ RSRV_ LKRQ# GN RFLK- RFLK GN GN W_ISL# PRST#.VUX GN.V_ SM_LK SM_T GN US_- US_ GN L_WWN# L_WLN# L_WPN#.V_ GN.V_ R *_N.U/V PR *K_N P *.U/V/_N P.U/V R *K_N PR *K_N P *P/V/_N.U/V.U/V.U/V.U/V.U/V.U/V/ () () MINILK_RQ# *.U/V_N,, PI_WK# R OX_WLN_TIV R OX_T_TIV_MINI MINILK_RQ# MINILK_RQ# LK_PI_MINI# LK_PI_MINI PI_RX- PI_RX PI-xpress TX and RX direct to connector PI_TX- PI_TX PI_WPN_T# WK#.V_ RSRV_ GN RSRV_.V_ LKRQ# UIM_PWR GN UIM_T RFLK- UIM_LK RFLK UIM_RST GN UIM_VPP UIM_ GN UIM_ W_ISL# GN PRST# PRn.VUX PRp GN GN.V_ GN SM_LK PTn SM_T PTp GN GN US_- RSRV_ US_ RSRV_ GN RSRV_ L_WWN# RSRV_ L_WLN# RSRV_ L_WPN# RSRV_.V_ RSRV_ GN RSRV_.V_ MOLX_- USP - USP () R R *_N WPN_RIO_IS_MINI# () () MM_SLK,,, MM_ST,,, US_WPN_T# L_WPN# PLTRST_SYS#,,, S_WPN_PI_RST# hange USP_- Net Name form US_-(). () J MOLX_- USP - USP MINI-PI hange USP- Net Name form US-(). L *PLWSSQT_N R R Pop R, R() QUNT OMPUTR USP- USP Layout Note: R and R close to choke as possible to minimize stubs. Size ocument Number Rev FX. ate: Thursday, November, Sheet of