AJ6 SYSTEM DIAGRAM. AMD Griffin S1G2 Processor 638P (upga)/35w PAGE 3,4,5. Lion Sabie HT3. PCI-Express 16X NORTH BRIDGE RS780MN

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1 LYER : TOP LYER : SV LYER : IN LYER : IN LYER : LYER : OT P STK UP LN PIE-LN MRVELL_E (//GagaLN) PGE RII-SOIMM RII-SOIMM J SYSTEM IGRM PGE, PGE, Express ard X (NEW R) PGE RII / MHz RII / MHz Mini PI-E ard (Wireless LN) PI-E PGE M Griffin SG Processor P (upg)/w PGE,, HT NORTH RIGE RSMN PGE,,,, Lion Sabie mm X mm, pin G PU THERML SENSOR PI-Express X PGE HMI PGE RT PGE LVS PGE PU_LK NGFX_LK NGPP_LK SLINK_LK MXM ONN PGE.MHz LOK GEN SLGSP PGE SYSTEM HRGER SYSTEM POWER R II SMR_VTERM.V/.VSUS VP +.V & +.V PGE PGE PGE PGE RJ PGE ST - H PGE ST - O PGE ST M ST M PIE X SOUTH RIGE S mm X mm, pin G.W(Ext).W(Int) PGE,... US. amera PGE zalia X luetooth PGE PI US / MHz, Mini PI-E X PGE R reader OZT PGE SSR_LK,,, Express US. Ports ard X (NEW R) X PGE PGE US (small/) X PGE PU ORE +VORE +VORE PGE SMUS TLE lock gen S--SL/S /R/R thermal/ccelerometer S--SL/S S--SL/S E --SL/S E--SL/S Wlan ard epress card attery charge/discharge VG thermal/system thermal +V +V/S +v/s +VPU +V Keyboard Touch Pad PGE PGE FN K LP ITE IT PGE PGE SPI FLSH PGE M ONN PGE RJ PGE UIO ONN (Phone/ MI) PGE UIO OE PGE UIO mplifier TP PGE Speaker onn. PGE N/R PROJET : J Quanta omputer Inc. Size ocument Number Rev ustom lock iagram ate: Monday, ugust, Sheet of

2 ohm,. LOKS name UM RS lock pin function +.V L LMPGSN(,.)_ ohms@mhz P/V/NPO_ EMI request. // U/.V_ +.V_LKVIO.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_ NGFX_LKP NGFX_LKN EXT_GFX_LKP EXT_GFX_LKN RP STUFF RP N RP STUFF RP STUFF to N for VG reference clock to M-M external reference clock +.V R:. ohm ohms@mhz +V_LKV L LMPGSN(,.)_ ohm,. U/.V_ +V_LKV.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_ NGPP_LKP NGPP_LKN RP STUFF RP N SLINK_LKP SLINK_LKN RP STUFF RP STUFF to N for RX for PIEX interface reference clock only RS is internal share with -LINK clock,rs not need to N for -LINK reference clock EMI reserved +V_LKV L LMPGSN(,.)_ P/V/NPO_ Y.MHZ P/V/NPO_.U/.V/XR_ Place very close to /G G_XIN G_XOUT +V_LK_V.U/V/XR_ +V_LKV +.V_LKVIO G_XIN G_XOUT U VOT VSR VTIG VS_SR VST VPU VHTT VREF V VSR_IO VSR_IO VTIG_IO VS_SR_IO VPU_IO OT SR SR TIG S_SR ST PU HTT REF X X QFN PUK_T PUK_ TIGT TIG TIGT TIG S_SRT S_SR S_SRT S_SR SRT SR SRT SR SRT SR SRT SR SRT SR SRT/STT SR/ST SRT/M_SS SR/M_NS PULKP PULKN NGFXLKP NGFXLKN EXTGFXLKP EXTGFXLKN PILNLKP PILNLKN SLINKLKP SLINKLKN PIEMINILKP PIEMINILKN PIEMINILKP PIEMINILKN NGPPLKP NGPPLKN PIENEWLKP PIENEWLKN SSRLKP SSRLKN LK_VG_M_SS LK_VG_M_NSS Place within." of LKGEN RP _PR RP RP RP RP RP RP RP RP RP T T T T _PR _PR _PR _PR _PR _PR _PR _PR _PR R PULKP PULKN NGFX_LKP NGFX_LKN EXT_GFX_LKP EXT_GFX_LKN PIE_LN_LKP PIE_LN_LKN SLINK_LKP SLINK_LKN PIE_MINI_LKP PIE_MINI_LKN PIE_MINI_LKP PIE_MINI_LKN NGPP_LKP NGPP_LKN PIE_NEW_LKP PIE_NEW_LKN SSR_LKP SSR_LKN *_ PULKP () PULKN () NGFX_LKP () NGFX_LKN () EXT_GFX_LKP () EXT_GFX_LKN () PIE_LN_LKP () PIE_LN_LKN () SLINK_LKP () SLINK_LKN () PIE_MINI_LKP () PIE_MINI_LKN () PIE_MINI_LKP () PIE_MINI_LKN () NGPP_LKP () NGPP_LKN () PIE_NEW_LKP () PIE_NEW_LKN () SSR_LKP () SSR_LKN () (,,) PLK_SM (,,) PT_SM PLK_SM PT_SM SMLK SMT HTTT/M HTT/M NHTREFLKP NHTREFLKN R _ R _ NHT_REFLKP NHT_REFLKN NHT_REFLKP () NHT_REFLKN () () MINILK_REQ# () MINILK_REQ# () NEW-R_LK_REQ# LK_P# P# LKREQ# LKREQ# LKREQ# LKREQ# LKREQ# T T T T T T T T T T MHz_ REF/SEL_HTT REF/SEL_ST REF/SEL_ LKMUS SEL_HT SEL_ST SEL_ R _ LK_M_US *P/VG_ LK_M_US () R R Ra /F_./F_ Rb RX RS EXT_N_OS () SLGSPVTR.V.V RELTK L Ra.R R lock chip has internal serial terminations for differencial pairs, external resistors are reserved for debug purpose. +V_LKV R.K_ Rb R.R RES HIP /W +-%()L-F -->SF RES HIP /W +-%() -->SF RES HIP. /W +-%() -->SF RES HIP. /W +-%() -->SF +.V * default SEL_ST SEL_ LK_P# R.K_ SLGSPVTR RTMN- P/N : LSP P/N : L MHz.V single ended HTT clock SEL_HTT * MHz differential HTT clock * MHz non-spreading differential SR clock SEL_ST MHz spreading differential SR clock MHz and M SS outputs SEL_ * MHz SR clock R *.K_ R.K_ RSM/RXM N/R PROJET : J Quanta omputer Inc. Size ocument Number Rev ustom lock Gen ate: Thursday, ugust, Sheet of

3 () HT_N_PU H[..] () HT_N_PU L[..] () HT_N_PU_LK_H[..] () HT_N_PU_LK_L[..] () HT_N_PU_TL_H[..] () HT_N_PU_TL_L[..] () HT_PU_N H[..] () HT_PU_N L[..] () HT_PU_N_LK_H[..] () HT_PU_N_LK_L[..] () HT_PU_N_TL_H[..] () HT_PU_N_TL_L[..] HT_N_PU H[..] HT_N_PU L[..] HT_N_PU_LK_H[..] HT_N_PU_LK_L[..] HT_N_PU_TL_H[..] HT_N_PU_TL_L[..] HT_PU_N H[..] HT_PU_N L[..] HT_PU_N_LK_H[..] HT_PU_N_LK_L[..] HT_PU_N_TL_H[..] HT_PU_N_TL_L[..].U/.V_.U/.V_.U/.V_ P/V_ +.V +.V +.V +.V +.V +.V HT_N_PU H E HT_N_PU L E HT_N_PU H E HT_N_PU L F HT_N_PU H G HT_N_PU L G HT_N_PU H G HT_N_PU L H HT_N_PU H J HT_N_PU L K HT_N_PU H L HT_N_PU L L HT_N_PU H L HT_N_PU L M HT_N_PU H N HT_N_PU L N HT_N_PU H E HT_N_PU L F HT_N_PU H F HT_N_PU L F HT_N_PU H G HT_N_PU L H HT_N_PU H H HT_N_PU L H HT_N_PU H K HT_N_PU L K HT_N_PU H L HT_N_PU L M HT_N_PU H M HT_N_PU L M HT_N_PU H N HT_N_PU L P HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_TL_H HT_N_PU_TL_L HT_N_PU_TL_H HT_N_PU_TL_L W/S= mil/mil L +PUV LMPGSN(,M,)_ U/.V_ U VLT_ VLT_ VLT_ VLT_ L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L L_IN_H L_IN_L J L_LKIN_H J L_LKIN_L J L_LKIN_H K L_LKIN_L N L_TLIN_H P L_TLIN_L P L_TLIN_H P L_TLIN_L HT LINK SOKET PIN.U/.V_.U/.V_ VLT_ E VLT_ E VLT_ E VLT_ E L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H W L_OUT_L W L_OUT_H V L_OUT_L U L_OUT_H U L_OUT_L U L_OUT_H T L_OUT_L R L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H L_OUT_L L_OUT_H Y L_OUT_L W L_OUT_H V L_OUT_L V L_OUT_H V L_OUT_L U L_OUT_H T L_OUT_L T L_LKOUT_H Y L_LKOUT_L W L_LKOUT_H Y L_LKOUT_L Y L_TLOUT_H R L_TLOUT_L R L_TLOUT_H T L_TLOUT_L R +.V +.V +.V +.V P/V_.U/.V_.U/.V_ P/V_ HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_TL_H HT_PU_N_TL_L HT_PU_N_TL_H HT_PU_N_TL_L () () PUTEST PUTEST PUTEST PUTEST PUTEST PUTEST PUTEST PUTEST PUTEST PU LK PULKP PULKN PULKIN PULKP PULKN PULKP PULKN Keep trace from resisor to PU within." keep trace from caps to PU within." R R *_ R M recommends / R _ R *_ *_ R R R R *_ R *_ *_ * /F_ () () PULKIN# P/V/XR_ P/V/XR_ PU_RY PU_TMS PU_TK PU_TRST# PU_TI W/S= mil/mil +PUV +PUV PULKIN PULKIN# R./F_ PU_HTREF R R./F_ PU_HTREF P place them to PU within." PU_V_RUN_F_H F PU_V_RUN_F_L E () PU_V_RUN_F_H () PU_V_RUN_F_L +.V_SUS T T T +PUV R _ R *_ PUTEST PUTEST PUTEST PUTEST T PUTEST T PUTEST T +.V_SUS PUTEST T PUTEST T R _ PUTEST PU_THERM PU_THERM PU_LT_RST# PU_LT_STOP# PU_PWRG PU_LT_REQ#_PU U F V F V LKIN_H LKIN_L _ R _ R _ R _ R PU_LT_RST# () PU_LT_RST# PU_PWRG RESET_L () PU_PWRG PU_LT_STOP# PWROK (,) PU_LT_STOP# F PU_LT_REQ#_PU LTSTOP_L THERMTRIP_L LTREQ_L PROHOT_L Sideand Temp sense I PU_SI MEMHOT_L F PU_SI SI F PU_LERT SI E LERT_L THERM THERM HT_REF +.V HT_REF R _ PUTESTH E PUTESTL E V_F_H V_F_L Y V_F_H V_F_L G RY TMS TK TRST_L F TI TEST H TEST G TEST TEST_H TEST_L TEST F TEST E TEST E TEST TEST F TEST TEST TEST RSV RSV RSV RSV RSV KEY KEY SV SV VIO_F_H VIO_F_L VN_F_H VN_F_L REQ_L TO TEST_H TEST_L TEST TEST TEST TEST TEST TEST TEST TEST_H TEST_L RSV RSV RSV RSV RSV M W F W W W Y H G +.V H_THRM () H_THRM () PU_SV_R PU_SV_R PU_THERMTRIP_L# PU_PROHOT_L# PU_MEMHOT_L# PU_THERM PU_THERM VIO_F_H VIO_F_L E PU_REQ# E PU_TO J H E F K H H PUTESTH PUTESTL PUTEST PUTEST PUTEST PUTEST PUTESTH PUTESTL VIO_F_H () VIO_F_L () PU_VN_RUN_F_H () PU_VN_RUN_F_L () T T T T T T T T SOKET PIN +.V Q PU_LT_REQ#_PU +.V_SUS +.V_SUS R R K_ PU_MEMHOT_L# K_ R R _ R _.U/V/XR_.K_ *SS_NL/SOT NTR_VREF R _ PU_LT_RST# PU_LT_REQ# () Q MMT PU_MEMHOT# G *SHORT_ P for debug only PU_MEMHOT# (,) +.V R K_ PU_LT_RST_HTP# Q SS_NL/SOT +.V_SUS R R R R R R VFIX MOE *.K_ K_ K_ PU_SV_R R _ PU_SV_R R _ PU_PWRG R _ *_ *_ *_ HT onnector PU_SV PU_SV PU_PWRG_SVI_REG VI Override ircuit SV SV Voltage Output.V.V.V.V Serial VI PU_SV () PU_SV () PU_PWRG_SVI_REG () +.V_SUS R _ PU_SI M recommends / R R R _ K PU_SI +.V_SUS +.V_SUS R PU_PROHOT_L# K_ R _ Q MMT PU_PROHOT# () +.V_SUS +.V_SUS R PU_THERMTRIP_L# K_ R _ Q MMT PU_THERMTRIP# () PU_RY PU_REQ# PU_TK PU_TMS PU_TI PU_TRST# PU_TO PU_LT_RST_HTP# T T T T T T T T PU_LERT PU_REQ# PROJET : J Quanta omputer Inc. N/R Size ocument Number Rev ustom SG HT,TL I/F / ate: Monday, ugust, Sheet of

4 E +.VSMVTT U +.VSMVTT () MEM_M_T[..] PLE THEM LOSE TO +.V_SUS VTT MEM:M/TRL/LK VTT W U PU WITHIN " VTT VTT +.VSMVREF (,) VTT VTT m MEM:T MEM_M_T[..] () MEM_M_T MEM_M_T VTT VTT R R Reserved MEM_M_T M_T M_T G MEM_M_T R./F_ M_ZP VTT MEM_M_T M_T M_T F F *_ MEM_M_T +.V_SUS R./F_ M_ZN MEMZP PU_VTT_SENSE K/F_ MEM_M_T M_T M_T H E MEM_M_T MEMZN VTT_SENSE Y PU_VTT_SENSE () MEM_M_T M_T M_T G G MEM_M_T MEM_M_RESET# MEMVREF_PU MEM_M_T M_T M_T H MEM_M_T T H RSV_M MEMVREF W E MEM_M_T M_T M_T H MEM_M_T MEM_M_RESET# MEM_M_T M_T M_T MEM_M_T (,) MEM_M_OT T M_OT RSV_M T MEM_M_T M_T M_T E MEM_M_T (,) MEM_M_OT V M_OT MEM_M_T M_T M_T H U MEM_M_T M_OT M_OT W R MEM_M_OT (,) MEM_M_T M_T M_T E V MEM_M_T M_OT M_OT W K/F_ MEM_M_OT (,).U/V/XR_ P/V_ MEM_M_T M_T M_T E MEM_M_T M_OT Y MEM_M_T M_T M_T H MEM_M_T (,) MEM_M_S# T M_S_L MEM_M_T M_T M_T E MEM_M_T (,) MEM_M_S# U M_S_L M_S_L V MEM_M_S# (,) MEM_M_T M_T M_T F U MEM_M_T M_S_L M_S_L W MEM_M_S# (,) MEM_M_T M_T M_T V MEM_M_T M_S_L M_S_L U MEM_M_T M_T M_T G MEM_M_T MEM_M_T M_T M_T G MEM_M_T (,) MEM_M_KE J M_KE M_KE J MEM_M_KE (,) MEM_M_T M_T M_T MEM_M_T (,) MEM_M_KE J M_KE M_KE H MEM_M_KE (,) MEM_M_T M_T M_T MEM_M_T MEM_M_T M_T M_T E N MEM_M_T M_LK_H M_LK_H P MEM_M_T M_T M_T E N MEM_M_T M_LK_L M_LK_L R MEM_M_T M_T M_T F MEM_M_T () MEM_M_LK_P E M_LK_H M_LK_H MEM_M_LK_P () MEM_M_T M_T M_T MEM_M_T () MEM_M_LK_N F M_LK_L M_LK_L MEM_M_LK_N () MEM_M_T M_T M_T MEM_M_T () MEM_M_LK_P Y M_LK_H M_LK_H F MEM_M_LK_P () E MEM_M_T M_T M_T F MEM_M_T () MEM_M_LK_N M_LK_L M_LK_L F MEM_M_LK_N () E MEM_M_T M_T M_T F P MEM_M_T M_LK_H M_LK_H R G MEM_M_T M_T M_T H P MEM_M_T M_LK_L M_LK_L R G MEM_M_T M_T M_T J MEM_M_T (,) MEM_M_[..] MEM_M_[..] (,) MEM_M_ MEM_M_ MEM_M_T M_T M_T E N MEM_M_T MEM_M_ M_ M_ P MEM_M_ MEM_M_T M_T M_T E M MEM_M_T MEM_M_ M_ M_ N G N MEM_M_ MEM_M_T M_T M_T H MEM_M_T MEM_M_ M_ M_ P G M MEM_M_ MEM_M_T M_T M_T H MEM_M_T MEM_M_ M_ M_ N M MEM_M_ MEM_M_T M_T M_T Y MEM_M_T MEM_M_ M_ M_ N L MEM_M_ MEM_M_T M_T M_T MEM_M_T MEM_M_ M_ M_ L M MEM_M_ MEM_M_T M_T M_T MEM_M_T MEM_M_ M_ M_ N E L MEM_M_ MEM_M_T M_T M_T MEM_M_T MEM_M_ M_ M_ L L MEM_M_ MEM_M_T M_T M_T W MEM_M_T MEM_M_ M_ M_ M K MEM_M_ MEM_M_T M_T M_T W MEM_M_T MEM_M_ M_ M_ K R MEM_M_ MEM_M_T M_T M_T Y MEM_M_T MEM_M_ M_ M_ T E L MEM_M_ MEM_M_T M_T M_T MEM_M_T MEM_M_ M_ M_ L K MEM_M_ MEM_M_T M_T M_T Y MEM_M_T MEM_M_ M_ M_ L V MEM_M_ MEM_M_T M_T M_T MEM_M_T MEM_M_ M_ M_ W E K MEM_M_ MEM_M_T M_T M_T MEM_M_T MEM_M_ M_ M_ J F K MEM_M_ MEM_M_T M_T M_T MEM_M_T M_ M_ J F MEM_M_T M_T M_T F MEM_M_T MEM_M_T M_T M_T MEM_M_T (,) MEM_M_NK R M_NK M_NK R MEM_M_NK (,) MEM_M_T M_T M_T MEM_M_T (,) MEM_M_NK R M_NK M_NK U MEM_M_NK (,) MEM_M_T M_T M_T Y MEM_M_T (,) MEM_M_NK J M_NK M_NK J MEM_M_NK (,) MEM_M_T M_T M_T E MEM_M_T MEM_M_T M_T M_T W MEM_M_T (,) MEM_M_RS# R M_RS_L M_RS_L U MEM_M_RS# (,) MEM_M_T M_T M_T W MEM_M_T (,) MEM_M_S# T M_S_L M_S_L U MEM_M_S# (,) MEM_M_T M_T M_T Y MEM_M_T (,) MEM_M_WE# T M_WE_L M_WE_L U MEM_M_WE# (,) F MEM_M_T M_T M_T Y MEM_M_T MEM_M_T M_T M_T F MEM_M_T SOKET PIN MEM_M_T M_T M_T F MEM_M_T MEM_M_T M_T M_T F MEM_M_T MEM_M_T M_T M_T MEM_M_T MEM_M_T M_T M_T MEM_M_T MEM_M_T M_T M_T Y Y MEM_M_T MEM_M_T M_T M_T W E MEM_M_T MEM_M_T M_T M_T F MEM_M_T MEM_M_T M_T M_T F MEM_M_T MEM_M_T M_T M_T MEM_M_T M_T M_T () MEM_M_M[..] MEM_M_M[..] () MEM_M_M MEM_M_M +.VSMVTT Place close to socket MEM_M_M M_M M_M E MEM_M_M MEM_M_M M_M M_M MEM_M_M MEM_M_M M_M M_M E E MEM_M_M MEM_M_M M_M M_M F MEM_M_M MEM_M_M M_M M_M E MEM_M_M.U/.V_.U/.V_.U/.V_.U/.V_ MEM_M_M M_M M_M Y.U/.V_.U/.V_.U/.V_.U/.V_ MEM_M_M MEM_M_M M_M M_M MEM_M_M M_M M_M Y +.VSMVTT P/V_ P/V_ P/V_ lose to PU within mils P/V_ P/V_ P/V_ P/V_ P/V_ () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N Processor Memory Interface M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L F M_QS_H E M_QS_L M_QS_H M_QS_L F M_QS_H F M_QS_L E M_QS_H M_QS_L F M_QS_H E M_QS_L M_QS_H G M_QS_L H M_QS_H G M_QS_L G M_QS_H M_QS_L M_QS_H G M_QS_L G M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H Y M_QS_L W M_QS_H W M_QS_L W MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_LK_P MEM_M_LK_P SOKET PIN.P/V_.P/V_ MEM_M_LK_N MEM_M_LK_N MEM_M_LK_P MEM_M_LK_P.P/V_.P/V_ MEM_M_LK_N PROJET : J Quanta omputer Inc. MEM_M_LK_N Size ocument Number Rev ustom SG RII MEMORY I/F / N/R ate: Monday, ugust, Sheet of E

5 UF +VORE +PUVN +.V_SUS UE G V_ V_ H V_ V_ J V_ V_ J V_ V_ J V_ V_ J V_ V_ K V_ V_ K V_ V_ K V_ V_ K V_ V_ L V_ V_ L V_ V_ L V_ V_ L V_ V_ L V_ V_ L V_ V_ M V_ V_ M V_ V_ M V_ V_ M V_ V_ N V_ V_ N V_ V_ N V_ V_ V_ K VN_ V_ M VN_ V_ P VN_ T VN_ VIO V VN_ VIO VIO H VIO VIO J VIO VIO K VIO VIO K VIO VIO K VIO VIO K VIO VIO L VIO VIO M VIO VIO M VIO VIO M VIO VIO M VIO VIO N VIO VIO SOKET PIN +VORE P P R R R R T T T T T T U U U U U V V V V V W Y Y V V V V U T T T T R P P P P +.V_SUS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E VSS E VSS E VSS E VSS E VSS E VSS E VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS H VSS H VSS H VSS H VSS J VSS SOKET PIN VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J J J J J J J K K K K K K K L L L L L L L M M M N N N N N P P P P P R R R R T T T T T T U U U U U U U U V V V V V V V W Y Y N +VORE U/.V_ +VORE +PUVN +.V_SUS +.V_SUS U/.V_ U/.V_ OTTOM SIE EOUPLING U/.V_ U/.V_ U/.V_ U/.V_ +.V_SUS.U/.V_ U/.V_ U/.V_ U/.V_ U/.V_.U/V_ P/V_ EOUPLING ETWEEN PROESSOR N IMMs PLE LOSE TO PROESSOR S POSSILE.U/.V_.U/.V_ U/.V_.U/.V_ U/.V_.U/.V_.U/.V_.U/.V_.U/V_.U/V_.U/.V_ P/V_.U/V_ P/V_.U/.V_.U/.V_.U/.V_.U/.V_.U/V_ P/V_ P/V_ P/V_ P/V_ PROESSOR POWER N GROUN +.V +.V +.V +VORE (,) LK Q NW--F R /F_.U/V_.U/V_ (,) T NW--F Q +.V () PM_THERM# (,) SYS_SHN# R K_ R K_ R K_ R _ R K_ ddress: H U SLK V S XP LERT# XN OVERT#.U/V/XR_ H_THRM () P/V_ H_THRM () add.uf stitching caps at RS (near HT pin out) side for connecting PU_ORE and planes. (round cap with ~ HT pairs) +VORE +VORE NW--F Q +.V GPU.U/V_.U/V_.U/V_.U/V_ PROJET : J Quanta omputer Inc. For fix HyperTransport nets across plane splits N/R Size ocument Number Rev ustom SG PWR & / ate: Tuesday, ugust, Sheet of

6 MEM_M_ IM_S MEM_M_RESET# IM_S IM_S MEM_M_NK MEM_M_ MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_NK MEM_M_NK MEM_M_T MEM_M_N MEM_M_RESET# MEMHOT_SOIMM# PT_SM MEM_M_T PLK_SM MEMHOT_SOIMM#_ MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ IM_S IM_S IM_S IM_S +.VSMVREF_IMM IM_S MEM_M_N MEM_M_ MEM_M_ MEM_M_NK MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_NK MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_NK PT_SM PLK_SM MEM_M_T MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEMHOT_SOIMM#_ PT_SM (,,) PLK_SM (,,) MEM_M_T[..] () MEM_M_M[..] () MEM_M_M[..] () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_KE (,) MEM_M_KE (,) MEM_M_RS# (,) MEM_M_S# (,) MEM_M_WE# (,) MEM_M_S# (,) MEM_M_OT (,) MEM_M_OT (,) MEM_M_S# (,) MEM_M_NK[..] (,) MEM_M_[..] (,) MEMHOT_SOIMM# () MEM_M_QS_N () MEM_M_QS_N () MEM_M_KE (,) MEM_M_KE (,) MEM_M_QS_N () MEM_M_QS_N () MEM_M_RS# (,) MEM_M_S# (,) MEM_M_WE# (,) MEM_M_S# (,) MEM_M_OT (,) MEM_M_OT (,) MEM_M_QS_P () MEM_M_QS_P () MEM_M_S# (,) MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_LK_P () MEM_M_QS_N () MEM_M_LK_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_NK[..] (,) MEM_M_[..] (,) MEM_M_T[..] () +.VSMVREF (,) +.V_SUS +.V_SUS +.V +.VSMVREF_IMM +.VSMVREF_IMM +.V +.V_SUS +.V +.VSMVREF_IMM Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : J N/R R SOIMMS: / HNNEL ustom Monday, ugust, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : J N/R R SOIMMS: / HNNEL ustom Monday, ugust, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : J N/R R SOIMMS: / HNNEL ustom Monday, ugust, SMbus address SMbus address H= H= Only for reserved o.u/.v/xr_.u/.v/xr_.u/v/xr_.u/v/xr_ R K/F_ R K/F_ R _ R _ T T R K/F_ R K/F_ SO-IMM (REVERSE) N R SO-IMM SOKET.V SO-IMM (REVERSE) N R SO-IMM SOKET.V Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q N N N N N/TEST M M M M M M M M QS QS QS QS QS QS QS QS K K K K KE KE VREF RS S WE S S S S S SL Vspd V V V V V V V V V V V V VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS QS QS QS QS QS QS QS QS OT OT VSS VSS VSS VSS VSS VSS VSS VSS VSS R K/F_ R K/F_.U/V/XR_.U/V/XR_ R K/F_ R K/F_.U/.V/XR_.U/.V/XR_ T T T T R _ R _.U/V/XR_.U/V/XR_ T T P/V_ P/V_ P/V_ P/V_ R K/F_ R K/F_ SO-IMM (Normal) N R SO-IMM SOKET.V SO-IMM (Normal) N R SO-IMM SOKET.V Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q N N N N N/TEST M M M M M M M M QS QS QS QS QS QS QS QS K K K K KE KE VREF RS S WE S S S S S SL Vspd V V V V V V V V V V V V VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS QS QS QS QS QS QS QS QS OT OT VSS VSS VSS VSS VSS VSS VSS VSS VSS R K/F_ R K/F_ R *_ R *_.U/V/XR_.U/V/XR_

7 (,) MEM_M_[..] (,) MEM_M_NK[..] MEM_M_[..] MEM_M_NK[..] (,) MEM_M_[..] (,) MEM_M_NK[..] MEM_M_[..] MEM_M_NK[..] +.VSMVTT +.VSMVTT (,) MEM_M_KE (,) MEM_M_WE# (,) MEM_M_S# (,) MEM_M_OT (,) MEM_M_S# (,) MEM_M_KE (,) MEM_M_S# (,) MEM_M_RS# (,) MEM_M_OT MEM_M_KE RP MEM_M_NK MEM_M_ RP MEM_M_ MEM_M_ RP MEM_M_ MEM_M_ RP MEM_M_ MEM_M_ RP MEM_M_NK MEM_M_WE# RP MEM_M_S# MEM_M_OT RP MEM_M_S# MEM_M_ RP MEM_M_KE MEM_M_ RP MEM_M_ MEM_M_ RP MEM_M_ MEM_M_ RP MEM_M_ MEM_M_NK RP MEM_M_ MEM_M_S# MEM_M_RS# MEM_M_ MEM_M_OT RP RP _PR PR PR PR PR PR PR PR PR PR PR PR PR PR_.U/V/XR_ +.V_SUS.U/V/XR_.U/V/XR_ +.V_SUS.U/V/XR_.U/V/XR_ +.V_SUS.U/V/XR_.U/V/XR_ +.V_SUS.U/V/XR_.U/V/XR_ +.V_SUS.U/V/XR_.U/V/XR_ +.V_SUS.U/V/XR_.U/V/XR_ +.V_SUS.U/V/XR_.U/V/XR_ +.V_SUS.U/V/XR_ (,) MEM_M_KE (,) MEM_M_WE# (,) MEM_M_S# (,) MEM_M_OT (,) MEM_M_S# (,) MEM_M_KE (,) MEM_M_S# (,) MEM_M_RS# (,) MEM_M_OT MEM_M_KE MEM_M_NK MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_NK MEM_M_WE# MEM_M_S# MEM_M_OT MEM_M_S# MEM_M_KE MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_NK MEM_M_ MEM_M_S# MEM_M_RS# MEM_M_OT MEM_M_ RP RP RP RP RP RP RP RP RP RP RP RP RP RP _PR PR PR PR PR PR PR PR PR PR PR PR PR PR_.U/V/XR_ +.V_SUS.U/V/XR_.U/V/XR_ +.V_SUS.U/V/XR_.U/V/XR_ +.V_SUS.U/V/XR_.U/V/XR_ +.V_SUS.U/V/XR_.U/V/XR_ +.V_SUS.U/V/XR_.U/V/XR_ +.V_SUS.U/V/XR_.U/V/XR_ +.V_SUS.U/V/XR_.U/V/XR_ +.V_SUS.U/V/XR_ PLE LOSE TO PROESSOR WITHIN. INH PLE LOSE TO PROESSOR WITHIN. INH +.V_SUS +.V_SUS.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_ PLE LOSE TO SOKET( PER EMI/EM) PLE LOSE TO SOKET( PER EMI/EM) +.V +.V R *K/F_ lose R socket R *K/F_ PU_MEMHOT# (,) U +.V R *_ (,,) PT_SM (,,) PLK_SM +.V PT_SM PLK_SM +VS.U/V/XR_ MEMHOT_SOIMM# O.S Q S *NE-G SL ddress:h *SU+T&R Q *NE-G +.V R K/F_ MEMHOT_SOIMM# MEMHOT_SOIMM# () PROJET : J Quanta omputer Inc. N/R Size ocument Number Rev ustom R SOIMMS TERMINTIONS ate: Monday, ugust, Sheet of

8 R HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_TL_H HT_PU_N_TL_L HT_PU_N_TL_H HT_PU_N_TL_L R /F_ HT_RXLP HT_RXLN U Y HT_RXP HT_TXP Y HT_RXN PRT OF HT_TXN V HT_RXP HT_TXP E V HT_RXN HT_TXN E V HT_RXP HT_TXP F V HT_RXN HT_TXN F U HT_RXP HT_TXP F U HT_RXN HT_TXN F T HT_RXP HT_TXP H T HT_RXN HT_TXN H P HT_RXP HT_TXP J P HT_RXN HT_TXN J P HT_RXP HT_TXP K P HT_RXN HT_TXN K N HT_RXP HT_TXP K N HT_RXN HT_TXN K HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN Y HT_RXP Y HT_RXN W HT_RXP W HT_RXN V HT_RXP V HT_RXN U HT_RXP U HT_RXN U HT_RXP U HT_RXN T HT_RXLKP T HT_RXLKN HT_RXLKP HT_RXLKN M HT_RXTLP M HT_RXTLN R HT_RXTLP R HT_RXTLN HT_RXLP HT_RXLN RS(RX) HYPER TRNSPORT PU I/F HT_TXP F HT_TXN G HT_TXP G HT_TXN H HT_TXP J HT_TXN J HT_TXP J HT_TXN K HT_TXP L HT_TXN J HT_TXP M HT_TXN L HT_TXP M HT_TXN P HT_TXP P HT_TXN M HT_TXLKP H HT_TXLKN H HT_TXLKP L HT_TXLKN L HT_TXTLP M HT_TXTLN M HT_TXTLP P HT_TXTLN R HT_TXLP HT_TXLN HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_TL_H HT_N_PU_TL_L HT_N_PU_TL_H HT_N_PU_TL_L HT_TXLP HT_TXLN R R /F_ HT_PU_N H[..] HT_PU_N L[..] HT_PU_N_LK_H[..] HT_PU_N_LK_L[..] HT_PU_N_TL_H[..] HT_PU_N_TL_L[..] HT_N_PU H[..] HT_N_PU L[..] HT_N_PU_LK_H[..] HT_N_PU_LK_L[..] HT_N_PU_TL_H[..] HT_N_PU_TL_L[..] HT_TXLP HT_TXLN HT_RXLP HT_RXLN HT_PU_N H[..] () HT_PU_N L[..] () HT_PU_N_LK_H[..] () HT_PU_N_LK_L[..] () HT_PU_N_TL_H[..] () HT_PU_N_TL_L[..] () HT_N_PU H[..] () HT_N_PU L[..] () HT_N_PU_LK_H[..] () HT_N_PU_LK_L[..] () HT_N_PU_TL_H[..] () HT_N_PU_TL_L[..] () signals RS RX R ohm % R ohm % R.k ohm % R.k ohm % RES HIP.K /W +-%() P/N : SF RES HIP /W +-%() P/N : SF This block is for UM RS only, RX N U PR OF MEM_(N) MEM_Q/VO_VSYN(N) E MEM_(N) MEM_Q/VO_HSYN(N) V MEM_(N) MEM_Q/VO_E(N) E MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) E MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q(N) Y MEM_(N) MEM_Q/VO_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) E MEM_(N) MEM_(N) MEM_QSP/VO_IKP(N) MEM_QSN/VO_IKN(N) W MEM_RSb(N) MEM_QSP(N) Y MEM_Sb(N) MEM_QSN(N) MEM_WEb(N) MEM_Sb(N) MEM_M(N) MEM_KE(N) MEM_M/VO_(N) V MEM_OT(N) IOPLLV(N) V MEM_KP(N) IOPLLV(N) W MEM_KN(N) IOPLLVSS(N) E MEM_OMPP(N) MEM_OMPN(N) MEM_VREF(N) RS(RX) S_MEM/VO_I/F Y V Y E Y W E W E E E E +.V +.V PROJET : J Quanta omputer Inc. N/R Size ocument Number Rev ustom RSMN-HT LINK I/F / ate: Monday, ugust, Sheet of

9 () PIE_RXP_LN () PIE_RXN_LN () PIE_RXP () PIE_RXN () PIE_RXP () PIE_RXN () PIE_RXP () PIE_RXN T T T T () PIE_S_N_RXP () PIE_S_N_RXN () PIE_S_N_RXP () PIE_S_N_RXN () PIE_S_N_RXP () PIE_S_N_RXN () PIE_S_N_RXP () PIE_S_N_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN U GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN E GFX_RXP F GFX_RXN G GFX_RXP G GFX_RXN H GFX_RXP H GFX_RXN J GFX_RXP J GFX_RXN J GFX_RXP J GFX_RXN L GFX_RXP L GFX_RXN M GFX_RXP L GFX_RXN P GFX_RXP M GFX_RXN P GFX_RXP M GFX_RXN R GFX_RXP P GFX_RXN R GFX_RXP R GFX_RXN P GFX_RXP P GFX_RXN T GFX_RXP T GFX_RXN PIE_RXP_LN E PIE_RXN_LN GPP_RXP PIE_RXP GPP_RXN E PIE_RXN GPP_RXP PIE_RXP GPP_RXN PIE_RXN GPP_RXP PIE_RXP GPP_RXN V PIE_RXN GPP_RXP W PIE_RXP GPP_RXN U PIE_RXN GPP_RXP U PIE_RXP GPP_RXN U PIE_RXN GPP_RXP U GPP_RXN S_RXP Y S_RXN S_RXP Y S_RXN S_RXP S_RXN W S_RXP Y S_RXN GFX_TXP PRT OF GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP PIE I/F GPP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN PIE I/F GFX PIE I/F S S_TXP S_TXN S_TXP S_TXN S_TXP S_TXN S_TXP S_TXN PE_LRP(PE_LRP) PE_LRN(PE_LRN) RS(RX) to solve the HMI issue. / () PEG_RXN[:] () PEG_RXP[:] _PEG_TX R E@ PEG_TX_H E@.U/V/XR_ PEG_TXP _PEG_TX# R E@ PEG_TX#_H E@.U/V/XR_ PEG_TXN _PEG_TX R E@ PEG_TX_H E@.U/V/XR_ PEG_TXP _PEG_TX# R E@ PEG_TX#_H E@.U/V/XR_ PEG_TXN _PEG_TX R E@ PEG_TX_H E@.U/V/XR_ PEG_TXP _PEG_TX# R E@ PEG_TX#_H E@.U/V/XR_ PEG_TXN _PEG_TX R E@ PEG_TX_H E@.U/V/XR_ PEG_TXP _PEG_TX# R E@ PEG_TX#_H E@.U/V/XR_ PEG_TXN E _PEG_TX E@.U/V/XR_ PEG_TXP E _PEG_TX# E@.U/V/XR_ PEG_TXN F _PEG_TX E@.U/V/XR_ PEG_TXP F _PEG_TX# E@.U/V/XR_ PEG_TXN F _PEG_TX E@.U/V/XR_ PEG_TXP F _PEG_TX# E@.U/V/XR_ PEG_TXN H _PEG_TX E@.U/V/XR_ PEG_TXP H _PEG_TX# E@.U/V/XR_ PEG_TXN H _PEG_TX E@.U/V/XR_ PEG_TXP H _PEG_TX# E@.U/V/XR_ PEG_TXN J _PEG_TX E@.U/V/XR_ PEG_TXP J _PEG_TX# E@.U/V/XR_ PEG_TXN K _PEG_TX E@.U/V/XR_ PEG_TXP K _PEG_TX# E@.U/V/XR_ PEG_TXN K _PEG_TX E@.U/V/XR_ PEG_TXP K _PEG_TX# E@.U/V/XR_ PEG_TXN M _PEG_TX E@.U/V/XR_ PEG_TXP M _PEG_TX# E@.U/V/XR_ PEG_TXN M _PEG_TX E@.U/V/XR_ PEG_TXP M _PEG_TX# E@.U/V/XR_ PEG_TXN N _PEG_TX E@.U/V/XR_ PEG_TXP N _PEG_TX# E@.U/V/XR_ PEG_TXN P _PEG_TX E@.U/V/XR_ PEG_TXP P _PEG_TX# E@.U/V/XR_ PEG_TXN PIE_TXP_.U/V/XR_ PIE_TXP_LN () TO PIE-LN PIE_TXN_.U/V/XR_ PIE_TXN_LN () PIE_TXP_.U/V/XR_ PIE_TXP () PIE_TXN_.U/V/XR_ PIE_TXN () TO WLN PIE_TXP_.U/V/XR_ PIE_TXP () PIE_TXN_.U/V/XR_ PIE_TXN () TO EPRESS R PIE_TXP_.U/V/XR_ Y PIE_TXP () PIE_TXN_.U/V/XR_ PIE_TXN () PIE_TXP_ T PIE_TXN_ T PIE_TXP_ T PIE_TXN_ T TO PIE R REER _TXP_.U/V/XR_ PIE_N_S_TXP () _TXN_.U/V/XR_ PIE_N_S_TXN () _TXP_.U/V/XR_ PIE_N_S_TXP () _TXN_.U/V/XR_ PIE_N_S_TXN () _TXP_.U/V/XR_ PIE_N_S_TXP () _TXN_.U/V/XR_ PIE_N_S_TXN () _TXP_.U/V/XR_ PIE_N_S_TXP () _TXN_.U/V/XR_ PIE_N_S_TXN () N_PIELRP R.K/F_ N_PIELRN R K/F_ +.V PEG_RXN[:] PEG_RXP[:] _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# To HMI ONN PEG_TXN[:] PEG_TXP[:] lose to North ridge _PEG_TX () _PEG_TX# () _PEG_TX () _PEG_TX# () _PEG_TX () _PEG_TX# () _PEG_TX () _PEG_TX# () PEG_TXN[:] () PEG_TXP[:] () RS RX/RS/RS difference table (PIE LINK) RS isplay Port Support (muxed on GFX) N_PIELRP RX/RS.K () P GFX_TX,TX,TX and TX UX and HP GPP GPP GPP GPP P GFX_TX,TX,TX and TX UX and HP PROJET : J Quanta omputer Inc. N/R Size ocument Number Rev ustom RSMN-PIE I/F / ate: Thursday, ugust, Sheet of

10 () N_PLTRST# RS R _ North ridge RESET ES recommend N_RST#_IN *P/V/XR_ N_PWRG_IN *P/V/XR_ ES recommend (,) PX_LVS_SWITH () () () INT_RT_RE INT_RT_GRN INT_RT_LU R *_ R _ R /F_ R _ R /F_ R _ R /F_ +V_V_N +.V_VI_N +.V_VQ_N RT_R_ RT_G_ RT U F V(N) E V(N) F VI(N) G VSSI(N) H VQ(N) H VSSQ(N) E _Pr(FT_GPIO) F Y(FT_GPIO) F OMP_Pb(FT_GPIO) G RE(FT_GPIO) G REb(N) E GREEN(FT_GPIO) F GREENb(N) E LUE(FT_GPIO) F LUEb(N) TXOUT_LP(N) PRT OF TXOUT_LN(N) TXOUT_LP(N) TXOUT_LN(N) TXOUT_LP(N) TXOUT_LN(G_GPIO) TXOUT_LP(N) TXOUT_LN(G_GPIO) RT/TVOUT TXOUT_UP(N) TXOUT_UN(N) TXOUT_UP(PIE_RESET_GPIO) TXOUT_UN(PIE_RESET_GPIO) TXOUT_UP(N) TXOUT_UN(N) TXOUT_UP(PIE_RESET_GPIO) TXOUT_UN(N) L_TP L_TN L_TP L_TN L_TP L_TN L_TP L_TN L_TP L_TN L_TP L_TN L_TP L_TN L_TP L_TN T T T T L_TP () L_TN () L_TP () L_TN () L_TP () L_TN () L_TP () L_TN () L_TP () L_TN () L_TP () L_TN () () () () INT_HSYN () INT_VSYN INT_RT_T INT_RT_LK R _ R _ R _ R _ HSYN_INT VSYN_INT T_INT LK_INT E F _HSYN(PWM_GPIO) _VSYN(PWM_GPIO) _S(PE_TLRN) _SL(PE_RLRN) TXLK_LP(G_GPIO) TXLK_LN(G_GPIO) TXLK_UP(PIE_RESET_GPIO) TXLK_UN(PIE_RESET_GPIO) L_LK L_LK# L_LK L_LK# L_LK () L_LK# () L_LK () L_LK# () HTV_ET R E@.K_ +.V E@HH-PT R Q *NE *E@HH-PT E@_ +.V EL, for M recommend. / R *K_ R *I@K_ (,) PX_LVS_SWITH (,) PX_EN () () () () N_PWRG_IN NHT_REFLKP NHT_REFLKN () () () () () () EXT_N_OS +.V NGFX_LKP NGFX_LKN NGPP_LKP NGPP_LKN SLINK_LKP SLINK_LKN R R.K_ R /F_.K_ R _ R RSET_N +.V_PLLV +.V_PLLV +.V_VHTPLL +.V_VPIEPLL N_RST#_IN N_PWRG_IN N_LT_STOP# N_LLOW_LTSTOP NHT_REFLKP NHT_REFLKN NGFX_LKP NGFX_LKN NGPP_LKP NGPP_LKN SLINK_LKP SLINK_LKN N_REFLK_P N_REFLK_N G H E E F T T U U V V _RSET(PWM_GPIO) PLLV(N) PLLV(N) PLLVSS(N) VHTPLL VPIEPLL VPIEPLL SYSRESETb POWERGOO LTSTOPb LLOW_LTSTOP HT_REFLKP HT_REFLKN REFLK_P/OSIN(OSIN) REFLK_N(PWM_GPIO) GFX_REFLKP GFX_REFLKN I/O GPP_REFLKP GPP_REFLKN I/O GPPS_REFLKP(S_REFLKP) GPPS_REFLKN(S_REFLKN) LOKs PM PLL PWR LVTM VLTP(N) VSSLTP(N) VLT_(N) VLT_(N) VLT_(N) VLT_(N) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) LVS_IGON(PE_TLRP) LVS_LON(PE_RLRP) LVS_EN_L(PWM_GPIO) E E F G +.V_VLTP_N +.V_VLT N R _ R _ R *_ R/R/R ISP_ON_N LVS_LON_N PST_PWM UM V Hybrid V ISP_ON_N () LVS_LON_N () PST_PWM () +.V R R R *.K_.K_.K_ HTV_ET N_I_T N_I_LK () () () () INT_LVS_PNT INT_LVS_PNLLK HMI LK HMI T R _ R _ R _ R _ () YN_PWR_EN T T R _ N_I_T N_I_LK HTV_ET STRP_T I_T I_LK _T/UXN(N) _LK/UXP(N) UXP(N) UXN(N) STRP_T MIS. TMS_HP(N) HP(N) TVLKIN(PWM_GPIO) THERMLIOE_P THERMLIOE_N E TMS_HP TMS_HP SUS_STT#_N R_N_THRM R_N_THRM R _ T R _ T T TMS_HP (,) SUS_STT# () G RSV TESTMOE TEST_EN T RS_UX_L UX_L(N) RS(RX) R.K/F_ Enables ebug us acess through memory T/O pads and GPIO. : Enable RS, efault : isable RS (RS use VSYN#) Indicates if memory Side port is available or not : available RS, efault : Not available RS ( RS use HSYN#) INT_VSYN INT_HSYN R R R RS K_ RS K_ *K_ +.V +.V +.V L LMPGSN(,.)_ +.V RX -->N / RS --- V- nalog not applicable to RX L LMPGSN(,.)_ U/.V_ PLLV - Graphics PLL not applicable to RX +V_V_N U/.V/XR_ +.V_PLLV U/.V/XR_ +.V +.V change value form.u to u (HM). / LMPGSN(,.)_ L R +.V_PLLV +.V_VI_N LMPGSN(,.)_ +.V_VQ_N L PLLV - Graphics PLL not applicable to RX U/.V/XR_ U/.V/XR_ U/.V/XR_ VI- igital not applicable to RX VQ- andgap Reference not applicable to RX +.V L L LMPGSN(,.)_.U/.V/XR_ LMPGSN(,M,)_.U/.V_ +.V_VLTP_N VLTP - LVS or VI/HMI PLL not applicable to RX +.V_VLT N VLT - LVS or VI/HMI digital not applicable to.u/v/xr_ RX For extrnal EEPROM ebug only STRP_T RS/RX R K/F_ +VG_N +.V VPIEPLL -PIE PLL mils width L +.V_VPIEPLL LMPGSN(,.)_ +VG_N R *.K_ +.V RS R +VG_N R *K/F_.U/.V/XR_ (,) PU_LT_STOP# R _ N_LT_STOP# VHTPLL -HT LINK PLL mils width L +.V_VHTPLL LMPGSN(,.)_ RS : remove level shifter +VG_N R *.K_.U/.V/XR_ () PU_LT_REQ# () LLOW_LTSTOP R _ R _ N_LLOW_LTSTOP PROJET : J Quanta omputer Inc. N/R Size ocument Number Rev ustom RSMN-SYSTEM I/F / Thursday, ugust, ate: Sheet of

11 E G G G H J R L L L L M N P R R R V U V V W W W W W Y E E E G E E J J K M L RX/RS POWER IFFERENE TLE UF VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PIN NME VHT VHTRX RX +.V +.V RS +.V +.V PIN NME IOPLLV V RX N N RS +.V +.V PRT / GROUN VHTTX VPIE VG +.V +.V +.V +.V +.V +.V VI VQ PLLV N N N +.V +.V +.V VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS V_MEM VPIE V N +.V PLLV N +.V +.V VPIEPLL +.V +.V +.V VHTPLL +.V +.V +.V +.V E G G G H J L L L L M N P R R R R H U V W W W Y L M N P P R R T U U U V W W Y E K V_MEM VG N N +.V/.V +.V VLTP VLT N N +.V +.V IOPLLV N +.V VLT N N +.V VHT - HT LINK digital I/O for RX/RS VHTRX - HT LINK RX I/O for RX/RS +.V -Test Modify +.V for RSM. LMPGSN(,M,)_ L V - RS I/O transform. LMPGSN(,M,)_ L +.V for RSM+S. L LMPGSN(,M,)_ VHTTX - HT LINK TX I/O for RX/RS.U/.V_ +.V for RSM+S m +.V L LMPGSN(,M,)_ VPIE - PIE TX stage.u/.v_.u/.v_ I/O for RX/RS +.V +.V U/.V_ESR_ U/.V_ESR_ V_MEM For UM RS only Not applicable to RX memory I/O transform.u/v/xr_.u/v/xr_ R R.. +.V_VHT.U/V/XR_.U/V/XR_.U/V/XR_ +.V_VHTRX.U/V/XR_.U/V/XR_.U/V/XR_ +.V_VHTTX.U/V/XR_.U/V/XR_ +.V_VPIE.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_ U/V_ *U/V_ +.V_VG_N +.V_V_MEM UE RS(RX) do not install when Side-port not using. J VHT_ VPIE_ K VHT_ PRT / VPIE_ L VHT_ VPIE_ M VHT_ VPIE_ P VHT_ VPIE_ R VHT_ VPIE_ T VHT_ VPIE_ VPIE_ H VHTRX_ VPIE_ G VHTRX_ VPIE_ F VHTRX_ VPIE_ E VHTRX_ VPIE_ VHTRX_ VPIE_ VHTRX_ VPIE_ VHTRX_ VPIE_ VPIE_ E VHTTX_ VPIE_ VHTTX_ VHTTX_ V_ VHTTX_ V_ VHTTX_ V_ Y VHTTX_ V_ W VHTTX_ V_ V VHTTX_ V_ U VHTTX_ V_ T VHTTX_ V_ R VHTTX_ V_ P VHTTX_ V_ M VHTTX_ V_ V_ J VPIE_ V_ P VPIE_ V_ K VPIE_ V_ M VPIE_ V_ L VPIE_ V_ W VPIE_ V_ H VPIE_ V_ T VPIE_ V_ R VPIE_ V_ Y VPIE_ V_ VPIE_ VPIE_ V_MEM(N) VPIE_ V_MEM(N) E VPIE_ V_MEM(N) U VPIE_ V_MEM(N) V_MEM(N) F VG_(V_) V_MEM(N) G VG_(V_) E V_MEM(N) VG_(N) V_MEM(N) VG_(N) POWER E F G H J K M L P R T V U K J U J K M L L M M N N P P P R R T T U T J E Y H H +.V_V_PIE.U/V/XR_.U/V/XR_ U/V_. RS.V(.) +V_VG R +.V V -.V I/O.U/V/XR_.U/V/XR_ Not applicable to RX.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_ U/V_.U/V/XR_ VPIE - PIE-E Main power R _.U/.V_ +.V V - ore Logic power +.V_YN V_MEM For UM RS only Not applicable to RX memory I/O transform PROJET : J Quanta omputer Inc. N/R Size ocument Number Rev ustom RSMN-POWER / ate: Thursday, ugust, Sheet of

12 PI_LK PLE THESE PIE OUPLING PS LOSE TO U R *M_ Y.KHZ R M_ P/V_ PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN +.V L LMPGSN(,.)_ +.V_PIE_PV m PIE_PV-- PIE PLL POWER.U/.V/XR_ U/V_ PU_PWRG *P/V/XR_ To RS RT_X RT_X P/V_ () N_PLTRST# () PIE_RST# () LN_PLTRST# () EPRESS_PLTRST# () MINI_PLTRST# () PIE_S_N_RXP () PIE_S_N_RXN () PIE_S_N_RXP () PIE_S_N_RXN () PIE_S_N_RXP () PIE_S_N_RXN () PIE_S_N_RXP () PIE_S_N_RXN +.V +.V () LLOW_LTSTOP () PU_PROHOT# () PU_PWRG (,) PU_LT_STOP# () PU_LT_RST# ES recommend () PIE_N_S_TXP () PIE_N_S_TXN () PIE_N_S_TXP () PIE_N_S_TXN () PIE_N_S_TXP () PIE_N_S_TXN () PIE_N_S_TXP () PIE_N_S_TXN R +.V_PIE_VR R () SSR_LKP () SSR_LKN T T T T T T T T T T T T T T T T T R R *_ R _ R _ R _ R _ R RST#_S.U/V/XR RXP_.U/V/XR RXN_.U/V/XR RXP_.U/V/XR RXN_.U/V/XR RXP_.U/V/XR RXN_.U/V/XR RXP_.U/V/XR RXN_ K/F_ /F_.K/F_ SSR_LKP SSR_LKN N_ISP_LKP N_ISP_LKN N_HT_LKP N_HT_LKN PU_HT_LKP PU_HT_LKN SLT_GFX_LKP SLT_GFX_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN T T RT_X RT_X LLOW_LTSTOP PU_PROHOT# PU_PWRG PU_LT_STOP# PU_LT_RST# N U _RST# V PIE_TXP V PIE_TXN V PIE_TXP V PIE_TXN U PIE_TXP U PIE_TXN T PIE_TXP T PIE_TXN U PIE_RXP U PIE_RXN U PIE_RXP V PIE_RXN R PIE_RXP R PIE_RXN R PIE_RXP R PIE_RXN PIE_LRP_S T PIE_LRN_S PIE_LRP T PIE_LRN P P PIE_PV RT XTL PU S Part of PI EXPRESS INTERFE N PIE_RLKP/N_LNK_LKP N PIE_RLKN/N_LNK_LKN P PU_HT_LKP M PU_HT_LKN M SLT_GFX_LKP M SLT_GFX_LKN J GPP_LKP J GPP_LKN L GPP_LKP L GPP_LKN M GPP_LKP M GPP_LKN PIE_PVSS K N_ISP_LKP K N_ISP_LKN M N_HT_LKP M N_HT_LKN MHZ N GPP_LKP P GPP_LKN L J J M_M_M_OS M_X M_X X X F LLOW_LTSTP F PROHOT# F LT_PG G LT_STP# G LT_RST# LP RT LOK GENERTOR PI LKS PI INTERFE PILK PILK PILK PILK PILK PILK/GPIO RTLK INTRUER_LERT# VT S I TRL(P) S (SELFG) P/N : JLT PIRST# E# E# E# E# FRME# EVSEL# IRY# TRY# PR STOP# PERR# SERR# REQ# REQ# REQ# REQ#/GPIO REQ#/GPIO GNT# GNT# GNT# GNT#/GPIO GNT#/GPIO LKRUN# LOK# INTE#/GPIO INTF#/GPIO INTG#/GPIO INTH#/GPIO LPLK LPLK L L L L LFRME# LRQ# LRQ#/GNT#/GPIO MREQ#/REQ#/GPIO SERIRQ P P P P T T N U P V T V U V V T W T R R R U U Y W V Y Y Y Y W U Y W Y U W W V E E E V E E G E H H J J H H V PI_LK_R PI_LK_R PI_LK_R PI_LK_R PIRST#_L REQ# GNT# PE_GPIO INTE# INTF# INTG# LP_LK LP_LK LP_L LP_L LP_L LP_L LP_LFRME# LRQ# LRQ#_S S_GPIO SERIRQ RT_LK INTRUER_LERT# +VT R _ R _ R _ R _ R _ PIRST# () () () () () () () () () () () () () () () () () () () () () () () (,) (,) (,) (,) (,) (,) (,) (,) () E# () E# () E# () E# () FRME# () EVSEL# () IRY# () TRY# () PR () STOP# () REQ# () T T GNT# () T T MIL T T INTE# () T R _ R _ T T LP_L (,) LP_L (,) LP_L (,) LP_L (,) LP_LFRME# (,) LRQ# () SERIRQ (,) RT_LK () mil G *SHORT_ P +VT PI_LK_TPM () PI_LK (,) PI_LK () PI_LK () PIRST# () U/V_ PE_GPIO () FPK# () LKRUN# (,,) PX_EN () PE_GPIO () LP_LK () LP_LK () PLK_LP_EUG () LP_LK_ () +VT.U/V/XR_ PE_GPIO S_GPIO follow M reference schematic R U/V_ R R R Maybe can remove /F_+VRT PLK_LP_EUG LP_LK_ *P/VG_.K_ *.K_ +.V ll the PI bus has build-in Pull-UP/own resistors K/F_ HH-PT HH-PT N +VRT_ MIL RT_ON. *P/VG_ +T +.V_LW mil R _ *P/VG_ PROJET : J Quanta omputer Inc. N/R Size ocument Number Rev ustom S-PIE/PI/PU/LP / ate: Monday, ugust, Sheet of

13 +.V_SUS R N only,an't be install *.K_ S_TEST U +.V_SUS +.V +.V_S Z_SOUT Z_SYN Z_LK Z_RST# Z_SIN_R Z_SIN_R Z_SOUT S_TEST S_TEST *K/F_ SWI# PLK_SM PT_SM S_SMLK S_SMT +.V_SSL/ST is V/S tolerance M datasheet define it +.V R R R SL/ST is V tolerance M datasheet define it R R SL/ST is V/S tolerance M datasheet define it R R R R R R R R R R R R *.K_ *.K_.K_.K_.K_.K_.K_.K_ K_ *.K_ *K_ *K_ *K_ K_ K_ S_SLK S_ST NSWON# GPIO SUS_STT# GPIO GPIO GPIO GPIO GPIO SYS_RST# To zalia H for MXM R _ R E@_ R _ R R _ R G *SHORT_ P E@_ E@_ R _ R K_ E@_ R _ R _ To Modem oard R _ lock gen/robson /R/R thermal/ccelerometer (,) PU_MEMHOT# () PM_THERM# Z_SOUT_UIO () Z_SOUT_MXM () Z_SYN_UIO () Z_SYN_MXM () IT_LK_UIO () Z_ITLK_MXM () Z_RST#_UIO () Z_RESET#_MXM () Z_SIN () Z_SIN () MXM Z_SOUT_UIO_M () () PI_PME# T T () SUS# () SUS# () NSWON# () S_PWRG_IN () SUS_STT# () () () () () GTE RIN# SI# KSMI# T (,,) PIE_WKE# () SWI# () PU_THERMTRIP# () W_PWRG RSMRST# () Z_SPKR (,,) PLK_SM (,,) PT_SM () S_SMLK () S_SMT () PE_RESET_MXM# Not connected (internal pull-down). remove external pull up resistor. +.V () NEWR_ETET T () US_O# () US_O# () +.V T T T HH-PT R R T T Z_RST# () MXM_PRESENT# T R R _ R _ R _ R _ PI_PME# RI# SLP_S SUS#_R SUS#_R Z_LK Z_SOUT Z_SIN_R Z_SIN_R Z_SIN_R Z_SYN Z_RST# S_PWRG_IN SUS_STT# S_TEST S_TEST S_TEST GTE RIN# SI# KSMI# RSMRST#_R GPIO GPIO GPIO GPIO GPIO GPIO PLK_SM PT_SM S_SMLK S_SMT PM_TLOW# SES_INT GEVENT# PU_MEMHOT#_IN *_ *K/F_ SMLERT#_ S_JTG_TO S_JTG_TK S_JTG_TI S_JTG_RST# SYS_RST# PIE_WKE# SWI#_R PU_THERMTRIP# W_PWRG H audio interface is.v voltage GPIO pin for MXM K_ T MXM_RUNPWROK H_UX_RST# MXM_PWR_EN E E H F G H H K H H H Y W K K F J H F J W E W V W W W K K Y Y G E F E M M J J L M L M L H H H F E E H UIO US O INTEGRTE u S Part of PI_PME#/GEVENT# RI#/EXTEVNT# USLK/M_M_M_OS SLP_S/GPM# SLP_S# US_ROMP G SLP_S# PWR_TN# PWR_GOO SUS_STT# TEST US_FSP E TEST US_FSN E TEST GIN/GEVENT# US_FSP F KRST#/GEVENT# US_FSN E LP_PME#/GEVENT# LP_SMI#/EXTEVNT# US_HSP H S_STTE/GEVENT# US_HSN J SYS_RESET#/GPM# WKE#/GEVENT# US_HSP E LINK/GPM# US_HSN F SMLERT#/THRMTRIP#/GEVENT# N_PWRG US_HSP US_HSN RSMRST# US_HSP US_HSN PI / WKE UP EVENTS ST_IS#/GPIO US_HSP G LK_REQ#/ST_IS#/GPIO US_HSN H SMRTVOLT/ST_IS#/GPIO LK_REQ#/ST_IS#/GPIO US_HSP E LK_REQ#/ST_IS#/FNOUT/GPIO US_HSN E LK_REQ#/ST_IS#/FNIN/GPIO SPKR/GPIO US_HSP SL/GPO# US_HSN S/GPO# SL/GPO# US_HSP S/GPO# US_HSN _SL/GPIO _S/GPIO US_HSP G LL#/GPIO US_HSN G SHUTOWN#/GPIO R_RST#/GEVENT# US_HSP H US_HSN H US_HSP US_HSN US_HSP US_O#/IR_TX/GEVENT# US_HSN US_O#/IR_TX/GPM# US_O#/IR_RX/GPM# IM_GPIO US_O#/IR_RX/GPM# IM_GPIO US_O#/GPM# IM_PWM/IM_GPIO F US_O#/GPM# SL/IM_GPIO US_O#/GPM# S/IM_GPIO F SL_LV/IM_GPIO E Z_ITLK S_LV/IM_GPIO E Z_SOUT IM_PWM/IM_GPIO E Z_SIN/GPIO IM_PWM/IM_GPO Z_SIN/GPIO IM_PWM/IM_GPO E Z_SIN/GPIO Z_SIN/GPIO IM_GPIO G Z_SYN IM_GPIO G Z_RST# IM_GPIO Z_OK_RST#/GPM# IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO SPI_S#/IM_GPIO IE_RST#/F_RST#/IM_GPO IM_GPIO IM_GPIO IM_GPIO IM_GPIO INTEGRTE u US MIS GPIO US. US. IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO LK_M_US_L US_ROMP_S US_FSP US_FSN US_FSP US_FSN S_SLK S_ST S_GPIO S_GPIO USP+ () USP- () US onnector T T T T USP+ () USP- () USP+ () USP- () T T R USP+ () USP- () USP+ () USP- () USP+ () USP- () USP+ () USP- () USP+ () USP- () USP+ () USP- () S JTG T T Min-ard US onnector US onnector WLN Min-ard NEW R LUETOOTH S_SLK () S_ST () S_GPIO () S_GPIO () N.K/F T T arama US US onnector +.V_SUS EMI recommend SPI/LP define S_JTG_TK S_JTG_TO S_JTG_TI S_TEST S_JTG_RST# R *_ *.U/V_ LK_M_US () *P/VG_ S *S/W JTG EUG Z_SYN R _ Z_SYN_UIO_M () *P/VG_ Z_LK R _ IT_LK_UIO_M () Z_RST# R _ *P/VG_ Z_RST#_UIO_M () PROJET : J Quanta omputer Inc. Z_SIN_R R _ Z_SIN () N/R Size ocument Number Rev ustom S-PI/GPIO/US / ate: Monday, ugust, Sheet of

14 ST PORT,,, can support HI mode ST ST O () ST_TXP () ST_TXN () ST_RXN () ST_RXP ST PORT, are only support IE mode () ST_TXP () ST_TXN () ST_RXN () ST_RXP PLE ST_L RES VERY LOSE TO LL OF S NOTE: R IS K % FOR MHz XTL,.K % FOR MHz INTERNL LOK P/V/NPO_ P/V/NPO_ Y MHZ R R M_ ST_X ST_X PLE ST OUPLING PS LOSE TO S T T T T T T K/F_ PLV_ST-- ST PLL POWER T T +.V.U/V_.U/V_.U/V_.U/V_ ST_TXP_ ST_TXN_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_TXP_ ST_TXN_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_RIS_PN S_ST_LE# +V_XTLV_ST ST_X ST_X +.V R K/F_ +.V_PLLV_ST XTLV_ST-- ST crystal power U ST_TXP E ST_TXN ST_RXN ST_RXP E ST_TXP ST_TXN ST_RXN E ST_RXP ST_TXP ST_TXN E ST_RXN ST_RXP ST_TXP E ST_TXN ST_RXN ST_RXP E ST_TXP ST_TXN ST_RXN E ST_RXP ST_TXP ST_TXN E ST_RXN ST_RXP V ST_L Y ST_X ST_X W ST_T#/GPIO PLLV_ST W XTLV_ST S S IE_IORY Part of IE_IRQ IE_ IE_ IE_ IE_K# IE_RQ IE_IOR# IE_IOW# IE_S# IE_S# IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO ST PWR SERIL T HW MONITOR SPI ROM T // SPI_I/GPIO SPI_O/GPIO SPI_LK/GPIO SPI_HOL#/GPIO SPI_S#/GPIO LN_RST#/GPIO ROM_RST#/GPIO FNOUT/GPIO FNOUT/GPIO FNOUT/GPIO FNIN/GPIO FNIN/GPIO FNIN/GPIO TEMP_OMM TEMPIN/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO VIN/GPIO VIN/GPIO VIN/GPIO VIN/GPIO VIN/GPIO VIN/GPIO VIN/GPIO VIN/GPIO V VSS Y Y Y Y E E E E E G F F U J M M M P P R F G ROM_RST# S_FNOUT S_FNOUT S_FNTH S_FNTH PORT PWR_WN TEMP_OMM TEMPIN TEMPIN M_THRM_S m T T T T IF THERE IS NO IE, TEST T POINTS FOR EUG US T T IS MNTORY T T T T R _ WLN_RF_OFF# T T T T T T T T T T OR_I OR_I OR_I OR_I OR_I +V_V_HWM *.U/V_ T T T T T R _ T T T T T T T T T T L *.U/.V_ +.V WLN_RF_OFF# (,) T_ON# (,) R R R R R +.V V--H/W monitor nalog power E@K/F_ *K/F_ *K/F_ *K/F_ K/F_ I I I I I OR_I OR_I OR_I OR_I OR_I Modify // UM R R R R R *I@K/F_ K/F_ K/F_ K/F_ *K/F_ MXM change the board I. / () ST_LE#.U/V/XR_ S_ST_LE# +.V m) +.V_PLLV_ST L LMPGSN(,.)_ U/V_ m.u/v/xr_ U TSHFU +.V m +V_XTLV_ST L LMPGSN(,.)_ U/V_ Place near ball PROJET : J Quanta omputer Inc. N/R Size ocument Number Rev ustom S-PI/GPIO/US / ate: Thursday, ugust, Sheet of

15 +.V_S_R +.V +.V U/.V_.U/V/XR_ +.V_S_R R _ U VQ--.V I/O power. L VQ_ M VQ_ T VQ_ U VQ_ U U/.V_ U/V_ U/V_ U/V_ U/V_ U/V_ U/V_.U/V/XR_.U/V/XR_ VQ_ U.U/V/XR_ U/.V_ VQ_ V VQ_ W VQ_ Y VQ_.V : FLSH MEMORY MOE(EFULT) VQ_.V: IE MOE VQ_ VQ_ +V_.U/V/XR_ LMPGSN(,.)_ L +.V L LMPGSN(,.)_ For support US wakeup-->v_s.u/.v_ U/.V_ +.V_S L LMPGSN(,.)_ +.V R _ V_--.V IE I/O power.v flash memory I/O power PIE_VR--PIE I/O power U/V_ U/V_ V_ST--ST phy power VTX--US Phy nalog I/O power U/.V_ +.V_PIE_VR m +.V_V_ST. +V_V_US. U/.V_.U/V/XR_.U/V/XR_ U/V_ U/V_.U/.V/XR_ U/.V_.U/V/XR_.U/V/XR_..U/V/XR_.U/V/XR_ PLE LL THE EOUPLING PS ON THIS SHEET LOSE TO S S POSSILE. Y V V V E V VTX_ VTX_ VTX_ VTX_ VTX_ E VTX_ F VRX_ F VRX_ F VRX_ G VRX_ G VRX_ G VRX_ S Part of PI/GPIO I/O P PIE_VR_ P PIE_VR_ P PIE_VR_ P PIE_VR_ R PIE_VR_ R PIE_VR_ R PIE_VR_ V_ST_ V_ST_ V_ST_ V_ST_ V_ST_ V_ST_ E V_ST_ IE/FLSH I/O -LINK I/O ST I/O PLL LKGEN I/O ORE S.V_S I/O ORE S POWER US I/O V_ L V_ M V_ M V_ N V_ P V_ P V_ R V_ R V_ T KV_.V_ L KV_.V_ L KV_.V_ L KV_.V_ L S_.V_ S_.V_ S_.V_ S_.V_ J S_.V_ J S_.V_ L S_.V_ L S_.V_ G S_.V_ G US_PHY_.V_ US_PHY_.V_ V_VREF VK_.V VK_.V V E J K E V-- S/ ORE power +.V_V_S_R m R R _ For S issue(/) - chip bug use - chip can remove +.V_S +.V UE S VSS_ U/V_ U/V_ U/V_ U/V_ VSS_ U/.V_.U/V/XR_.U/V/XR_ VSS_ VSS_ T VSS_ST_ VSS_ U VSS_ST_ VSS_ U VSS_ST_ VSS_ U VSS_ST_ VSS_ KV_.V-- Internal V VSS_ST_ VSS_ +.V_KV clock Generator I/O V VSS_ST_ VSS_ power W VSS_ST_ VSS_ Y VSS_ST_ VSS_ m Y L VSS_ST_ VSS_ +.V Y VSS_ST_ VSS_ Y LMPGSN(,.)_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ U/.V_.U/V_.U/V_ U/V_.U/.V/XR_ VSS_ST_ VSS_.U/.V/XR_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ E VSS_ST_ VSS_ VSS_ VSS_ VSS_ S_.--.v standby power +VLW_R VSS_ VSS_. R VSS_US_ VSS_US_ VSS_ +.V_S VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_.U/.V/XR_.U/.V/XR_ VSS_US_ VSS_.U/V/XR_.U/V/XR_ U/.V_ VSS_US_ VSS_ VSS_US_ VSS_ E VSS_US_ VSS_ F VSS_US_ VSS_ S_.V--.V standby power F +.VLW_R VSS_US_ VSS_ G VSS_US_ VSS_. H R VSS_US_ VSS_ +.V_S H VSS_US_ VSS_ J VSS_US_ VSS_ J VSS_US_ VSS_ J VSS_US_ VSS_. U/V_ U/V_ J VSS_US_ VSS_ J VSS_US_ VSS_ +.V_US_PHY_R K VSS_US_ VSS_ K VSS_US_ VSS_ K VSS_US_ K VSS_US_ PIE_K_VSS_ V_VREF--PI V TOLERNE PIE_K_VSS_ m +V_VREF R PIE_K_VSS_ +V K/F_ PIE_K_VSS_ PIE_K_VSS_ +V_VK m H PIE_K_VSS_ PIE_K_VSS_ +.V J +.V_VK m PIE_K_VSS_ PIE_K_VSS_ J HH-PT PIE_K_VSS_ PIE_K_VSS_ K +V_V U/V_ PIE_K_VSS_ PIE_K_VSS_ M PIE_K_VSS_ PIE_K_VSS_ M PIE_K_VSS_ PIE_K_VSS_ m M PIE_K_VSS_ PIE_K_VSS_ P PIE_K_VSS_ PIE_K_VSS_ *_ F VSS GROUN Part of VSSK F G H K K K L L L L L L L M M M M M N N N P P P P P P R R R R R R R T T T U U V Y E E P R R T U U V V V W W W W L U/V_ U/V_ U/V_.U/V/XR_.U/V/XR_.U/V/XR_.U/V/XR_ S S +.V_S R +.V_US_PHY_R.U/V/XR_.U/V/XR_ U/.V_ US_PHY_.V--US Phy digital power +.V_S +V_V V--US nalog PLL power L LMPGSN(,.)_.U/V/XR_ U/.V_.U/.V/XR_ +.V L LMPGSN(,.)_ +.V_VK VK_.--US Phy digital power.u/.v/xr_ +.V +V_VK VK_.--nalog system PLL power L LMPGSN(,.)_.U/.V/XR_ PROJET : J Quanta omputer Inc. N/R Size ocument Number Rev ustom S-PWR/EOUPLING / ate: Monday, ugust, Sheet of

16 OVERLP OMMON PS WHERE POSSILE FOR UL-OP RESISTORS. It must ready refore RSMRST# +.V_S For rev. +.V +.V +.V_S R R R K/F_ K/F_ *K/F_ REQUIRE STRPS () S_GPIO () S_GPIO R.K_ Maybe can be remove -- internla pull up check M () PI_LK_TPM () (,) PI_LK PI_LK () PI_LK () LP_LK () () LP_LK RT_LK () Z_RST# GPIO R *.K_ R.K_ GPIO R K/F_ R K/F_ R *K/F_ R *K/F_ R K/F_ R K/F_ R K/F_ TYPE GPIO GPIO PULL HIGH PI_LK_TPM OOTFIL TIMER ENLE PI_LK USE EUG STRPS PI_LK RESERVE PI_LK RESERVE LP_LK ENLE PI MEM OOT LP_LK LKGEN ENLE RT_LK INTERNL RT EFULT Z_RST# E ENLE FWH LP SPI L :.K pull down N L :.K pull down L :.K pull down L :.K pull down N PULL LOW OOTFIL TIMER ISLE EFULT IGNORE EUG STRPS EFULT ISLE PI MEM OOT EFULT LKGEN ISLE EFULT EXT. RT (P on X, apply KHz to RT_LK) E ISLE EFULT RSV N N EUG STRPS S HS K INTERNL PU FOR PI_[:] +.V_S R K/F_ N_PWRG_IN: RS/RX =.V; RS =.V o NOT share it with S_PWRG when use Internal lk Gen (Need S PLL initialize firstly) +.V R *K/F_ R _ S_PWRG_IN S_PWRG_IN () (,) (,) (,) (,) (,) (,) (,) (,) R *.K/F_ R *.K/F_ R *.K/F_ R *.K/F_ R *.K/F_ R *.K/F_ R *.K/F_ R *.K/F_ () VRM_PWRG () PWROK *.U/.V_ HH-PT HH-PT +.V U N V Y R *NLSZFTG SOT- *.U/V_ *_ +.V R _ RX,RS N_PWRG_IN R N_PWRG_IN (,) *K/F_ +.V Use.K P. N/S POWER GOO IRUIT _ R W_PWRG () PI_ PI_ PI_ PI_ PI_ PI_ PULL HIGH USE LONG RESET EFULT USE PI PLL EFULT USE PI LK EFULT USE IE PLL EFULT USE EFULT PIE STRPS EFULT RESERVE PULL LOW USE SHORT RESET YPSS PI PLL YPSS PI LK YPSS IE PLL USE EEPROM PIE STRPS LSZ LUG I(P) NLSZFTG(SOT-) I OTHER(P) SNUGVR(SOT-) SOT- SOT- PROJET : J Quanta omputer Inc. N/R Size ocument Number Rev ustom S-STRPS ate: Monday, ugust, Sheet of

17 + N () () PIE_RST# PE_GPIO () () () () () () () () () () () () () () () () () () () () () () EXT_LVS_TXUK# EXT_LVS_TXUK EXT_LVS_TXU# EXT_LVS_TXU# EXT_LVS_TXU# EXT_LVS_TXU EXT_LVS_TXU EXT_LVS_TXU EXT_LVS_TXLK# EXT_LVS_TXLK () () () EXT_LVS_TXL# EXT_LVS_TXL# EXT_LVS_TXL# EXT_LVS_TXL EXT_LVS_TXL EXT_LVS_TXL ISP_ON_MXM LVS_LON_VG EXT_LVS_PNLLK EXT_LVS_PNLT () () EXT_HSYN EXT_VSYN EXT_VG_RE EXT_VG_GRN EXT_VG_LU EXT_RT_LK EXT_RT_T E@HH-PT E@HH-PT MXM_SMT MXM_SMLK T +V_MXM T R E@K/F_ MXM_RST# EXT_LVS_TXUK# EXT_LVS_TXUK EXT_LVS_TXU# EXT_LVS_TXU# EXT_LVS_TXU# EXT_LVS_TXU EXT_LVS_TXU EXT_LVS_TXU EXT_LVS_TXLK# EXT_LVS_TXLK EXT_LVS_TXL# EXT_LVS_TXL# EXT_LVS_TXL# EXT_LVS_TXL EXT_LVS_TXL EXT_LVS_TXL ISP_ON_MXM LVS_LON_VG EV_LVS_L_RGHT EXT_LVS_PNLLK EXT_LVS_PNLT EXT_HSYN EXT_VSYN EXT_VG_RE EXT_VG_GRN EXT_VG_LU EXT_RT_LK EXT_RT_T VG_THERM# dd for MXM // PWREN# LVS_ULK# LVS_ULK LVS_UTX# LVS_UTX# LVS_UTX# LVS_UTX# LVS_UTX LVS_UTX LVS_UTX LVS_UTX LVS_LLK# LVS_LLK LVS_LTX# LVS_LTX# LVS_LTX# LVS_LTX# LVS_LTX LVS_LTX LVS_LTX LVS_LTX LVS_PPEN LVS_LEN LVS_L_RGHT _LK _T VG_HSYN VG_VSYN VG_RE VG_GREEN VG_LUE _LK _T TV_Y/HTV_Y/TV_VS TV_/HTV_Pr TV_VS/HTV_Pb THERM# SM_T SM_LK E@MXM_TYPEII MXM_VIN R E@_ Q E@MENE LVS VI / HMI VI- VI- RT TV HMI_VI_LK# / VI LK# HMI_VI_LK / VI LK HMI_VI_TX# / VI TX# HMI_VI_TX# / VI TX# HMI_VI_TX# / VI TX# HMI_VI_TX / VI TX HMI_VI_TX / VI TX HMI_VI_TX / VI TX HMI_VI_HP / VI HP MXM_PWREN _LK _T P_L / IGP/VI LK# P_L# / IGP/VI LK P_L / IGP/VI TX# P_L / IGP/VI TX# P_L / IGP_/VI TX# P_L# / IGP/VI TX P_L# / IGP/VI TX P_L# / IGP_VI TX P_HP / VI HP/ H_SI / IGP H_SO / IGP IGP_RSV / IGP P_UX# / IGP P_UX / IGP IGP_RSV / IGP IGP_RSV / IGP IGP_RSV / IGP IGP_RSV / IGP IGP_RSV / IGP IGP_RSV / IGP RSV RSV IGP_RSV / RSV IGP_RSV / RSV H_LK / RSV H_SYN / RSV RUNPWROK /TT# +V TX_HMI_L- TX_HMI_L- TX_HMI_L- TX_HMI_L- TX_HMI_L+ TX_HMI_L+ TX_HMI_L+ TX_HMI_L+ TMS_HP HMI_SL HMI_S VI HP SIN_MXM MXM_PWRG R Q E@TYU Q E@FN_NL TX_HMI_L- () TX_HMI_L+ () TX_HMI_L- () TX_HMI_L- () TX_HMI_L- () TX_HMI_L+ () TX_HMI_L+ () TX_HMI_L+ () TMS_HP (,) HMI_SL () HMI_S () remove caps. / R R E@_ *S K Z_ITLK_MXM () Z_SYN_MXM () R *K_ K E@K_ IN Q E@N Z_SIN () Z_SOUT_MXM () E@_ R +.V E@K_ MXM_PWREN +.V_MXM *E@u/V_ *E@u/V_ *E@.u/V_ *E@u/.V_ +V_MXM () IN (,) +.V E@.u/V_ E@p_ E@u/V_. E@u/V_ E@.u/V_ E@p_. E@u/.V_ E@.u/V_ E@p_.. R E@K/F_ MXM_VIN +V_MXM +V_MXM +.V_MXM *E@u/V_ *E@.u/V_ *E@p_ Z_RESET#_MXM MXM_VIN +V_MXM +V_MXM +.V_MXM +.V_MXM Modify // E@HH-PT Q *E@FN_NL T PE_GPIO () MXM_SPIF_OUT N PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN H_RST# / SPIF / E@MXM_TYPEII LK_REQ# PEX_RST# PEX_REFLK# PEX_REFLK PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX P P PRSNT# PRSNT# R *_ R E@_ PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP R PE_RESET_MXM# () MXM_RST# EXT_GFX_LKN () EXT_GFX_LKP () PEG_RXN[:] () PEG_RXP[:] () PEG_TXN[:] () PEG_TXP[:] () MXM_PRESENT# () E@_ () PE_GPIO +PWR_SR R R E@K_ E@K_ MXM_PWREN PWREN# Q E@NE R Q *K_ E@NE Modify for MXM // +PWR_SR.U/V_ E@PGM Q E@u/V_ E@u/V_ + -Test Modify E@U/V_.X. MXM_VIN MXM_PWREN +.V +V_MXM Q E@FN_NL +V_MXM MXM_PWREN +.V +.V_MXM remove Q,Q. / E@u/V_ Q *E@FS +.V_MXM dd // MXM_SMLK MXM_SMT N/R +.V Q E@NW--F MLK MLK (,) +.V Q E@NW--F MT MT (,) PROJET : J Quanta omputer Inc. Size ocument Number Rev MXM ONN ate: Thursday, ugust, Sheet of