ZR3. AMD S1 Turion 64 Rev.F Dual-Core/ Sempron Rev.F Single-Core Dual-Core 35W / Single-Core 25W (638 S1g1 socket) Page:3, 4, 5, 6 HT_LINK

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1 PU ORE MXIM MX Page:.V.VSUS/.V 0.V_VTER TI TPS/ Page: V_ORE.V.VSUS.V 0.V_VTER R-II SOIMM Page: R-II SOIMM Page: R-II /MHz ZR M S Turion Rev.F ual-ore/ Sempron Rev.F Single-ore ual-ore W / Single-ore W ( Sg socket) Page:,,, HT_LINK PU THERML SENSOR Page: X'TL.MHz lock generator IS Page: VPU/VPU V_S V/V VSUS/VSUS TI TP Page:0 VPU V_S VSUS V VPU VSUS V S-Video Page: mini R Page: 0 TV-OUT PIE N Ti RS -Pins FG Package Page:,,0, RG LVS RT LVS Page: Page:.V/.V GMT G/- TTERY HRGER MXIM ISL Power State Table Power ontrol Name Signal V_ORE.V VPU VS VSUS V VPU VSUS V.V 0.V_VTER.VS.VSUS.V.V VRON MINON N/ S_ON SUS MIN N/ SUS MIN MINON MINON Page: Page: S_ON SUSON MIN MINON Power State LWYS -S -S LWYS -S -S -S.V.V TTERY MI-IN Page: LINE-IN Page: Manufacturing Option ST H Page: PT H Page: IE-O Page: UIO OE RELTEK- L -pins Package udio MP MX Page: LINEOUT Page: Page: udio MP MX0 Page: SPEKER Page: ST T /00 zalia MOEM FOXONN M Page: RJ (External) S X PIE Ti -Pins G Package Page:,,, X'TL.KHz K NS PV -Pins Package Touchpad Page: LP MHZ Page: Keyboard Page: RT Page: PI US MHZ US.0 IOS SSTVF00 Page: FN Page: luetooth US interface Page:0 US SYSTEM US PORT* U,, US Page: 0 US MER Page: 0 RELTEK 00SL/L 0/00 LN REQ0# / GNT0# INTE# Page: ENE /0 ardbus controller REQ# / GNT# INTH#,INTG# Page: MINI-PI Wireless LN 0 REQ# / GNT# INTG#, INTE# Page: 0 TRNSFORMER Page: RJ Page: PMI SLOT Page: R REER Page: PROJET : ZR Quanta omputer Inc. Size ocument Number Rev LOK IGRM Wednesday, October, 00 ate: Sheet of

2 TLE OF ONTENTS Page 0 : LOK IGRM Page 0 : TLE OF ONTENTS Page 0 : THLON HT I/F Page 0 : THLON RII MEMORY I/F Page 0 : THLON TRL & EUG Page 0 : THLON PWR & GN Page 0 : RII SOIMMX Page 0 : RS-HT LINK0 I/F Page 0 : RS-PIE LINK I/F Page 0 : RS-SYSTEM I/F & VO Page : RS-POWER Page : External LOK GENERTOR Page : M PIE/PI/PU/LP I/F Page : M PI/GPIO/US/ Page : M H/POWER/EOUPLING Page : M STRPS Page : LN RTL0SL/L Page : ENE /0 Page : R RE & RUS SLOT Page 0 : MINI PI & PI-E,US PORT,LUETOOTH Page : RT & LVS & S-Video Page : H & ROM & HOLES Page : L & M & HP MP Page : SPEKER MP / JK Page : & FLSH Page : T/P,FN,SWITH,LE,K/ Page : TTERY HRGER Page : VORE MX Page : TPS/.V/.V Page 0 : TP /V Page :.V /.V SYSTEM PU R R N POWER VOLTGE TIVE SOPE V V V VPU VPU VORE V_RUN V.V V.V.V.V V.V V.V V_HT.V V.V V.V V VI[0..].V.V.V.V VQ.V PLLV V VSUS V VSUS.V.V V_S.V VLT_RUN.V 0.V_VTER.V.V V_VO VR.V LPV.V LPV.V LWYS LWYS -S -S.VSUS.V -S V_N 0.V.V.V.VSUS.V -S.VSUS.V -S 0.V_VTER 0.V PGE VPU RSMRST# SUS#, SUS# V,V,.V HWPG_.V HWPG_.V PU_OREPG N_PWRG E_PWRG PU_PWRG PI_RST# PU_RST# POWER UP SEQUENE T T T T>= 0 ms ms < T < 0ms ms < T < ms S V.V.V.V V_S.V.V_S.V V.V V_K.V V_ST.V XTLV_T.V PLLV_T.V PIE_PV.V PIE_VR.V PU-PWR.V VQ.V V_VREF V.V_SU_PHY.V VSUS.V -S S_S_V.V S_S_.V.V PROJET : ZR Quanta omputer Inc. Size ocument Number Rev TLE OF ONTENTS ate: Wednesday, October, 00 Sheet of

3 PROESSOR HYPERTRNSPORT INTERFE VLT_x N VLT_x RE ONNETE TO THE LT_RUN POWER SUPPLY THROUGH THE PKGE OR ON THE IE. IT IS ONLY ONNETE ON THE OR TO EOUPLING NER THE PU PKGE VLT_RUN U VLT_ VLT_ VLT_ VLT_0 VLT_ VLT_ VLT_ VLT_0 E E E E.U/.V_ () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN0_P () HT_IN0_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN_P () HT_IN_N () HT_IN0_P () HT_IN0_N N P M M L M K K H H G H F F E F N N L M L L J K G H G G E F E E L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 T T V U V V Y W T R U U V U W W HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT0_P () HT_OUT0_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT_P () HT_OUT_N () HT_OUT0_P () HT_OUT0_N ().V L FJH0 L FJH0 VLT_RUN 0 ohm().u/.v_.u/.v_ / hange 0pF to placed on the VLT power fill..u/v_.u/v_ LYOUT: Place bypass cap on topside of board NER HT POWER PINS THT RE NOT ONNETE IRETLY TO OWNSTREM HT EVIE, UT ONNETE INTERNLLY TO OTHER HT POWER PINS PLE LOSE TO VLT0 POWER PINS 0P_ 0P_ VLT_RUN () HT_LKIN_P () HT_LKIN_N () HT_LKIN0_P () HT_LKIN0_N J K J J L0_LKIN_H L0_LKIN_L L0_LKIN_H0 L0_LKIN_L0 L0_LKOUT_H L0_LKOUT_L L0_LKOUT_H0 L0_LKOUT_L0 Y Y Y W HT_LKOUT_P () HT_LKOUT_N () HT_LKOUT0_P () HT_LKOUT0_N () R./F_ HT_TLIN_P P HT_PU_TLOUT_P HT_TLIN_N L0_TLIN_H L0_TLOUT_H T P HT_PU_TLOUT_N T R./F_ L0_TLIN_L L0_TLOUT_L R T () HT_TLIN0_P N L0_TLIN_H0 L0_TLOUT_H0 R HT_TLOUT0_P () P () HT_TLIN0_N L0_TLIN_L0 L0_TLOUT_L0 R HT_TLOUT0_N () thlon S Processor Socket PROJET : ZR Quanta omputer Inc. Size ocument Number Rev THLON HT I/F ate: Wednesday, October, 00 Sheet of

4 E.VSUS V_VTT_SUS_PU IS ONNETE TO THE V_VTT_SUS POWER SUPPLY THROUGH THE PKGE OR ON THE IE. IT IS ONLY ONNETE ON THE OR TO EOUPLING NER THE PU PKGE R M Q[0..] U M Q[0..] () M Q[0..] M Q[0..] () M Q M Q M Q M_T K/F_ M_T F M Q M Q M_T M_T F M Q M Q0 M_T M_T E M Q0 PU_M_VREF M Q M_T0 M_T0 Y M Q M Q M_T M_T W M Q M Q M_T M_T Y M Q M Q M_T M_T F M Q R M Q M_T M_T F M Q.U_ 000p/0V_ M Q M_T M_T K/F_ F M Q M Q M_T M_T M Q M Q M_T M_T F M Q M Q M_T M_T Y M Q.VSUS M Q0 M_T M_T Y M Q0 0.V_VTER M Q M_T0 M_T0 W E M Q M Q M_T M_T W M Q U M Q M_T M_T 0 M Q R M Q M_T M_T Y 0 M Q M Q M_T M_T W M Q.F_ MEMVREF VTT 0 F M Q M_T M_T M Q VTT_SENSE VTT 0 F M Q M_T M_T T Y0 M Q VTT_SENSE VTT 0 F0 M Q M_T M_T M Q VTT 0 E0 M Q M_T M_T M Q M_ZN VTT W0 M Q0 M_T M_T 0 E0 M Q0 M_ZP MEMZN VTT 0 M Q M_T0 M_T0 Y0 F0 M Q MEMZP VTT 0 E M Q M_T M_T M Q VTT 0 M Q M_T M_T Y M Q VTT 0 M Q M_T M_T W M Q R M Q M_T M_T W M Q () M S# V M0_S_L M0_LK_H Y M_LKOUT () E M Q M_T M_T M Q () M S# J M0_S_L M0_LK_L M_LKOUT# ().F_ M Q M_T M_T M Q () M S# V M0_S_L M0_LK_H E M_LKOUT0 () M Q M_T M_T M Q () M S#0 T M0_S_L0 M0_LK_L F M_LKOUT0# () M Q M_T M_T Y G M Q M Q0 M_T M_T H M Q0 () M S# Y M0_S_L M0_LK_H F M_LKOUT () G M Q M_T0 M_T0 H0 M Q () M S# J M0_S_L M0_LK_L F M_LKOUT# () M Q M_T M_T E M Q () M S# W M0_S_L M0_LK_H M_LKOUT () M Q M_T M_T E M Q () M S#0 U M0_S_L0 M0_LK_L M_LKOUT# () G M Q M_T M_T J G M Q M Q M_T M_T H M Q () M_KE H M_KE M0_OT W M_OT () E M Q M_T M_T F M Q () M_KE J M_KE0 M0_OT0 W M_OT () E PLE THEM LOSE TO M Q M_T M_T F0 M Q () M_KE J0 M_KE M0_OT V0 M_OT () M Q M_T M_T M Q PU WITHIN " () M_KE0 J M_KE0 M0_OT0 U M_OT0 () M Q M_T M_T M Q () M [0..] M [0..] () 0 M M M Q0 M_T M_T F K M Q0 M M_ M_ J 0 K0 M M Q M_T0 M_T0 E M Q M M_ M_ J V M M Q M_T M_T E0 M Q M M_ M_ W K M M Q M_T M_T M Q M M_ M_ L L0 M M Q M_T M_T M Q M 0 M_ M_ L 0 R M 0 M Q M_T M_T G M Q M M_0 M_0 U L M M Q M_T M_T G M Q M M_ M_ L L M M Q M_T M_T M Q M M_ M_ M L M M Q M_T M_T F M Q M M_ M_ L M M M Q M_T M_T E M Q M M_ M_ N 0 M0 M M Q0 M_T M_T H M Q0 M M_ M_ N M M M Q M_T0 M_T0 E M Q M M_ M_ N M M M Q M_T M_T E M Q M M_ M_ N N M M Q M_T M_T H M Q M M_ M_ P N M M Q M_T M_T E M Q M 0 M_ M_ P R M 0 M Q M_T M_T M Q M_0 M_0 T E M Q M_T M_T H G M Q M Q M_T M_T H M Q () M S# K M_NK M_NK K M S# () M Q M_T M_T G M Q () M S# R0 M_NK M_NK T M S# () M Q M_T M_T H M Q () M S#0 T M_NK0 M_NK0 U M S#0 () M Q0 M_T M_T F M Q0 M M[0..] M_T0 M_T0 G M M[0..] () M RS# T0 M_RS_L M_RS_L U M RS# () () M M[0..] M M[0..] () M M M M () M S# U0 M_S_L M_S_L V M S# () M M M_M M_M Y M M () M WE# U M_WE_L M_WE_L U M WE# () M M M_M M_M E M M M M M_M M_M Y M M R II: M/TRL/LK M M M_M M_M E M M M M M_M M_M F M M thlon S M M M_M M_M E M M M M0 M_M M_M M M0 Processor Socket E M_M0 M_M0 M QS F W M QS M QS# M_QS_H M_QS_H E W M QS# M QS M_QS_L M_QS_L E Y M QS M QS# M_QS_H M_QS_H W M QS# M QS M_QS_L M_QS_L F M QS M QS# M_QS_H M_QS_H F 0 M QS# M QS M_QS_L M_QS_L M QS M QS# M_QS_H M_QS_H M QS# M QS M_QS_L M_QS_L F G M QS M QS# M_QS_H M_QS_H E G M QS# M QS M_QS_L M_QS_L M QS M QS# M_QS_H M_QS_H M QS# M QS M_QS_L M_QS_L G M QS M QS# M_QS_H M_QS_H G M QS# 0.V_VTER M Q M_QS_L M_QS_L G M Q M QS#0 M_QS_H0 M_QS_H0 H M QS#0 M_QS_L0 M_QS_L0.U/.V_.U/.V_.U/.V_ 0.V_VTER.U/.V_.U/V_.U/V_.U/V_.U/V_ () M QS#[0..] M QS#[0..] () M QS#0 M QS#0 M QS# M QS# 0 M QS# M QS# M QS# M QS# 000p/0V_ 000p/0V_ 000p/0V_ 000p/0V_ 0P_ 0P_ 0P_ 0P_ M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# To SOIMM socket (Far) () M QS[0..] Processor R Memory Interface M Q M QS M QS M QS M QS M QS M QS M QS R: T thlon S Processor Socket M Q M QS M QS M QS M QS M QS M QS M QS M QS[0..] () To SOIMM socket (near) PROJET : ZR Quanta omputer Inc. Size ocument Number Rev THLON RII MEMORY I/F Wednesday, October, 00 ate: Sheet of E

5 PU_V_RUN PU_V_RUN.U/.V_ R 00_.V LYOUT: ROUTE V TRE PPROX. 0 mils WIE (USE x mil TRES TO EXIT LL FIEL) N 00 mils LONG..U/V_ V R.K/F_ L LMPG0SN 00p/V_.VSUS.V 00U/.V_.U_ If M SI is not used, the SI pin can be left unconnected and SI should have a 00- ( %) pulldown to VSS. Place them to PU within " VLT_RUN To Power () OREFV () OREF- () PULK.V R R R R 00p/V_ *00_ *00_ R 00_.F_.F_ R T T THLON ontrol and ebug PU_V_RUN.VSUS U PU_V_RUN F H_THERMTRIP# V THERMTRIP_L F F H_PROHOT# V PROHOT_L R PU_HT_RESET# PU_LL_PWROK RESET_L 00_ PU_LTSTOP# PWROK F0 LTSTOP_L VI () PU_SI_R VI F VI () PU_SI_R SI VI F SI VI VI () VI () PU_HTREF VI P VI () PU_HTREF0 HT_REF VI R HT_REF0 VI0 VI0 () PU_PRESENT# PU_PRESENT_L F V_F_H E PSI_L V_F_L PSI_L PU_VIO_SUS_F_H W PU_VIO_SUS_F_L VIO_F_H Y PSI_L is a Power Status Indicator signal. This signal is asserted VIO_F_L when the processor is in a low powerstate. PSI_L should be PU_LKIN_S_P connected to the power supply controller, if the controller supports PU_LKIN_S_N LKIN_H LKIN_L skipmode, or diode emulation mode. PSI_L is asserted by the processor during the and S states. (,) PU_PWRG.V PU_LL_PWROK U NSZ0PX_NL () PULK# 00p/V_.VSUS /F_ T PU_RY G0 RY R 0_ PU_TMS PU_REQ# R0 0_ R 0_ PU_TK TMS REQ_L E0 R0 0_ PU_TRST# TK R 0_ PU_TI TRST_L F PU_TO TI TO E T.VSUS (0,,) LT_STOP#.VSUS R.U_ 00_ PU_LTSTOP# U NSZ0PX_NL.V.VSUS.VSUS V R.U_ 00_ R0 R T T PU_TEST_H_YPSSLK_H PU_TEST_L_YPSSLK_L PU_TEST_PLLTEST0 PU_TEST_PLLTEST PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST_P0 PU_TEST_SNSHIFTEN PU_TEST_THERM PU_TEST_THERM E E G H0 E F W W Y TEST_H TEST_L TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST_H TEST_L TEST TEST TEST TEST TEST0 TEST_H TEST_L TEST TEST TEST0 TEST E E F J H F E K PU_TEST_H_FLKOUT_P R 0.F_ PU_TEST_L_FLKOUT_N ROUTE S 0 Ohm IFFERENTIL PIR PLE IT LOSE TO PU WITHIN " PU_TEST_SNLK PU_TEST_TSTUP PU_TEST_SNSHIFTEN PU_TEST_SNEN PU_TEST0_SNLK PU_TEST_SINGLEHIN PU_TEST_URNIN# T () LT_RST# (,,) E_PWRG (0,) N_PWRG R 0_ R *0_ PU_HT_RESET# U NSZ0PX_NL separated input voltage R.K/F_ E_PWRG PSI_L 0K_ Q0 MMT0.V 0K_ PSI# PSI# () P0 P N0 N R R P R RSV0 RSV RSV RSV RSV RSV RSV RSV MIS RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 H H G R W R H H R.K/F_ R.VSUS R 0_ Q MMT0 M NPT S SOKET Processor Socket.VSUS Q MMT0 00_ PU_E_PROHOT# ().VSUS R 00_ H_THERMTRIP# THERM_SYS_PWR (0) H_PROHOT# R0 *0_ PU_PROHOT# () PU_TEST_SINGLEHIN PU_TEST_URNIN# PU_PRESENT# PU_TEST_H_YPSSLK_H R *00_ R 00_ R K/F_ R 0/F_ PU H/W MONITOR V R PU_TEST_THERM /F_ PU_TEST_THERM 0 mil trace / 0 mil space MIL V_THM.U_ 00P/0V_ ddress H U V XN XP -OVT G -LT SMT SMLK GN V R *0K_ KSMT KSMLK V R 0K_ To S GPIO MX_L# () To FN V R 0K_ MT_PU () V R0 0K_ MLK_PU () MX_OV# () SMus SLVE RESS: h PU_TEST_SNEN PU_TEST0_SNLK PU_TEST_SNLK PU_TEST_SNSHIFTEN PU_TEST_SNSHIFTEN PU_TEST_P PU_TEST_P0 PU_TEST_L_YPSSLK_L PU_TEST_PLLTEST0 PU_TEST_PLLTEST R 00_ R 00_ R0 00_ R 00_ R 00_ R 00_ R 00_ R 0/F_ R 00_ R 00_ IF no use which Net need pull-up or down PROJET : ZR Quanta omputer Inc. Size ocument Number Rev THLON TRL & EUG Wednesday, October, 00 ate: Sheet of

6 V_ORE G H J J J K K0 K K L L L L L M M M M0 N N N P P0 R R R R T T T T0 T T U U U U V V V0 UE V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO POWER thlon S Processor Socket V_ORE V V W Y J K L M P T U V H J K K K K L M M M M N P P P P R T T T T U V V V V Y.VSUS E E E E E E E E F F F F F F F F F H H H H J UF VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS GROUN VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VS0 VS VS VS VS VS VS VS VS VS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS thlon S Processor Socket J J J0 J J J J K K K K K K K L L L0 L L L L M M M M N N N0 N N P P P P P R R0 R R T T T T T T U U U U0 U U U U V V V V V V V W Y Y N V_ORE U/0V_ V_ORE.U/V_.VSUS U/0V_.VSUS.U/.V_.VSUS.0U_ OTTOMSIE EOUPLING U/0V_.U/V_ U/0V_ U/0V_ V_ORE Near TI RS hipset EOUPLING ETWEEN PROESSOR N IMMs PLE LOSE TO PROESSOR S POSSILE.U/.V_.0U_.0U_.U/V_ 0.U/.V_ 0P_ U/0V_ 0P_ 0.U/V_.U/.V_ 0P_ U/0V_.U/V_.U/V_ 0 0P_ U/0V_.U/V_.U/V_ 0P_ U/0V_.0U_.U/V_ 0P_ U/0V_.0U_.U/V_ 0P_ 0 U/0V_.0U_.0U_ thlon Sg upg Top View PROESSOR POWER N GROUN F PROJET : ZR Quanta omputer Inc. Size ocument Number Rev THLON PWR & GN ate: Wednesday, October, 00 Sheet of

7 E E M S# M_OT M M M S#0 M M M M M Q0 M Q PT_SM M M 0 M M M Q M M M M Q PLK_SM M M_LKOUT M 0 M M_LKOUT# M_LKOUT M M M_LKOUT# M M M Q M Q0 M M Q M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q MVREF_IM M Q M Q M Q M Q MVREF_IM M M M0 MVREF_IM M M M M M M M M M M M Q M M M M M QS M QS M QS M QS M QS M QS M QS M Q0 M Q M Q M Q M Q M Q0 M Q M M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M 0 M Q M M M M M Q M M M Q M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M M M M M M0 M M M M M M M M M QS# M M QS M QS M QS M QS M QS M QS M Q M QS M M M M M Q M_LKOUT# M M 0 M Q M M Q M_LKOUT0 M M_LKOUT# M_LKOUT M_LKOUT M_LKOUT# M Q M Q M Q M Q M M Q M_LKOUT0# M Q M_LKOUT M Q M Q M Q M Q M 0 M S# M M M 0 M M M S# M M M M M M RS# M M S# M S# M S# M WE# M S#0 M_OT0 M S# M M 0 M M M S#0 M 0 M M M M S# M M M M M M M S# M S# M_OT M S# M RS# M S#0 M_OT M S# M WE# M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M_LKOUT0# M_LKOUT M_LKOUT0 M_LKOUT# M_KE M_KE M_KE M_KE0 PT_SM (,,0) PLK_SM (,,0) 0.V_VTER 0.V_VTER 0.V_VTER 0.V_VTER 0.V_VTER.VSUS 0.V_REF V V V.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS M S#0 () M S# () M [0..] () M_KE0 () M_KE () M RS# () M S# () M WE# () M S#0 () M S# () M_OT0 () M Q[0..] () M_LKOUT0 () M_LKOUT0# () M_LKOUT () M_LKOUT# () M_OT () M S# () M S# () M S#0 () M QS#[0..] () M QS[0..] () M M[0..] () M_LKOUT () M_LKOUT# () M_LKOUT () M_LKOUT# () M_OT () M_KE () M_KE () M_OT () M [0..] () M S# () M S#0 () M S# () M QS#[0..] () M QS[0..] () M M[0..] () M RS# () M S# () M WE# () M Q[0..] () M S# () M S# () M S# () M S# () Size ocument Number Rev ate: Sheet of R SO-IMM Wednesday, October, 00 Size ocument Number Rev ate: Sheet of R SO-IMM Wednesday, October, 00 Size ocument Number Rev ate: Sheet of R SO-IMM Wednesday, October, 00 TERMINTOR EOUPLING PITOR R TERMINTOR REVERSE (H=) REVERSE (H=) SMus RESS: 0h SMus RESS: h Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M Q QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 0 S S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VS 0 VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS Q QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VS SO-IMM N0 RII_SOIMM_R SO-IMM N0 RII_SOIMM_R Quanta omputer Inc. PROJET : ZR Quanta omputer Inc. PROJET : ZR.U-V_.U-V_ *0U/.V/XR_ *0U/.V/XR_.U-V_ 0.U-V_ 0.U_.U_ RN _PR_S RN _PR_S.U_.U_.U_.U_.U-V_.U-V_ RN _PR_S RN _PR_S RN _PR_S RN _PR_S RN _PR_S RN _PR_S RN _PR_S RN _PR_S R _ R _ RN _PR_S RN _PR_S 0U/0V/XR_ 0 0U/0V/XR_ 0 RN _PR_S RN _PR_S R *0_ R *0_.U-V_.U-V_.U-V_.U-V_.U-V_.U-V_ RN _PR_S RN _PR_S RN _PR_S RN _PR_S.U_ 0.U_ 0 R K/F_ R K/F_ RN _PR_S RN _PR_S.U-V_ 0.U-V_ 0.U-V_ 0.U-V_ 0 RN _PR_S RN _PR_S.U_.U_ RN _PR_S RN _PR_S.U_.U_ R _ R _.U_ 0.U_ 0.U-V_.U-V_.P_.P_.U-V_.U-V_.U/0V/XR_.U/0V/XR_ RN _PR_S RN _PR_S.U-V_.U-V_ RN _PR_S RN _PR_S.U-V_.U-V_.P_.P_.U-V_ 0.U-V_ 0.U-V_.U-V_.U-V_ 0.U-V_ 0 RN _PR_S RN _PR_S.U_ 0.U_ 0.U-V_.U-V_.U_.U_ RN _PR_S RN _PR_S.U-V_.U-V_ RN _PR_S RN _PR_S.P_.P_.U-V_ 00.U-V_ 00 R _ R _ 0U/.V_ 0U/.V_.U_.U_ RN _PR_S RN _PR_S.U-V_ 0.U-V_ 0 RN0 _PR_S RN0 _PR_S Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M Q QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 0 S S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VS 0 VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS Q QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VS SO-IMM N RII_SOIMM_R SO-IMM N RII_SOIMM_R.U_.U_.U_.U_.U_.U_.U-V_.U-V_.U-V_.U-V_.U_.U_ 0U/0V/XR_ 0U/0V/XR_ RN _PR_S RN _PR_S RN _PR_S RN _PR_S.U_.U_.U-V_.U-V_ RN0 _PR_S RN0 _PR_S RN _PR_S RN _PR_S.P_.P_.U_.U_.U_.U_.U_.U_.U-V_.U-V_.U_.U_ *0U/.V/XR_ *0U/.V/XR_.U_.U_ RN _PR_S RN _PR_S.U-V_.U-V_ U/0V_ U/0V_.U-V_.U-V_ R0 _ R0 _.U_ 0.U_ 0.U-V_ 0.U-V_ 0.U-V_.U-V_.U_.U_.U_.U_.U-V_.U-V_ R K/F_ R K/F_ RN _PR_S RN _PR_S.U_.U_ R 0K_ R 0K_.U-V_ 0.U-V_ 0.U-V_.U-V_ RN _PR_S RN _PR_S.U_.U_ RN _PR_S RN _PR_S.U_.U_.U-V_ 0.U-V_ 0 0.U/0V/XR_ 0.U/0V/XR_.U-V_.U-V_ RN _PR_S RN _PR_S

8 U VHT_PKG () HT_OUT_P R HT_RXP () HT_OUT_N R HT_RXN R () HT_OUT_P HT_RXP () HT_OUT_N R HT_RXN U () HT_OUT_P HT_RXP () HT_OUT_N U HT_RXN () HT_OUT_P U HT_RXP U () HT_OUT_N HT_RXN () HT_OUT_P W HT_RXP W0 () HT_OUT_N HT_RXN () HT_OUT0_P HT_RX0P () HT_OUT0_N HT_RX0N 0 () HT_OUT_P HT_RXP () HT_OUT_N 0 HT_RXN () HT_OUT_P HT_RXP () HT_OUT_N Y HT_RXN T () HT_OUT_P HT_RXP () HT_OUT_N R HT_RXN U () HT_OUT_P HT_RXP () HT_OUT_N U HT_RXN () HT_OUT_P V HT_RXP U () HT_OUT_N HT_RXN () HT_OUT_P V HT_RXP V () HT_OUT_N HT_RXN () HT_OUT_P HT_RXP () HT_OUT_N HT_RXN () HT_OUT_P HT_RXP () HT_OUT_N HT_RXN () HT_OUT_P HT_RXP () HT_OUT_N HT_RXN () HT_OUT0_P HT_RX0P () HT_OUT0_N HT_RX0N W () HT_LKOUT_P HT_RXLKP () HT_LKOUT_N W HT_RXLKN Y () HT_LKOUT0_P HT_RXLK0P () HT_LKOUT0_N W HT_RXLK0N () HT_TLOUT0_P P HT_RXTLP () HT_TLOUT0_N P HT_RXTLN PRT OF HT_TXP P HT_IN_P () HT_TXN P HT_IN_N () HT_TXP P HT_IN_P () HT_TXN P HT_IN_N () HT_TXP M HT_IN_P () HT_TXN M HT_IN_N () HT_TXP M HT_IN_P () HT_TXN M HT_IN_N () HT_TXP L HT_IN_P () HT_TXN L HT_IN_N () HT_TX0P G HT_IN0_P () HT_TX0N G HT_IN0_N () HT_TXP J0 HT_IN_P () HT_TXN J HT_IN_N () HT_TXP F HT_IN_P () HT_TXN F HT_IN_N () HT_TXP N HT_IN_P () HT_TXN N HT_IN_N () HT_TXP L HT_IN_P () HT_TXN M HT_IN_N () HT_TXP K HT_IN_P () HT_TXN K HT_IN_N () HT_TXP J HT_IN_P () HT_TXN K HT_IN_N () HT_TXP G HT_IN_P () HT_TXN H HT_IN_N () HT_TXP F HT_IN_P () HT_TXN F HT_IN_N () HT_TXP E HT_IN_P () HT_TXN F HT_IN_N () HT_TX0P E HT_IN0_P () HT_TX0N E HT_IN0_N () HT_TXLKP L HT_LKIN_P () HT_TXLKN L HT_LKIN_N () HT_TXLK0P J HT_LKIN0_P () HT_TXLK0N J HT_LKIN0_N () HT_TXTLP N HT_TLIN0_P () HT_TXTLN P HT_TLIN0_N () HYPER TRNSPORT PU I/F R./F_ HT_RXLP HT_TXLP R 00/F_ HT_RXLN HT_RXLP HT_TXLP HT_TXLN R./F_ HT_RXLN HT_TXLN RSM HT PROJET : ZR Quanta omputer Inc. Size ocument Number Rev RS-HT LINK0 I/F ate: Wednesday, October, 00 Sheet of

9 WLN MINI R (0) MINI_PIE_RXP0 (0) MINI_PIE_RXN0 U G GFX_RX0P G GFX_RX0N J GFX_RXP J GFX_RXN J GFX_RXP J GFX_RXN L GFX_RXP L GFX_RXN L GFX_RXP L GFX_RXN M GFX_RXP M GFX_RXN M GFX_RXP M GFX_RXN P GFX_RXP P GFX_RXN P GFX_RXP P GFX_RXN R GFX_RXP R GFX_RXN R GFX_RX0P R GFX_RX0N U GFX_RXP U GFX_RXN W GFX_RXP W GFX_RXN Y GFX_RXP Y GFX_RXN V GFX_RXP W GFX_RXN GFX_RXP GFX_RXN W GPP_RX0P W GPP_RX0N PRT OF PIE I/F GFX GFX_TX0P GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TX0P GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GPP_TX0P GPP_TX0N J H K K K L L L N N P P P R R R T U V V V W W W Y E E E GPP_TX0P_ GPP_TX0N_ Place these caps close to connector.u_.u_ MINI_PIE_TXP0 (0) MINI_PIE_TXN0 (0) WLN MINI R T T Y GPP_RXP GPP_RXN GPP_RXP GPP_RXN PIE I/F GPP GPP_TXP GPP_TXN GPP_TXP GPP_TXN E E T T _TX0P_ () _RX0P W 0.U_ S_RX0P S_TX0P E _TX0P () _TX0N_.U_ () _RX0N W S_RX0N PIE I/F S S_TX0N 0 _TX0N () () _RXP () _RXN R R R: R: 0K_.K/F_ PE_ISET PE_TXISET 0KOhm FOR RS.KOhm FOR RS0.KOhm FOR RS NI FOR RS0 GPP_RXP GPP_RXN S_RXP S_RXN GPP_TXP GPP_TXN S_TXP S_TXN PE_ISET(PE_LI) PE_PL(PE_LRP) PE_TXISET(N) PE_NL(PE_LRN) E RSM HT _TXP TXN_ PE_PL R PE_NL R R: 0 Ohm FOR RS Ohm FOR RS0 R:.U_ 0 0/F_ 00/F_.U_ Ward update to 00 Ohm FOR RS KOhm FOR RS0 _TXP () _TXN () V_PKG PROJET : ZR Quanta omputer Inc. Size ocument Number Rev RS-PIE LINK I/F ate: Wednesday, October, 00 Sheet of

10 .V HTPV L HTPV K0H_ 0U/0V/XR_.U/.V_ V V_N L K0H_ 0U/.V_.U_ *00U/.V_ () TV_/R_SYS () TV_Y/G_SYS () TV_OMP_SYS () VG_RE () VG_GRN () VG_LU (,,) LT_STOP# close to N R 0/F_ close to N R 0/F_.V V R 0K_ Q MMT0 TV_/R_SYS TV_Y/G_SYS TV_OMP_SYS R 0/F_ R0 0/F_ R K/F_ R 0/F_ R 0/F_ LT_STOP#_N.V.V L High, LO ROM STRP ISLE.V PLLV LO_ROM#: LO ROM STRP ENLE Low, LO ROM STRP ENLE L K0H_ K0H_ (,0,) (,) () R () () () () VQ () () () () () 0U/0V/XR_ 0U/0V/XR_ 0/F_ LINK_RST# N_PWRG LLOW_LTSTOP HTREFLK N_OS NSR_LKP NSR_LKN SLINK_LKP SLINK_LKN R MREQ# PHL_LK PHL_T V.U/.V_ K/F_.U/0V_.U/0V/XR_ V () () () ().U_ VSYN HSYN LK T HTPV R 0_ R 0_ R LO_ROM# R R R R R R R T T T T T G H 0 0 TV_/R_SYS TV_Y/G_SYS 0 TV_OMP_SYS E F G R /F_ R0 0_ R 0_ 0 0 N_RST# 0 LT_STOP#_N R 0K_ R 0K_ PLLV F E G G *.K_ FT_GPIO0 *.K_ FT_GPIO *.K_ FT_GPIO *.K_ FT_GPIO *.K_ FT_GPIO.K/F_ K/F STRP_T U V V VSSN VSSN VI VSSI VQ VSSQ _R Y_G OMP_ RE GREEN LUE VSYN HSYN RSET SL S RT/TVOUT PLLV(PLLV) PLLVSS HTPV HTPVSS SYSRESET# POWERGOO LTSTOP# LLOW_LTSTOP HTTSTLK HTREFLK TVLKIN OSIN OSOUT(PLLV) GFX_LKP GFX_LKN S_LKP S_LKN FT_GPIO0 FT_GPIO FT_GPIO FT_GPIO FT_GPIO FT_GPIO MREQb I_LK I_T THERMLIOE_P THERMLIOE_N TMS_HP _T TESTMOE STRP_T TXOUT_L0P PRT OF TXOUT_L0N TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_U0P TXOUT_U0N TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXLK_LP TXLK_LN TXLK_UP TXLK_UN LPV LPVSS LVR_ LVR_ LVR_ LVR_ LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVSSR LVS_IGON LVS_LON LVS_LEN VO_0(GPP_TXP) VO_(GPP_TXN) VO_(N) VO_(GPP_RXP) VO_(GPP_RXN) VO_(N) VO_(N) VO_(GPP_TXN) VO_(GPP_TXP) VO_(GPP_RXN) VO_0(GPP_RXP) VO_(N) VO_VSYN(N) VO_E(N) VO_HSYN(N) VO_IKP(N) VO_IKN(N) PM PLL PWR LOKs MIS. RSM HT VO LVS H G E E H G E F F E G F E E E E0 0 E E E LPV LVR_ L_PON LVS_LON LVS_LEN LVR_ R K/F_ N_PWRG TXLOUT0 () TXLOUT0- () TXLOUT () TXLOUT- () TXLOUT () TXLOUT- () T T TXUOUT0 () TXUOUT0- () TXUOUT () TXUOUT- () TXUOUT () TXUOUT- () T T TXLLKOUT () TXLLKOUT- () TXULKOUT () TXULKOUT- ().U_ 0.U_.U_.U/.V_.U/.V_.U/.V_ L_POWER_ON () 0/ hange R from 0 to k T RS: LVR=.V L0 K0H_ L K0H_ L K0H_ L_POWER_ON.V.V.V R OSOUT() RS OSOUT RS0 PLLV R0 0_ 0/ dd For TOPPOLY L Power On Garbage VO_0() VO_() VO_() VO_(E) VO_(E) VO_() VO_(E0) VO_0 VO_ VO_ VO_ VO_ VO_ VO_ GPP_TXP GPP_TXN GPP_RXP GPP_RXN GPP_TXN GPP_TXP GPP_RXN L_PON LVS_LON LVS_LEN R0 R R K/F_.K/F_ *.K/F_ LVS_LON N_PWRG V U *NSZ0PX_NL LON () 0/0 dd R0 For L Power OnOff Sequence PROJET : ZR Quanta omputer Inc. VO_0(0) VO_0 GPP_RXP Size ocument Number Rev RS-SYSTEM I/F & VO Friday, October 0, 00 ate: Sheet of 0

11 VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS F E G Y P R E M J G J L L L0 L M M0 M M N N L P P0 P R R R0 W Y U0 H W Y G H R E T T E R H M F M VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS VSS VSS VSS VSS VSS VSS VSS VSS VSS M V V V F V H G J H E0 J E F L M M J P T N P R U T U U Y Y W Y Y Y R 0 G Y Y UE RSM HT PR OF GROUN VLT_RUN 0 ohm().v L V.V V.V RS: V=.V V 0U/0V_ L 0 SW00 0 ohm() L LMPG0SN 0 00U/.V_ TI00G ohm (000m) L 0U/0V_ R 0_ U/0V_ TI00G TI00G SW00 0U/0V_ U/.V_ U/0V_.U/.V_ U/0V_ SW00 V U/0V_ VR VVO VPLL U/.V_ V U/0V_.U/.V_ U/0V_ U/0V_ U/0V_ U/.V_ U/0V_ U/0V_ U/0V_ 0mil trace width 0 U/.V_ 0 U/0V_ U/0V_ 0mil trace width 0mil trace width 0mil trace width U/0V_ VHT_PKG V_PKG V_PKG U/0V_ V_PKG 0 0U/0V/XR_ E E Y W 0 E J J E U W E E E E F F G M U V_HT PRT OF V_HT V_HT V_HT V_HT V_HT V_HT V_HT V_HT V_HT0 V_HT V_HT V_HT V_HT V_HT V_ V_ V_(V_) V_(V_) V_(V_) V_(V_) V_(V_) V_(V_) V_(V_) V_(V_0) VR_ VR_ V_VO(VR_) V_VO(VR_) V_VO(VR_) V_(VPLL_) V_(VPLL_) VSS(VSSPLL_) VS(VSSPLL_) VHT_PKG V_PKG V_PKG RSM HT POWER V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ G E E M F L E L L L M R M N N N J H P P R R U U P L J 0 G0 U U U/0V_ U/0V_ U/0V_ U/0V_ V U/0V_ U/0V_ U/0V_ U/0V_ 0 0U/0V_ U/0V_ 0U/0V_ U/0V_ 0 ohm().v L FJH0 00U/.V_ 00U/.V_ V_N.V L TIU0 L TIU0 0 0 U/0V_ 0U/0V/XR_ 0U/0V/XR_ N RS POWER STTES Power Signal S S S/S G VHT ON ON VR V V V V V ON ON ON ON ON ON ON ON ON ON ON ON VI ON ON PLLV ON ON HTPV ON ON VR ON ON LPV ON ON LVR ON ON LVR ON ON PROJET : ZR Quanta omputer Inc. Size ocument Number Rev RS-POWER Wednesday, October, 00 ate: Sheet of

12 V LK_V L SK00T-0Y-S ohm/ 0 U/0V_.U_.U_.U_ 0.U_ 0.U_ 00.U_.U_ 0.U_ LK_V 0.U_ V L0 K0H0_ U/0V_ V L SK00T-0Y-S LK_V_US LK_V U0 LK_V () SYS_RST# R0 V *0_ 00ohm/00m L0 00ohm/00m LK_V R 0K_ U/0V_ SK00T-0Y-S U/0V_.U_ P_ Y.MHZ LK_V_REF 00.U_ P_ Parallel Resonance rystal R *M_ LK_XIN LK_XOUT 0 V_PU V_SR V_SR V_SR V_SR V_ V_TIG V_REF VHTT GN_PU GN_SR GN_SR GN_SR GN_SR GN_ GN_TIG GN_REF GNHTT XIN XOUT RESET_IN# N V GN PULKT0 PULK0 PULKT PULK TIGLKT0 TIGLK0 TIGLKT TIGLK SRLKT0 SRLK0 SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK 0 0 LK_V PULK_EXT_R PULK#_EXT_R NSR_LKP_R NSR_LKN_R SLINK_LKP_R SLINK_LKN_R SSR_LKP_R SSR_LKN_R GPP_LK0P_R GPP_LK0N_R R R R /F_ /F_ R0 0_ R0 0_ R0 0_ R0 0_ R 0_ R 0_ R 0_ R 0_ /F_ /0 hange Footprint to 00. PULK () PULK# () NSR_LKP (0) NSR_LKN (0) SLINK_LKP (0) SLINK_LKN (0) SSRLK () SSRLK# () LK_PIE_MINI (0) LK_PIE_MINI# (0) N N S MINI (,,0) (,,0) PLK_SM PT_SM R0 0_ R 0_ 0 SMLK SMT *LKREQ# *LKREQ# *LKREQ# LKREQ# LKREQ# LKREQ# T T T0 Ioh = * Iref (.m) Voh = 0 ohm R0 0K/F_ 0 IREF/**Turbo MHz_/**Sync MHz_0/**Mode *FS/REF *FS/REF0 *FS/REF HTTLK0 LK_M R LK_M R R R /F_ /F_ *0P_ 0 *0P_ SLK () USLK () LK_V EXT LK FREQUENY SELET TLE(MHZ) RTM0T- Note: * internal 0K pull up, ** internal 0K pull down R 0K_ R 0K_ R 0K_ R0 R R0 *0K_ *0K_ *0K_ FS FS F PU HTT SR TIG US SS S_OSIN_R R00 /F_ S_OSIN () N_OSIN_R R0 /F_ N_OS (0) /- 0.% /- 0.% /- 0.% /- 0.% /- 0.% /- 0.% /- 0.% LK_M R LK_M R LKREQ# LKREQ# LKREQ# R R R0 R R0 LK_V *0K_ *0K_ *0K_ *0K_ *0K_ HTREFLK_R R /F_ R./F 0P_ 0 *0P_ HTREFLK (0) *0P_ 0/ More overshoot and undershoot improvement /- 0.% heck M clock PROJET : ZR Quanta omputer Inc. Size ocument Number Rev EXTERNL LOK GENERTOR ate: Wednesday, October, 00 Sheet of

13 VSUS VRT VRT R? R? R?.V LG RT (0,0,) VPU RT_N0 LINK_RST# S LIRTION RESISITOR VLUE 0 OHM %.0K % 0 ohm PIE Power R0 K/F_ / attery should be connected directly - not through a UL resistor, and not through a diode. Q MMT0 L TI00G_ RT_N0 RT_N0 0 U/0V_ R R.K/F_ 0 OHM % 0 OHM %.U_ R.K %.V U/0V_ RT_N0 U NSZ0PX R.U_ L 0.U_.U_ *0_ PIE_PV PIE_VR VRT 0 SK00T-0Y-S_ R.K/F_ JP *lear P R0 00/F_ R.U_.K/F_.U_ E_PWRG VPU 0U/0V_ () SSRLK () SSRLK# 0.U_ () () () () () () () () _RX0P _RX0N _RXP _RXN T T T T _TX0P _TX0N _TXP _TXN T T T T PIE_VR 0 U/0V_.U_ 0.U_.U RX0P RX0N RXP RXN_ PIE_LRP PIE_LRN PIE_LI PIE_PV Ti Recommend Vendor: NSK Part Number: NXG.KEFU PPM. K_X R 0M_ For 0, connect to PU_PG/LT_PG For, connect to SSMUXSEL/GPIO0 (,) PU_PWRG T0 T T T (,0,) LT_STOP# T0 T T (0) LLOW_LTSTOP T0 () H_PSLP# T () LT_RST# R R R0 R P_ V.U_ R Y.V m.0u_.0u_.0u_.0u_ 0/F_ 0/F_.K/F_.U_.KHZ 0M_.K_ K_X 0 P_ TI recommand have internal pull-up R *0K_ K_X K_X G0 J J P P M M K K H H T T T T M M M M E E E U U F F F G G G G J J L L L N R *0_ H_INTR W H_NMI W H_INIT# W H_SMI# H_IGNNE# H_0M# H_FERR# Y STP_PU# H H_PSLP# R0 *0_ PRSLPVR W FOR, THIS LL IS LT_RST# ONLY U _RST# PIE_RLKP PIE_RLKN PIE_TX0P PIE_TX0N PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_RX0P PIE_RX0N PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_LRP PIE_LRN PIE_LI PIE_PV PIE_PVSS PIE_VR_ PIE_VR_ PIE_VR_ PIE_VR_ PIE_VR_ PIE_VR_ PIE_VR_ PIE_VR_ PIE_VR_ PIE_VR_0 PIE_VR_ PIE_VR_ PIE_VR_ X X S xmm XTL PU_PG/LT_PG INTR/LINT0 NMI/LINT INIT# SMI# SLP#/LT_STP# IGNNE#/SI 0M#/SI FERR# STPLK#/LLOW_LTSTP PU_STP#/PSLP_V# PSLP_O#/GPIO PRSLPVR LT_RST#/PRSTP#/PROHOT# PILK0 Part of PILK PILK PILK PILK PILK PILK SPIF_OUT/PILK/GPIO PI EXPRESS INTERFE PU LP PI INTERFE PIRST# 0/ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM /ROM 0/ROM /ROM /ROM /ROM /ROM /ROM /ROM0 /ROM /ROM /ROM 0/ROM /ROM /ROM /ROM 0 E0#/ROM0 E#/ROM E#/ROMWE# E# FRME# EVSEL#/ROM0 IRY# TRY#/ROMOE# PR/ROM STOP# PERR# SERR# REQ0# REQ# REQ# REQ#/GPIO0 REQ#/GPIO GNT0# GNT# GNT# GNT#/GPIO GNT#/GPIO LKRUN# LOK# INTE#/GPIO INTF#/GPIO INTG#/GPIO INTH#/GPIO L0 L L L LFRME# LRQ0# LRQ#/GNT#/GPIO MREQ#/REQ#/GPIO SERIRQ RT PI LKS RTLK RT_IRQ#/GPIO VT RT_GN U T U V W U V T J W Y W W Y J E J H J H H H G G F J G H G F Y G J E G H H F H G G F F F F G G H H F J H W F F E PI_MINI R _ PLK_MINI PLK_MINI (,0,) PI_ R _ PLK_ PLK_ (,) PI_PM R _ PLK_PM PLK_PM (,) PI_SIO R _ PLK_SIO PLK_SIO () PI_LK R _ PILK PILK () PI_LN R _ PLK_LN PLK_LN (,) PI_LK R0 _ PILK PILK () SPIF_RR R 0_ S_SPIF_OUT () PIRST#_ FRME# EVSEL# IRY# TRY# PR STOP# PERR# SERR# REQ0# REQ# REQ# REQ# REQ# GNT0# GNT# GNT# GNT# GNT# LKRUN# PI_LOK# INTE# INTF# INTG# INTH# L0/FWH0 L/FWH L/FWH L/FWH LFRME#/FWH LRQ#0 LRQ# MREQ# SERIRQ U/0V_ [0..] [0..] (,,,0,) 000p/0V_ E_PWRG (,,) E_PWRG PIRST#_ 0 R *P_.K_ R0 *0_ PI_LOK# INTE# INTF# INTG# INTH# E0# (,,0,) E# (,,0,) E# (,,0,) E# (,,0,) FRME# (,,0,) EVSEL# (,,0,) PERR# IRY# (,,0,) FRME# TRY# (,,0,) TRY# PR (,,0) STOP# STOP# (,,0) PERR# (,,0) SERR# (,,0) REQ# REQ0# () EVSEL# REQ0# REQ# (0) REQ# REQ# () GNT0# () GNT0# GNT# GNT# (0,) GNT# GNT# () GNT# LKRUN# (,0,) REQ# SERR# INTE# (,0) REQ# INTF# (0) IRY# INTG# () INTH# () GNT# dd for debug. PR L0/FWH0 () L/FWH L/FWH () L/FWH () L/FWH L/FWH () LFRME#/FWH (,) L/FWH L0/FWH0 MREQ# (0) SERIRQ (,0,) SERIRQ RT_LK () UTO_ON# () VRT MREQ# / For EMI PLK_MINI P_ PLK_ P_ PLK_PM P_ PLK_SIO P_ PILK P_ PLK_LN P_ PILK P_ V.U_ U NSZ0PX_NL PIRST# PIRST# (,,0,,) P_ V R.K_ R.K_ R.K_ 0.U_ R.K_ R.K_ V RN.KX_ 0 RN.KX_.U_ RN0 *.KX_ RN.KX_ R *.K_ R.K_ R 00K/F_.U_ R 00K/F_ R 00K/F_ R 00K/F_ R 0K_ R 0K_ RN 0KX_ LKRUN# P_ LRQ# LRQ#0.U_ N TON R0 K/F_ R 0K_ H_PSLP# R *0K_ PROJET : ZR Quanta omputer Inc. Size ocument Number Rev ustom M PIE/PI/PU/LP I/F Wednesday, October, 00 ate: Sheet of

14 PU/P V_S S_OSIN R *_ *0P_ SUS# SUS# NSWON# PME# SUS_STT# RI# SWI# SYS_RST# PIE_WKE# EMIL_LE# MX_L# Z_RST# _RST# PU_PROHOT# RIN# GTE0 EXTEVNT# S_THERMTRIP# PLK_SM PT_SM RST_H# S_LL# GPIO GPIO GPIO GPIO GPIO GPIO GPIO0 GPIO0 GPIO GPIO PSPK PU_PROHOT# _SIN Z_SIN _SIN0 _ITLK_R Z_RST# Z_SYN Z_SOUT Z_ITLK US power use S power,ut Over current signal datasheet is S only,ut TI FE say use S is ok KSMI# US_OP# SI# US_OP# US_OP# US_OP# US_OP# US_OP# US_OP# R RP RP RN R R R R R R R0 R R0 R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R0 R R R 0KX_.K/F_ *0KX_ 0KX_.K/F_.K/F_.K/F_.K/F_ 0K_ 0K_ 0K_ 0K_.K/F_ 0K_ 0K_ *0K_ 0K_.K/F_.K/F_ *0K_ 0K_ 0K_.K_.K_ 0K_ *0K_.K/F_ 0K_ 0K_ 0K_ 0K_ 0K_ *0K_ *0K_ 0K_ 0K_ 0K_ *0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ V_S V () () 0.U_.U ITLK_M () Z_ITLK _SOUT_M () (,,) () (,0) PME# () SUS# () SUS# NSWON# E_PWRG () GTE0 () RIN# () SWI# elay 0ms after S powerok () RSMRST# () (,,0) (,,0) (,) PU_PROHOT# () SYS_RST# (0) PIE_WKE# () EMIL_LE# () () () () () (,0,) 0 0 () S_OSIN RST_H# () PSPK PLK_SM PT_SM PU_PWRG () SI# () KSMI# _SOUT _SIN0 Z_SIN H_PSLP# MX_L# LT_STOP# R _ *P_ R _ *P_ R0 _ T T T T T T T0 T T T T T T T Z_ITLK R R00 R PME# RI# SUS# SUS# NSWON# SUS_STT# 0K_ 0K_ 0K_ GTE0 RIN# SWI# EXTEVNT# PU_PROHOT# SYS_RST# PIE_WKE# EMIL_LE# S_THERMTRIP# RSMRST# S_OSIN GPIO0 GPIO GPIO GPIO RST_H# GPIO PSPK PLK_SM PT_SM OR_I OR_I0 R 0_ GPIO0 S_LL# US_OP# US_OP# US_OP# US_OP# Z_RST# US_OP# US_OP# US_OP# SI# KSMI# Z_ITLK Z_SOUT Z_SYN _ITLK_R _SIN0 Z_SIN _SIN _SYN_R _RST# GPIO GPIO GPIO H_PSLP# GPIO MX_L# R 0_ () _SYN_M F E F E G F G F E G E F N M K L K L L L J J M L E E T U PI_PME#/GEVENT# RI#/EXTEVNT0# SLP_S# SLP_S# PWR_TN# PWR_GOO SUS_STT# TEST TEST TEST0 G0IN KRST# LP_PME#/GEVENT# LP_SMI#/EXTEVNT# S_STTE/GEVENT# SYS_RESET#/GPM# WKE#/GEVENT# LINK/GPM# SMLERT#/THRMTRIP#/GEVENT# RSMRST# M_OS ST_I#/GPIO0 ROM_S#/GPIO GHI#/ST_IS#/GPIO W_PWRG/GPIO SMRTVOLT/ST_IS#/GPIO SHUTOWN#/GPIO SPKR/GPIO SL0/GPO0# /GPO# SL/GPO# S/GPO# _SL/GPIO _S/GPIO SSMUXSEL/ST_IS#/GPIO0 LL#/GPIO US_O#/SLP_S/GPM# US_O#/Z_OK_RST#/GPM# US_O#/GEVENT# US_O#/GEVENT# US_O#/R_RST#/GPM# US_O#/GPM# US_O#/GPM# US_O#/GPM# US_O#/GPM# US_O0#/GPM0# Z_ITLK Z_SOUT Z_SIN/GPIO Z_SYN Z_RST# _ITLK/GPIO _SOUT/GPIO Z_SIN0/GPIO Z_SIN/GPIO Z_SIN/GPIO _SYN/GPIO0 _RST#/GPIO N N N N N N N N R _ S xmm OS / RST ZLI US O GPIO Part of PI / WKE UP EVENTS US INTERFE US PWR () _RESET#_M USLK US_ROMP US_TEST US_TEST0 US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP0 US_HSM0- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- US_HSP US_HSM- VTX_0 VTX_ VTX_ VTX_ VTX_ VRX_0 VRX_ VRX_ VRX_ VRX_ V VSS VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_0 VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_0 VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_ VSS_US_0 VSS_US_ VSS_US_ VSS_US_ 0 H G E E G H E E G H G H E G H E E F F F F F F F G G H H J J J J J J S_M_X US_ROMP R _ R R0 T0 T0 T T T T *_.K/F_ USP (0) USP- (0) USP (0) USP- (0) USP (0) USP- (0) USP (0) USP- (0) USP (0) USP- (0) USP0 (0) USP0- (0).U_.U_ U/0V_ *0P_ V USLK () U: / IO US: / IO US: / IO US: M/ IO US: LUETOOTH US: MINI R.U_.U_ R R US power.v_v V_US OR_I0 OR_I oard I I I0 0 0.U_.U/0V_ *0K_ *0K_.U_ L 0 U/0V_ SK00T-0Y-S R R0 V_S 00 PT H ST H L TI00G 0 U/0V_ 0K_ 0K_ V_S LG 0/0 Stuff, to P For EMI Situation. R _ Z_SOUT R _ Z_SYN () Z_SOUT () Z_SYN (,) Z_RESET# P_ P_ *P_ *P_ 0 *P_ R _ *P_ Z_RST# PROJET : ZR Quanta omputer Inc. Size ocument Number Rev ustom M PI/GPIO/US/ Wednesday, October, 00 ate: Sheet of

15 ST_TX0_ ST_TX0-_ ST_L ST_X ST_X ST_T# ST_X ST_X P0 P P P P P P P P P P0 P P P P P P[0..] V_VREF PK# (,) PREQ () PIOR# () PIOW# () PS# () PS# () P0 () P () P () PHRY () IRQ () ST_TXP0 () ST_TXN0 () ST_RXP0 () ST_RXN0 () HLE# (,) P[0..] () V_K_.V.V_S.V_T PLLV_T XTLV_T XTLV_T.V.V PLLV_T XTLV_T PLLV_T.V_T.V.V_T.V V V.V.V V VQ_V V_.V.V V_S S_S_V S_S_.V.VUS_PHY.V_S Size ocument Number Rev ate: Sheet of M H/POWER/EOUPLING ustom Wednesday, October, 00 Size ocument Number Rev ate: Sheet of M H/POWER/EOUPLING ustom Wednesday, October, 00 Size ocument Number Rev ate: Sheet of M H/POWER/EOUPLING ustom Wednesday, October, 00 ST Power 0ohm/ 0ohm/ LG PU_PWR=.V WHEN 0 PU_PWR=.V WHEN :R When PT mount 000J ST nd Osc mount F 00ohm(00m) 00ohm(00m) L0 *SK00T-0Y-S@ST L0 *SK00T-0Y-S@ST *U/0V_ *U/0V_ T0 T0 R *0M_@ST R *0M_@ST.U_.U_ T00 T00.U_.U_.U_.U_ *U/0V_ *U/0V_ 0.U_ 0.U_ *U/0V_ *U/0V_ *U/0V_ *U/0V_.U_.U_.U_.U_ L SK00T-0Y-S L SK00T-0Y-S Quanta omputer Inc. PROJET : ZR Quanta omputer Inc. PROJET : ZR U/0V_ U/0V_.U/0V_.U/0V_.U_.U_ *S@ST *S@ST 00U/.V_ 00U/.V_ U/0V_ U/0V_ 0.U_ 0.U_ L *SK00T-0Y-S@ST L *SK00T-0Y-S@ST *U/0V_ *U/0V_ U/0V_ U/0V_.U_.U_ R0 *0_ R0 *0_ *.U_ *.U_ R 0_@PT R 0_@PT L SK00T-0Y-S L SK00T-0Y-S U/0V_ U/0V_ IE_IORY IE_IRQ IE_0 IE_ IE_ Y IE_K# IE_RQ IE_IOR# IE_IOW# IE_S# W IE_S# W IE_0/GPIO IE_/GPIO IE_/GPIO E IE_/GPIO F IE_/GPIO G IE_/GPIO0 H IE_/GPIO J IE_/GPIO J IE_/GPIO H IE_/GPIO G IE_0/GPIO G IE_/GPIO F IE_/GPIO F IE_/GPIO E IE_/GPIO IE_/GPIO0 V_ST_ E XTLV_ST V_ST_ E PLLV_ST_ J0 VSS_ST_0 E VSS_ST_ F VSS_ST_ F V_ST_ E PLLV_ST_ VSS_ST_ F VSS_ST_ F VSS_ST_ G VSS_ST_ G VSS_ST_ G VSS_ST_ G VSS_ST_0 G VSS_ST_ G VSS_ST_ V_ST_ E ST_TX H ST_TX- H ST_RX J ST_RX- H ST_TX J ST_TX- H ST_RX J ST_RX- H ST_TX0 H ST_TX0- J ST_RX0- H0 ST_RX0 J0 ST_TX H ST_TX- J ST_RX- H ST_RX J ST_L F ST_X ST_X ST_T#/GPIO V_ST_ F V_ST_ F V_ST_ G V_ST_ G VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ VSS_ST_ E SPI_I/GPIO J SPI_O/GPIO J SPI_LK/GPIO G SPI_HOL#/GPIO G SPI_S#/GPIO G FNOUT/GPIO T FNOUT/GPIO V FNIN0/GPIO0 N FNIN/GPIO P FNIN/GPIO W LN_RST#/GPIO ROM_RST#/GPIO G 0/GPIO V /GPIO L /GPIO M /GPIO V /GPIO M /GPIO P /GPIO M /GPIO0 V TEMPIN0/GPIO P TEMPIN/GPIO P TEMPIN/GPIO T TEMPIN/TLERT#/GPIO T FNOUT0/GPIO M V N VSS M TEMP_OMM P V_ST_ H V_ST_0 H V_ST_ J V_ST_ J VSS_ST_ G VSS_ST_ G VSS_ST_ G0 V_ST_ J VSS_ST_ G VSS_ST_ H0 V_ST_ J VSS_ST_ H V_ST_ J T /00 Part of S xmm SERIL T POWER SERIL T SPI ROM HW MONITOR U T /00 Part of S xmm SERIL T POWER SERIL T SPI ROM HW MONITOR U *.0U_ *.0U_ 0 U/0V_ 0 U/0V_.U_.U_ 0.U_ 0.U_.U_.U_ SW00 SW00 U/0V_ U/0V_ 0.U_ 0.U_ T0 T0 L SK00T-0Y-S L SK00T-0Y-S Y *MHZ@ST Y *MHZ@ST R *K/F_@ST R *K/F_@ST T T R K/F_ R K/F_.U_.U_ 0.U_ 0.U_ T0 T0 0 U/0V_ 0 U/0V_.U_.U_ U/0V_ U/0V_.U_.U_ R0 0_@PT R0 0_@PT T0 T0.U_.U_ *.U_ *.U_.U_.U_ *P_@ST *P_@ST *.U_ *.U_ T0 T0 *.U_ *.U_ U/0V_ U/0V_.U_.U_ R0 0_@PT R0 0_@PT.U_.U_ 0U/0V_ 0U/0V_ *U/0V_ *U/0V_ *.0U_ *.0U_ 0.U_ 0.U_ T T U/0V_ U/0V_ 0.U_ 0.U_.U_.U_ T0 T0 R 0_@PT R 0_@PT.U_.U_ R 0_ R 0_ L SK00T-0Y-S L SK00T-0Y-S.U_.U_ U/0V_ U/0V_ 00 *00U/.V_ 00 *00U/.V_ T0 T0 U/0V_ U/0V_.U_.U_ *P_@ST *P_@ST T T L *TI00G_@ST L *TI00G_@ST U/0V_ U/0V_.U_.U_ *U/0V_ *U/0V_ U/0V_ U/0V_.U_.U_ 0 U/0V_ 0 U/0V_.U_.U_ L FJH0 L FJH0 U/0V_ U/0V_ 0 0U/0V_ 0 0U/0V_ L FJH0 L FJH0 U/0V_ U/0V_.U_.U_ T T VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ W VSS_ V VSS_0 V VSS_ V VSS_ V VSS_ V VSS_ U VSS_ T VSS_ R VSS_ R VSS_ P VSS_ P VSS_ P VSS_ N VSS_ N VSS_ M VSS_0 M VSS_ L VSS_ L VQ_ VQ_ VQ_ VQ_ VQ_ L VQ_ L VQ_ M VQ_ P VQ_ P VQ_0 T VQ_ V VQ_ W VQ_ W VQ_ W VQ_ W VQ_ VQ_ VQ_ VQ_ VQ_0 PU_PWR V_VREF E S_.V_ H US_PHY_.V_ V_ N V_ M V_ N V_ R V_ U V_ R V_ M V_ N V_ U VSS_ J VSS_ J VSS_ G VSS_ F S_.V_ G S_.V_ H S_.V_ H VK_.V VSSK VSS_ G VSS_ J VSS_ J VSS_ J V_0 U V_ V V_ V S_.V_ VQ_ E VQ_ E VQ_ E VQ_ H VQ_ J VSS_ U S_.V_ S_.V_ F S_.V_ J S_.V_ J S_.V_ K US_PHY_.V_ US_PHY_.V_ US_PHY_.V_ 0 VSS_ Y VSS_ E VQ_ VSS_ VSS_ 0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ F VSS_ E VSS_ M VSS_ M US_PHY_.V_ VK_.V VQ_ J VQ_ J PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ G PIE_VSS_ G PIE_VSS_ G PIE_VSS_ H PIE_VSS_ J PIE_VSS_ J PIE_VSS_ K PIE_VSS_ L PIE_VSS_ L PIE_VSS_ L PIE_VSS_ L PIE_VSS_ L PIE_VSS_ M PIE_VSS_ M PIE_VSS_0 M PIE_VSS_ N PIE_VSS_ N PIE_VSS_ P PIE_VSS_ P PIE_VSS_ P PIE_VSS_ P PIE_VSS_ P PIE_VSS_ P PIE_VSS_ T PIE_VSS_0 T PIE_VSS_ T PIE_VSS_ T PIE_VSS_ T PIE_VSS_ U PIE_VSS_ V PIE_VSS_ V PIE_VSS_ V PIE_VSS_ V PIE_VSS_ V PIE_VSS_0 V PIE_VSS_ V VSS_0 R VSS_ T VSS_ V VSS_ W VSS_ E PIE_VSS_ F PIE_VSS_0 J PIE_VSS_ V Part of 0 S xmm POWER U Part of 0 S xmm POWER U

16 V V_S V V V V V_S V V V V V R0 *0K_ R 0K_ R *0K_ R0 0K_ R0 0K_ R *0K_ R0 0K_ R0 *0K_ R0 *0K_ R0 0K_ R *0K_ R0 *0K_ () _SOUT () UTO_ON# () RT_LK () S_SPIF_OUT () PILK (,) PLK_PM () PILK () PLK_SIO (,0,) PLK_MINI (,) PLK_LN (,) PLK_ (,) LFRME#/FWH R0 0K_ R *0K_ R 0K_ R00 *0K_ R0 *0K_ R 0K_ R *0K_ R 0K_ R0 0K_ R *0K_ R 0K_ R 0K_ PLK_MINI PLK_ REQUIRE STRPS PULL HIGH PULL LOW _SOUT USE EUG STRPS IGNORE EUG STRPS EFULT RT_LK INTERNL RT EFULT EXTERNL RT PI_LK PI_LK PI_LK0 PI_LK USE INT. PLL USE EXT. MHZ EFULT PU IF=K EFULT PU IF=P ROM TYPE: H, H = PI ROM H, L = LP TYPE I ROM L, H = LP TYPE II ROM EFULT L, L = FWH ROM NOTE:FOR,PILK[:] RE ONNETE TO SUSTRTE LLS PILK[:0] PULL HIGH PULL LOW UTO_ON# S_SPIF_OUTPLK_PM PLK_SIO PLK_LN PWRON MNUL PWR ON EFULT UTO PWR ON SPIF_OUT SIO MHz SIO MHz EFULT PI_LK XTL MOE US PHY POWEROWN NOT ISLE SUPPORTE EFULT MHZ OS MOE EFULT PI_LK US PHY POWEROWN ENLE PI_LK PIE_M_SET HIGH PIE_M_SET HLOW EFULT LFRME# LFRME# ENLE THERMTRIP# ISLE THERMTRIP# EFULT IOS ENLE FTER STRTUP V V V V V V V R 0K_ R *0K_ R *0K_ R *0K_ R0 *0K_ R0 *0K_ R *0K_ (,) PK# (,,,0) (,,,0) (,,,0) (,,,0) (,,,0) (,,,0) R *0K_ R *0K_ R 0K_ R 0K_ R 0K_ R 0K_ R *0K_ EUG STRPS PULL HIGH PK# USE LONG RESET EFULT PI_ PI_ YPSS PI PLL PI_ YPSS PI LK PI_ YPSS IE PLL PI_ USE EEPROM PIE STRPS PI_ LG PULL LOW USE SHORT RESET USE PI PLL EFULT USE PI LK EFULT USE IE PLL EFULT USE EFULT PIE STRPS EFULT PROJET : ZR Quanta omputer Inc. Size ocument Number Rev ustom M STRPS ate: Wednesday, October, 00 Sheet of

17 I Select : Interrupt Pin : INTF# Request Indicate : REQ0# Grant Indicate : GNT0# VS_LV.VS_LV V_S U_0 L.U_ K0H_ 0U_.U_ 0.U_.U_.U_ VS_LV 0.U_.U_ V_S VS_LV (,,,0,) [0..] U V VL V VL PI N RTL0SL N 0 N 0 VH V V---.V IGITL VH V NLOG VL-----.V NLOG V-----.V IGITL V_----.V NLOG RTL00L V---.V IGITL VL-----.V NLOG V-----.V IGITL VH V NLOG V V V V_ PM V V V V V V V V V V V PME ISOLTE LWKE 0 N N N N 0 N N 0 TRL N N N N N LN_PME# ISOLTE TRL VS_LV.VS_LV T V R K_ R K/F_ TRL.U_ VS_LV RX V_ TX T_RX- RX- TX- Q SKR 0 u_0 U R T T T 0 0U_ L RX T R- T- RX- TX- MT TX 0.U_ K0H_ 0.U_ T_RX MT T_TX- MT0 T_TX 0U_.U_ R.U_.U_.U_.VS_LV R.U_ R0 (,0,) (,,0,) E0# (,,0,) E# (,,0,) E# (,,0,) E# (,,0) STOP# (,,0) PERR# (,,0,) TRY# (,,0,) EVSEL# (,,0,) FRME# (,,0,) IRY# (,,0) SERR# () REQ0# (,,0,,) PIRST# () GNT0# (,0) INTE# (,,0) PR.K/F_ (,) LKRUN# PLK_LN LKRUN# PLK_LN E0# E# E# E# STOP# PERR# TRY# EVSEL# R 00_ FRME# IRY# SERR# REQ0# PIRST# GNT0# INTE# PR R 0_ E0 E E E STOP PERR TRY EVSEL ISEL FRME IRY SERR REQ RST GNT INT PR RSET LKRUN LK MII LE OS EEPROM TX- N N N N RX- RX TX- TX N LE LE LE0 XTL XTL 0 EES EESK 0 EEI EEO 0 RX- RX TX- TX LNLINK# LNT# LN_XIN LN_XOUT EESEL EELK EEI EEO / Reserve circuit For close Lan chips. R R R R *./F_ *./F_./F_./F_ R0 *M_ *.0U_.0U_ Near Lan chipset Y.0000 MHz P_ P_ Near Transformer RX- RX TX- TX R R R R./F_./F_ *./F_ *./F_ V_S LNT# R 0_ R 0 T_RX-.0U_ *.0U_ */F_ NS 0 / hange to 0.0uF For different from reference design. N YELLOW_N YELLOW_P TX- TX /F_ /F_ 0 000P/KV_0 R R */F_ TX- GN *_ *0P_ GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN N N N N N N N N RTL00L / hange P To Match the frequency stability T_RX T_TX- T_TX TX TX TX0- TX0 GN V_S VS_LV V_S LNLINK# R0 0_ GREEN_N GREEN_P LN R0.K_ EESEL EELK EEI EEO *00P_ U S SK I O -GR V N N GN V_S 0.U_ LN_PME# R *0K_ LN_PME# () RJ PROJET : ZR Quanta omputer Inc. Size ocument Number Rev LN RTL0SL/00L ate: Wednesday, October, 00 Sheet of

18 V 0/0 Stuff R0, in materials For EMI Situation. PLK_PM R0 _ PLK_PM_R 0p_ 0 SLK SLK ().U_ V.U_ (,0) PME#.U_ 0.U_.U_.U_.U_.U_ V.U_.U_ Q0 () INTH# () INTG# (,0,) SERIRQ () PMSPK () REQ# () GNT# (,,0,,) PIRST# (,) PLK_PM (,,0,) FRME# (,,0,) IRY# (,,0,) TRY# (,,0,) EVSEL# (,,0) STOP# (,,0) PERR# (,,0) SERR# PM_PME# INTH# INTG# SERIRQ PM_PME# PMSPK PIRST# REQ# GNT# PIRST# PLK_PM FRME# IRY# TRY# EVSEL# STOP# PERR# SERR# R 0_ R 00_ PM_GRST# PM_ISEL V R K_ PM_SUS# V# V0# VPP VPP0 _RSV/ _RSV/ _RSV/ _# _# _VS# _VS# XPWREN#MSPWREN# XT/MSS XT/MST0 XT/MST XRE#/MSLK XT/MST XT/MST MSINX# R *0 RSV/ () _RSV/ () _RSV/ () _# () _# () _VS# () _VS# () XPWREN#MSPWREN# () XT/MSS () XT/MST0 () XT/MST () XRE#/MSLK () XT/MST () XT/MST () MSINX# () _# _# 0P_ 0P_ ENE ENE0 (,,,0,) *TEU [0..] J000T0 J000T [0..] N K L N M N M K M L K M K N M N J J H H G G F F E E E M SERR# L PERR# L STOP# L EVSEL# K TRY# K IRY# J FRME# H PILK G PIRST# F ISEL PIGNT# PIREQ# M0 G_RST# L SUSPEN# M SPKROUT L RI_OUT#/PME# M MFUN N MFUN L0 MFUN N0 MFUN K MFUN N MFUN K MFUN0 J MFUN H SLKI M V# N V0# M VPP N VPP0 RSV/ J RSV/ E0 RSV/ L #/# #/# VS/VS VS/VS SMPWREN#/MSPWREN J H SMT/MSS G SMT/MST0 F SMT/MST E SMRE#/MSLK G SMT/MST H SMT/MST H MSINX# U /0 0/ / / /0 /0 / / / / / 0/ / / / / /IOWR# / /IOR# / /OE# 0/E# /0 / / / / / / / / 0/ E F0 E F F G0 G G H H0 J J K J0 K0 K L _[0..] _[0..] () (,,0,) (,,0,) (,,0,) (,,0,) (,,0) E0# E# E# E# PR E0# E# E# E# PR N N J E M E0# E# E# E# PR GN GN GN GN GN GN GN GN V V V V V V V V V V V V0 V_S GN_S UIO/V/SPKR# STSHG/V/STSHG# INT#/REY/IREQ# LOK#/ GNT#/WE# REQ#/INPK# SERR#/WIT# PERR#/ STOP#/0 EVSEL#/ TRY#/ IRY#/ FRME#/ LKRUN#/WP/IOIS# RST#/RESET LK/ SMSY# SME# SMWP# SM# SMLE/ST SMLE/SM SMT/ST0 SMWE#/SLK SMT/ST SMT0/ST SMWP#/SWP S# SPWREN# E0#/E# E#/ E#/ E#/REG# PR/ H E _/E0# _/E# _/E# _/E# _PR _/E0# () _/E# () _/E# () _/E# () _PR () H L M K F 0 F G K N L L H G E G H J J J F E E F G F F E G /0 V V V0# V# U0 V0# V#.V.V V V GN O# ENE P- SHN# VPP0 VPP V V V VPP 0 V V VPP0 VPP V VPP V V V V_RV R LK R 0_ SPWREN# S# SWP XT0/ST XT/ST XWE#/SLK XT/ST0 XLE/SM XLE/ST X# XWP# XE# XSY# _LK _RST# _LKRUN# SPWREN# () S# () SWP () XT0/ST () XT/ST () XWE#/SLK () XT/ST0 () XLE/SM () XLE/ST () X# () XWP# () XE# () XSY# () _LK () _RST# () _LKRUN# () V V.U_.U_.U_.U_ V 0.U_.U_.U_.U_.U_ VPP.U_.U_ V_RV.U_.U FRME# _IRY# _TRY# _EVSEL# _STOP# _PERR# _SERR# _REQ# _GNT# _LOK# _INT# _STSHG _UIO _FRME# () _IRY# () _TRY# () _EVSEL# () _STOP# () _PERR# () _SERR# () _REQ# () _GNT# () _LOK# () _INT# () _STSHG () _UIO () PROJET : ZR Quanta omputer Inc. Size ocument Number Rev ENE /0 Wednesday, October, 00 ate: Sheet of

19 XLE/ST S_SW XT0/ST S_SW S_SW S# R0 0_ R 0_ V XT/ST0 XT/MST XT/MST XT/ST XT/MST XT/MST0 XT/MSS XT0/ST XWP# XWE#/SLK XLE/SM XLE/ST XE# XRE#/MSLK XSY# X# Q *N00 R *0K_ Q *N00 () () V_RV MSINX# S# XT/MSS XT/MST XT/MST0 XT/MST MSINX# XT/MST XRE#/MSLK XLE/ST_SW XT/ST XLE/SM XWE#/SLK XT/ST0 XT0/ST_SW S# SWP V_RV / dd the Switch For MS Pro issue Fixed. Q *N N ()X-V ()X- ()X- ()X- ()X- ()X- ()X- ()X- (0)X-0 ()X-GN ()X-WP ()X-WE ()X-LE ()X-LE ()X-E ()X-RE ()X-R/ ()X- ()X-GN S-WP X-V X- X- X- X- X- X- X- X-0 X-GN X-WP X-WE X-LE X-LE X-E X-RE X-R/ X- X-GN GN 0 0 N ()MS-GN ()MS-S ()MS-T ()MS-T0 ()MS-T ()MS-INS ()MS-T ()MS-SLK ()MS-V (0)MS-GN ()S-T ()S-T ()S-M ()S-GN ()S-V ()S-LK ()S-GN ()S-T0 ()S-T S- S--OM SIO-GN X-V X- S-T X- MS-GN S-T0 X- X- T-ST-TOPview 0 S-/WP-OM S-T S-T0 S-GN S-LK S-V S-GN S-M S-T S-T MS-S S-GN X- MS-T X- S-LK MS-T0 X- MS-T S-V 0 X-0 X-GN S# 0 MS-INS S-GN X-WP S- MS-GN MS-S MS-T MS-T0 MS-T MS-INS MS-T MS-SLK MS-V MS-GN MS-T X-WE MS-SLK S-M X-LE MS-V X-LE S-T 0 MS-GN X-E S-T X-RE X-R/ X- X-GN ()X- ()X-GN ()X-R/ ()X-RE ()X-E ()X-LE ()X-LE 0 ()X-WE ()X-WP ()X-GN (0)X-0 ()X- ()X- ()X- ()X- ()X- ()X- 0 ()X- ()X-V S-WP S-WP-OM SIO-GN *R@TI TWUN R REER 0 ()S-T ()S-T0 (0)MS-GN ()S-GN ()MS-S ()S-LK ()MS-T ()MS-T0 ()S-V 0 ()MS-T ()MS-INS ()S-GN ()MS-T ()S-M ()MS-SLK ()MS-V ()S-T ()MS-GN ()S-T V_RV V_RV X# XSY# XRE#/MSLK XE# XLE/ST XLE/SM XWE#/SLK XWP# XT0/ST XT/MSS XT/MST0 XT/MST XT/ST XT/MST XT/MST XT/ST0 SWP XT0/ST_SW XT/ST0 XT/MSS XWE#/SLK XT/MST XT/MST0 XT/MST MSINX# XT/MST XLE/SM XRE#/MSLK XT/ST XLE/ST_SW X# () XSY# () XRE#/MSLK () XE# () XLE/ST () XLE/SM () XWE#/SLK () XWP# () XT0/ST () XT/MSS () XT/MST0 () XT/MST () XT/ST () XT/MST () XT/MST () XT/ST0 () SWP () () _0 () _ () _ () _ () _ () _/E0# () _ () _ () _ () _ () _/E# () _PR () _PERR# () _GNT# () _INT# () _LK () _IRY# () _/E# () _ () _0 () _ () _ () _ () _ () _ () _ () _ () _ () _RSV/ () _LKRUN# () _# () _ () _ () _ () _RSV/ () _ () _0 () _VS# () _ () _ () _ () _RSV/ () _LOK# () _STOP# () _EVSEL# () _TRY# () _FRME# () _ () _ () _VS# () _RST# () _SERR# () _REQ# () _/E# () _UIO () _STSHG () _ () _0 () _ () _# _0 _/E0# _/E# _PR _PERR# _GNT# _INT# _LK _IRY# _/E# 0 _RSV/ _LKRUN# _# RSV/ 0 _VS# RSV/ _LOK# _STOP# _EVSEL# _TRY# _FRME# _VS# _RST# _SERR# _REQ# _/E# _UIO _STSHG 0 # V R K V N VPP GN SKT/V SKT0/ SKT/V SKT/ SKT/ SKT/VPP SKT/ SKT/VPP SKT/ -SKTE0/E# SKT/0 SKT/OE# GN 0 0 SKT/ GN SKT/ GN -SKTE/ GN SKTPR/ GN -SKTPERR/ GN0 -SKTGNT/WE# -SKTINT/RY UPPER PIN SKTPLK/ 0 -SKTIRY/ -SKTE/ SKT/ SKT0/ SKT/ SKT/ SKT/ SKT/ SKT/ SKT/0 0 SKT/0 SKT/ SKTRSV/ -SKTLKRUN/WP GN GN -SKT/# SKT/ SKT/ SKT/ 0 SKTRSV/ SKT/ SKT0/E# -SKTVS/VS# SKT/IOR# SKT/IOWR# SKT/ -SKTRSV/ -SKTLOK/ -SKTSTOP/0 0 -SKTEVSEL/ LOWER PIN -SKTTRY/ -SKTFRME/ SKT/ SKT/ -SKTVSVS# -SKTRST/RESET 0SKTSERR/WIT# 0 -SKTREQ/INPK# -SKTE/REG# SKTUIO/V -SKTSTSHG/V SKT/ SKT0/ SKT/0 -SKT/# GN PMI_SOKET GN PRO-ST-TOPview PROONN R REER V V V_RV V_RV N SWP S# 0 V_RV () XPWREN#MSPWREN# () SPWREN# XPWREN#MSPWREN# SPWREN# R 0_ R 0_ R00 K_ Q GN OUT IN OUT IN OUT EN# OUTN GPU.U_ GN S-WP S- XT/ST0 XT/MST XT/MST XT/ST XT/MST XT/MST0 XT/MSS XT0/ST XWP# XWE#/SLK XLE/SM XLE/ST XE# XRE#/MSLK XSY# X# X-V X- X- ()X-V X- ()X- ()X- X- 0 ()X- ()X- X- ()X- X- ()X- ()X- X- (0)X-0 X-0 ()X-GN ()X-WP X-GN ()X-WE ()X-LE X-WP 0 ()X-LE X-WE ()X-E ()X-RE X-LE ()X-R/ ()X- X-LE ()X-GN X-E X-RE X-R/ X- X-GN 0 S-T S-T0 S-GN S-LK S-V S-GN S-M S-T S-T MS-GN MS-S MS-T MS-T0 MS-T MS-INS MS-T MS-SLK MS-V MS-GN 0 ()S-T ()S-T0 (0)MS-GN ()S-GN ()MS-S ()S-LK ()MS-T ()MS-T0 ()S-V 0 ()MS-T ()MS-INS ()S-GN ()MS-T ()S-M ()MS-SLK ()MS-V ()S-T ()MS-GN ()S-T XT0/ST_SW XT/ST0 XT/MSS XWE#/SLK XT/MST XT/MST0 XT/MST MSINX# XT/MST XLE/SM XRE#/MSLK XT/ST XLE/ST_SW V_RV.U_.U_.U_.U_ 0U/V_ /0 dd capacitor tolerance for worst environment. XE# XWE#/SLK XSY# XRE#/MSLK XLE/SM XLE/ST XT0/ST XT/ST XT/ST0 XWP# R R R R R R0 R R R R V_RV.K_ 0K_ 0K_ 0K_ *K_ *K_ *K_ *K_ *K_.K_ MP GN NorthStar-ST-TOPview *NS R REER_N PROJET : ZR Quanta omputer Inc. Size ocument Number Rev R RE & RUS SLOT ate: Wednesday, October, 00 Sheet of