PF1/2/PF1Q BLOCK DIAGRAM

Transcription

1 VI PG MXM Module PG 0 RII-SOIMM PG, RII-SOIMM PG, LVS ST - H RT PG PG ST - H ST - O LVS PG PG PG R II MHZ HMI PG ST0 ST ST PF//PFQ LOK IGRM LVS(ch) PI-E X HT_LINK M Sg Griffin Processor ( Sg socket) PG,,, RX/RS0M mm X mm, pin G _LINK (X) S00 PG 0,,, PU_LK NGFX_LK NGPP_LK SLINK_LK PI-E, X (port) PI-E, X (port0) US.0 (P) PI-E, X (port) US.0 (P) PI-E, X (port) US.0 (P0) PI-E, X (port) SSR_LK US.0 (P) US.0 (P) RTL0EL(0/00) PG Mini ard (WLN) Mini ard (TV) NEW R LOK GENERTOR JM0 PG ISLPRSKLFT SLGSPVTR luetooth RJ PG PG PG PG PG PG PG HOST 00MHz PIE 00MHz US MHz REF MHz US.0 (P) US.0 (P0) US.0 (P) US.0 (P) ard Reader IN PG IEEE N. PG US.0 I/O Ports X (M) PG US.0 I/O Ports X () PG US.0 I/O Ports X () PG US.0 I/O Ports X () PG P STK UP LYER : TOP LYER : GN LYER : IN LYER : IN LYER : V LYER : OT aughter oard MM oard US oard Touch Pad board Switch board PU_ORE PU_ORE PU VN_ORE PU ORE N_ORE N ORE (.0~.V) RV. V. RV. 0 E - ST PG ST mm X mm, pin G E IT.W(Ext).W(Int) LP zalia PG,,,, PG Flash PG PORT- H.P/ JK PG zalia udio odec L/L PORT- MI JK PG INT. MI PG PG Speaker mplifier G PG INT. S.P. PG WOOFER PG.VSUS V. SMR_VTERM V..V_N VPU RV VSUS V VPU VSUS V V..VSUS SMR VTERM V/V FN PG Keyboard PG SPI Flash Touch ROM Pad PG PG IR PG PROJET : PF Quanta omputer Inc. Size ocument Number Rev LOK IGRM Wednesday, June, 00 ate: Sheet of 0

2 PF Power On Sequence OM naming rule 0 From,attery VPU VPU From PWM SYS_HWPG(PU) From Power utton NSWON# From E RV_ON RV From E From E From S From S to E From E From PWM From E From PWM From E From PWM From E From S From S From S From S RV RV. >0ms RSMRST# >00ms NSWON# PIE_WKE# SUS#,SUS# SUSON SUSON VSUS.VSUS SMR_VREF SMR_VTERM HWPG_.V (SUS) MINON MINON V V V. V. V. N_ORE.V_N HWPG_.V,HWPG_.V,GFXPG(MIN) HWPG_._N VRON PU_ORE0, PU_ORE, PU VN_ORE, V. VRM_PWRG (PU) HWPG EPWROK S_PWRG N_PWRG PU_PWRG/LT_PG PLTRST# PIRST# PU_LT_RST# PU_LT_STOP# 0ns~0ns ms~0ms Items Function TO Name escription UM v IV@ Internal VG stuff iscrete VG v EV@ External VG stuff Subwoofer v WF@ Only for PFP IEEE v EV@ External VG model stuff VI-I -SU(RT) v v EV@ IV@ External VG model stuff Internal VG model stuff HMI v EV@ External VG model stuff IR v IR@ For PFP and PFP(M) TV TV@ For PFP and PFP(M) 0 0 S00 ST0/SLK0(V) S00 ST/SLK(V_S) S00 ST/SLK(V_S) Power Reserve MOS ckt *Note: E will sampling SUS# & SUS# every ms. M S00 SMUS Table LK GEN RM Mini ard (TV) Mini-card(WL) New ard HMI V V V V V V V V V V(theros) V RV V V V V V V E ST/SLK(VPU) E ST/SLK(VPU) E ST/SLK(VPU) E ST/SLK(VPU) Power Reserve MOS ckt E SMUS Table attery PU thermal Sensor E EEPROM VG thermal Sensor Touch Sensor HMI E V V V V V V VPU V VPU V VPU VPU X V X V X V PROJET : PF Quanta omputer Inc. Size ocument Number Rev SYSTEM INFORMTION Wednesday, June, 00 ate: Sheet of 0

3 LK_GEN_SLGSP 0 V LK_V V. LK_VIO L L0 K0HS00 U/.V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0.u/0V_ K0HS00 U/.V_ 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ ISLPRS0 SLGSP RTM0N- U P/N : LPRS0000 P/N : LSP000 P/N : L lock chip has internal serial terminations for differencial pairs, external resistors are reserved for debug purpose. Place within 0." of LKGEN R 0/ modify it V LK_V_US L K0HS00 0.U/.V_ LK_V 0 VOT VSR VTIG VS_SR VST VPU VHTT VREF V PUK_0T 0 PUK_0 TIG0T 0 TIG0 TIGT TIG PULKP_R PULKN_R NGFX_LKP_R NGFX_LKN_R MXM_REFLKP_R MXM_REFLKN_R RP RP0 RP 0X 0X EV@0X */F_ NGFX_LKP NGFX_LKN MXM_REFLKP MXM_REFLKN PULKP PULKN MXM_REFLKP (0) MXM_REFLKN (0) PULKP () PULKN () NGFX_LKP () NGFX_LKN () To PU RS0/RX for VG To N LKREQ# LKREQ# R *0K_ R0 *0K_ V Q *RHU00N0 V Q *RHU00N0 LKREQ_LN# () LKREQ_WLN# () LK_VIO G_XIN G_XOUT 0 0 VSR_IO0 VSR_IO VTIG_IO VS_SR_IO VPU_IO GN GNOT GNSR0 GNSR GNTIG GNS_SR GNST GNPU GNHTT GNREF X X QFN S_SR0T S_SR0 S_SRT S_SR SR0T SR0 SRT 0 SR SRT SR SRT SR SRT SR SRT/STT SR/ST SRT/M_SS SR/M_NS SLINK_LKP_R RP SLINK_LKN_R SSR_LKP_R RP SSR_LKN_R NGPP_LKP_R RP NGPP_LKN_R LK_PIE_NEW_R RP LK_PIE_NEW#_R LK_PIE_MINI_R RP LK_PIE_MINI#_R LK_PIE_MINI_R RP LK_PIE_MINI#_R LK_PIE_LN_R RP LK_PIE_LN#_R LK_PIE_JM0_R RP LK_PIE_JM0#_R T T 0X 0X 0X 0X 0X 0X 0X SLINK_LKP SLINK_LKP () SLINK_LKN To N SLINK_LKN () SSR_LKP SSR_LKP () SSR_LKN To S SSR_LKN () EV@0X NGPP_LKP NGPP_LKP () NGPP_LKN NGPP_LKN () LK_PIE_NEW LK_PIE_NEW () LK_PIE_NEW# To New ard LK_PIE_NEW# () LK_PIE_WLN LK_PIE_WLN () LK_PIE_WLN# To Mini PIE Slot LK_PIE_WLN# () LK_PIE_MINIR LK_PIE_MINIR () LK_PIE_MINIR# To Mini PIE Slot LK_PIE_MINIR# () LK_PIE_LN LK_PIE_LN () LK_PIE_LN# To LN ontroller LK_PIE_LN# () LK_PIE_JM0 LK_PIE_JM0 () LK_PIE_JM0# To in ontroller LK_PIE_JM0# () RX only To N / check RX :(0/) dd WLN & LN LKREQ circuit (OI request) (,,,) PLK_SM (,,,) PT_SM SMLK SMT HTT0T/M HTT0/M NHT_REFLKP_R RP0 NHT_REFLKN_R 0X NHT_REFLKP NHT_REFLKN NHT_REFLKP () NHT_REFLKN () To N LK_P# P# MHz_0 LK_M_US_R R0 _ LK_M_US LK_M_US () To S LK_V R0 R.K_.K_ NEW_LKREQ# LK_P# New ard LKREQ# () NEW_LKREQ# 0P 0P T NEW_LKREQ# LKREQ# T LKREQ# G_XIN Y.MHZ/0P G_XOUT LKREQ0# LKREQ# LKREQ# LKREQ# LKREQ# SLGSP TGN0 TGN TGN TGN TGN 0 TGN TGN TGN TGN TGN REF0/SEL_HTT REF/SEL_ST REF/SEL_ SEL_HTT SEL_ST Ra SEL_ R R Rb 0 *0P_ *0P_ Ra 0/ dd 0p for EMI issue (Suggestion by Seligo) Rb /F_ 0./F_ RX0.V.R 0R EXT_N_OS RS0.V R 0.R EXT_N_OS () To N N LOK INPUT TLE N LOKS RX HT_REFLKP 00M IFF HT_REFLKN 00M IFF REFLK_P M SE (.V) REFLK_N N GFX_REFLK 00M IFF RS0 00M IFF 00M IFF M SE (.V) vref 00M IFF(IN/OUT)* RES HIP 0 /W +-%(00)L-F -->S0F RES HIP /W +-%(00) -->SF00 RES HIP 0. /W +-%(00) -->S00F RES HIP. /W +-%(00) -->S0F GPP_REFLK GPPS_REFLK 00M IFF 00M IFF N or 00M IFF OUTPUT 00M IFF LOKS name RX RS0 lock pin function LK_V NGFX_LKP NGFX_LKN MXM_REFLKP MXM_REFLKN NGPP_LKP NGPP_LKN RP0 STUFF RP STUFF RP STUFF RP0 STUFF RP N RP N SLINK_LKP SLINK_LKN RP STUFF RP STUFF to N for VG reference clock to M-S external reference clock -RX0 only to N for RX0 for PIEX interface reference clock only RS0 is internal share with -LINK clock,rs0 not need to N for -LINK reference clock R *.K_ R0.K_ / modify R.K_ SEL_ST SEL_HTT SEL_ R.K_ SEL_HTT SEL_ST SEL_ MHz.V single ended HTT clock 0* 00 MHz differential HTT clock * 00 MHz non-spreading differential SR clock 0 0* * default 00 MHz spreading differential SR clock MHz and M SS outputs 00 MHz SR clock PROJET : PF Quanta omputer Inc. Size ocument Number Rev LOK GENERTOR_SLGSP ate: Wednesday, June, 00 Sheet of 0

4 V. R 0_ R 0_ () HT_N_PU H[..0] () HT_N_PU L[..0] () HT_N_PU_LK_H[..0] () HT_N_PU_LK_L[..0] () HT_N_PU_TL_H[..0] () HT_N_PU_TL_L[..0] () HT_PU_N H[..0] () HT_PU_N L[..0] () HT_PU_N_LK_H[..0] () HT_PU_N_LK_L[..0] () HT_PU_N_TL_H[..0] () HT_PU_N_TL_L[..0] +.V_VLT +.V_VLT HT_N_PU H[..0] HT_N_PU L[..0] HT_N_PU_LK_H[..0] HT_N_PU_LK_L[..0] HT_N_PU_TL_H[..0] HT_N_PU_TL_L[..0] HT_PU_N H[..0] HT_PU_N L[..0] HT_PU_N_LK_H[..0] HT_PU_N_LK_L[..0] HT_PU_N_TL_H[..0] HT_PU_N_TL_L[..0] V..U/.V_.U/.V_ 0.U/.V_ 0P/0V_ FOX PZ-R-F G0^00000 I SOKET SM P S(P.,H.) MLX - G0^00000 I SOKET SM P S(P.,H.) TY -00- G0^00000 I SOKET SM P S(P.,H.) LMPGSN(0,00M,)_ L LS00-00M-N 0U/.V_ +.V_VLT +.V_VLT +.V_VLT +.V_VLT HT_N_PU H0 E HT_N_PU L0 E HT_N_PU H E HT_N_PU L F HT_N_PU H G HT_N_PU L G HT_N_PU H G HT_N_PU L H HT_N_PU H J HT_N_PU L K HT_N_PU H L HT_N_PU L L HT_N_PU H L HT_N_PU L M HT_N_PU H N HT_N_PU L N HT_N_PU H E HT_N_PU L F HT_N_PU H F HT_N_PU L F HT_N_PU H0 G HT_N_PU L0 H HT_N_PU H H HT_N_PU L H HT_N_PU H K HT_N_PU L K HT_N_PU H L HT_N_PU L M HT_N_PU H M HT_N_PU L M HT_N_PU H N HT_N_PU L P HT_N_PU_LK_H0 HT_N_PU_LK_L0 HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_TL_H0 HT_N_PU_TL_L0 HT_N_PU_TL_H HT_N_PU_TL_L U VLT_0 VLT_ VLT_ VLT_ L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L J L0_LKIN_H0 J L0_LKIN_L0 J L0_LKIN_H K L0_LKIN_L N L0_TLIN_H0 P L0_TLIN_L0 P L0_TLIN_H P L0_TLIN_L SOKET PIN HT LINK +PUV W/S= mil/0mil.u/.v_ 0.U/.V_ VLT_0 E VLT_ E VLT_ E VLT_ E L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H W L0_OUT_L W L0_OUT_H V L0_OUT_L U L0_OUT_H U L0_OUT_L U L0_OUT_H T L0_OUT_L R L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H Y L0_OUT_L W L0_OUT_H V L0_OUT_L V L0_OUT_H V L0_OUT_L U L0_OUT_H T L0_OUT_L T L0_LKOUT_H0 Y L0_LKOUT_L0 W L0_LKOUT_H Y L0_LKOUT_L Y L0_TLOUT_H0 R L0_TLOUT_L0 R L0_TLOUT_H T L0_TLOUT_L R 00P/0V_ +.V_VLT.U/.V_ +.V_VLT 0.U/.V_ +.V_VLT 0P/0V_ +.V_VLT HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N_LK_H0 HT_PU_N_LK_L0 HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_TL_H0 HT_PU_N_TL_L0 HT_PU_N_TL_H HT_PU_N_TL_L () () PU_PWRG PUTEST PUTEST PUTEST PUTEST PUTEST PUTEST PUTEST0 PUTEST PUTEST PUTEST PU LK PULKP PULKN PULKIN PULKP PULKN PULKP PULKN Keep trace from resisor to PU within 0." keep trace from caps to PU within." R PULKIN# (,) PU_LT_RST# () PU_PWRG (,) PU_LT_STOP# () PU_SI Sideand Temp sense I () PU_SI () PU_LERT 0.U/0V_.VSUS.VSUS / R for P REV:F refer M PU design guide +.V_VLT / M suggest, closed to PU R 00_ R *00_ R *00_ R0 *00_ R *00_ R *00_ R 00_ R 00_ R *00_ R 00_ /F_ 00P/V_ 00P/V_ / R,R for P REV:F refer M PU design guide R R () PU_V0_F_H () PU_V0_F_L () PU_V_F_H () PU_V_F_L PU_RY PU_TMS PU_TK PU_TRST# PU_TI +PUV W/S= mil/0mil +PUV +PUV PULKIN PULKIN# PU_LT_RST# PU_PWRG PU_LT_STOP# PU_LT_REQ#_PU PU_SI PU_SI PU_LERT PU_THERM PU_THERM PU_LT_RST# PU_PWRG PU_LT_REQ#_PU./F_ PU_HTREF0./F_ PU_HTREF place them to PU within." T R 0_ PUTEST F V F V LKIN_H LKIN_L F V0_F_H E V0_F_L R 0_ R 0_ 00_ R 00_ R 00_ R RESET_L PWROK F0 LTSTOP_L THERMTRIP_L LTREQ_L PROHOT_L MEMHOT_L F SI F SI E LERT_L THERM THERM R HT_REF0 P HT_REF Y V_F_H V_F_L G0 RY TMS TK TRST_L F TI U TEST PUTEST T H0 PUTEST TEST T G R 00_ TEST R *00_ PUTESTH E R *00_ PUTESTL TEST_H E R 00_ TEST_L PUTEST T PUTEST0 TEST T F.VSUS PUTEST TEST0 T E PUTEST TEST T E R PUTEST TEST T *00_ PUTEST TEST F TEST TEST TEST RSV RSV RSV RSV RSV SOKET PIN KEY KEY SV SV VIO_F_H VIO_F_L VN_F_H VN_F_L REQ_L TO TEST_H TEST_L TEST TEST TEST TEST TEST TEST0 TEST TEST_H TEST_L RSV0 RSV RSV RSV RSV M W F W W W Y H G H_THERM () H_THERM () V. PU_SV_R PU_SV_R PU_THERMTRIP_L# PU_PROHOT_L# PU_MEMHOT_L# PU_THERM PU_THERM VIO_F_H VIO_F_L E0 PU_REQ# E PU_TO J H E F K H H PUTESTH PUTESTL PUTEST PUTEST PUTEST PUTEST PUTESTH PUTESTL 0 VIO_F_H () VIO_F_L () PU_VN_F_H () PU_VN_F_L () T T T T T T0 T T V R 0K/F_ NTR_VREF 0 0.U/0V_ R.K/F_ NTR_VREF () V Serial VI VFIX MOE VI Override ircuit Q PU_LT_REQ#_PU R 0_ *SS_NL/SOT NTR_VREF PU_LT_RST# PU_LT_REQ# () R 0_ R K/F_ PU_LT_RST_HTP# Q SS_NL/SOT.VSUS PU_SV_R PU_SV_R PU_PWRG R R R *.K_ K/F_ K/F_ R 0_ R 0_ R0 0_ R *0_ R *0_ R *0_ PU_SV PU_SV PU_PWRG_SVI_REG PU_SV () PU_SV () PU_PWRG_SVI_REG () SV SV Voltage Output 0 0.V 0.V 0.0V 0.V.VSUS.VSUS R PU_MEMHOT_L# 0K/F_ R 00_ Q MMT0 PU_MEMHOT# PU_MEMHOT# (,) HT onnector.vsus.vsus.vsus.vsus R R0 00_ PU_PROHOT_L# *0K/F_ Q *MMT0 R 0_ PU_PROHOT# ().VSUS.VSUS R R 00_ PU_THERMTRIP_L# 0K/F_ Q MMT0 PU_THERMTRIP# () R0 00_ PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO *0.U/0V_ 0 0 KEY N *HT ONN PU_LT_RST_HTP# PROJET : PF Quanta omputer Inc. Size ocument Number Rev SG HT,TL I/F / ate: Wednesday, June, 00 Sheet of 0

5 E E M_ZN M_ZP MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_T PU_VTT_SENSE MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_RESET# MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M0 MEM_M_M MEM_M_OT0 MEM_M_OT0 MEM_M_OT MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M0 MEM_M_RESET# MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T PU_M_S_L0 PU_M_S_L PU_M_LK_L PU_M_LK_H PU_M_LK_H PU_M_LK_L PU_M_LK_H PU_M_LK_HL PU_M_LK_L PU_M_LK_H MEMVREF_PU MEM_M_LK_P MEM_M_LK_P MEM_M_LK_N MEM_M_LK_P MEM_M_LK_N MEM_M_LK_P MEM_M_LK_N MEM_M_LK_N MEM_M_[0..] (,) MEM_M0_OT0 (,) MEM_M0_OT (,) MEM_M0_S#0 (,) MEM_M0_S# (,) MEM_M_KE0 (,) MEM_M_KE (,) MEM_M_LK_P () MEM_M_LK_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_NK0 (,) MEM_M_NK (,) MEM_M_NK (,) MEM_M_RS# (,) MEM_M_S# (,) MEM_M_WE# (,) MEM_M_NK0 (,) MEM_M_NK (,) MEM_M_NK (,) MEM_M_RS# (,) MEM_M_S# (,) MEM_M_WE# (,) MEM_M_LK_P () MEM_M_LK_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_KE0 (,) MEM_M_KE (,) MEM_M0_S#0 (,) MEM_M0_S# (,) MEM_M0_OT0 (,) MEM_M0_OT (,) MEM_M_[0..] (,) MEM_M_T[0..] () MEM_M_M[0..] () MEM_M_QS0_P () MEM_M_QS0_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS0_P () MEM_M_QS0_N () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_M[0..] () MEM_M_T[0..] () PU_VTT_SENSE () SMR_VREF (,) SMR_VTERM SMR_VTERM.VSUS SMR_VTERM SMR_VTERM.VSUS Size ocument Number Rev ate: Sheet of SG RII MEMORY I/F / 0 Wednesday, June, 00 Size ocument Number Rev ate: Sheet of SG RII MEMORY I/F / 0 Wednesday, June, 00 Size ocument Number Rev ate: Sheet of SG RII MEMORY I/F / 0 Wednesday, June, 00 PLE THEM LOSE TO PU WITHIN " Processor Memory Interface Place close to socket 0 lose to PU within 00 mils 0 m T T T T 000P/0V_ 000P/0V_ T T 0 0P/0V_ 0 0P/0V_ T T 0P/0V_ 0P/0V_.U/.V_.U/.V_ 000P/0V_ 000P/0V_ R./F_ R./F_ T T 0P/0V_ 0P/0V_ 0.U/0V_ 0.U/0V_ T0 T0.P/0V_.P/0V_ R *0_ R *0_ 0.U/.V_ 0.U/.V_ 0 0.U/.V_ 0 0.U/.V_ 0.U/0V_ 0.U/0V_.U/.V_.U/.V_ 0.U/0V_ 0.U/0V_ R./F_ R./F_ T T 0.U/.V_ 0.U/.V_.P/0V_.P/0V_ 000P/0V_ 000P/0V_ T T.P/0V_.P/0V_ T0 T0 0.U/.V_ 0.U/.V_ R K/F_ R K/F_ T T VTT 0 VTT 0 VTT 0 VTT 0 VTT W0 VTT 0 VTT 0 VTT 0 VTT 0 M_OT V M_OT0 U M0_OT V M0_OT0 T M_OT0 Y M0_OT W M0_OT0 W RSV_M M_S_L0 U M0_S_L W M0_S_L0 V M0_S_L U M_S_L V0 M_S_L0 U0 M0_S_L0 T0 M_ K M_ K M_ V M_ K0 M_ L M_0 R M_ K M_ L M_ L M_ M M_ L0 M_ M M_ M M_ N M_ M0 M_0 N M_NK J M_NK R M_NK0 R0 M_RS_L R M_S_L T M_WE_L T MEMZP F0 MEMZN E0 VTT_SENSE Y0 MEMVREF W M_LK_H P M_LK_L P0 M_LK_H Y M_LK_L M_LK_H E M_LK_L F M_LK_H N M_LK_L N0 M_LK_H R M_LK_L R M_LK_H F M_LK_L F M_LK_H M_LK_L M_LK_H P M_LK_L R M_KE0 J M_KE J0 M_KE0 J M_KE H M_ J M_ J M_ W M_ L M_ L M_0 T M_ K M_ M M_ L M_ N M_ L M_ N M_ N M_ P M_ N M_0 P M_NK J M_NK U M_NK0 R M_RS_L U M_S_L U M_WE_L U RSV_M H MEM:M/TRL/LK U SOKET PIN MEM:M/TRL/LK U SOKET PIN 0 0P/0V_ 0 0P/0V_ R K/F_ R K/F_ 0.U/.V_ 0.U/.V_ M_T M_T F M_T F M_T0 E M_T Y M_T M_T M_T F M_T F M_T F M_T M_T F M_T M_T0 M_T E M_T M_T 0 M_T 0 M_T F M_T F M_T F0 M_T E0 M_T M_T0 M_T E M_T M_T M_T M_T E M_T M_T M_T M_T G M_T0 G M_T M_T M_T G M_T G M_T E M_T E M_T M_T M_T 0 M_T0 0 M_T M_T M_T M_T 0 M_T M_T M_T M_T M_T 0 M_T0 M_T M_T M_T M_T M_T E M_T G M_T M_T M_T M_T0 M_T M_T M_T M_T0 M_T W M_T Y M_T M_T M_T M_T M_T M_T Y M_T Y M_T0 W M_T W M_T M_T Y M_T M_T M_T M_T M_T M_T 0 M_T0 Y0 M_T M_T Y M_T W M_T W M_T M_T M_T M_T Y M_T H M_T0 H0 M_T E M_T E M_T J M_T H M_T F M_T F0 M_T M_T M_T F M_T0 E M_T E0 M_T M_T M_T G M_T G M_T M_T F M_T E M_T H M_T0 E M_T E M_T H M_T E M_T M_T H M_T H M_T G M_T H M_T F M_T0 G M_M M_M M_M E M_M M_M E M_M M_M M_M0 M_QS_H F M_QS_L E M_QS_H E M_QS_L M_QS_H F M_QS_L F M_QS_H M_QS_L M_QS_H F M_QS_L E M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H0 M_QS_L0 M_M Y M_M M_M Y M_M M_M F M_M E M_M M_M0 E M_QS_H W M_QS_L W M_QS_H Y M_QS_L W M_QS_H M_QS_L 0 M_QS_H M_QS_L M_QS_H G M_QS_L G M_QS_H M_QS_L M_QS_H G M_QS_L G M_QS_H0 G M_QS_L0 H MEM:T U SOKET PIN MEM:T U SOKET PIN Quanta omputer Inc. PROJET : PF Quanta omputer Inc. PROJET : PF 0.U/.V_ 0.U/.V_ T T T T 000P/0V_ 000P/0V_ T T T T.P/0V_.P/0V_ T T T T 000P/0V_ 000P/0V_

6 PU_SI THERM_LERT# PU_SI MT MLK PU_LERT THER_SH# THER_SH# LMV H_THERM H_THERM PU_SI () PU_SI () PU_LERT () NTR_VREF () MT (0,,) MLK (0,,) SYS_SHN# () MLK (0,,) THERM_LERT# (,) MT (0,,) H_THERM () H_THERM ().VSUS.VSUS.VSUS.VSUS.VSUS PU VN_ORE PU_ORE PU_ORE0 PU_ORE0 PU_ORE PU VN_ORE.VSUS V V V V V V PU_ORE0 PU_ORE Size ocument Number Rev ate: Sheet of SG PWR & GN / 0 Wednesday, June, 00 Size ocument Number Rev ate: Sheet of SG PWR & GN / 0 Wednesday, June, 00 Size ocument Number Rev ate: Sheet of SG PWR & GN / 0 Wednesday, June, 00 OTTOM SIE EOUPLING PROESSOR POWER N GROUN EOUPLING ETWEEN PROESSOR N IMMs PLE LOSE TO PROESSOR S POSSILE 0 RESS: H U/.V_ U/.V_ 0.0U/V_ 0.0U/V_ 0.U/.V_ 0.U/.V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0P/0V_ 0P/0V_ R *0_ R *0_ 0 U/.V_ 0 U/.V_ R 0K_ R 0K_ 0.U/.V_ 0.U/.V_ U/.V_ U/.V_.U/.V_.U/.V_ U/.V_ U/.V_ Quanta omputer Inc. PROJET : PF Quanta omputer Inc. PROJET : PF 0.U/.V_ 0.U/.V_ U/.V_ U/.V_ 0 0.0U/V_ 0 0.0U/V_ 0P/0V_ 0P/0V_ 0.U/.V_ 0.U/.V_ V XP XN -OVT GN -LT SMT SMLK U G MSOP-_- U G MSOP-_- 0.U/.V_ 0.U/.V_ R *.K_ R *.K_ 0 0.0U/V_ 0 0.0U/V_ 0.0U/V_ 0.0U/V_.U/.V_.U/.V_ V_ V_ V0_ G V0_ H V0_ J V0_ J V0_ J V0_ K V0_ K0 V0_ K V0_0 K V0_ L V0_ L V0_ L V0_ L V0_ L V0_ M V0_ M V0_ M V0_0 M0 V0_ N V0_ N V0_ N V_ P V_ P0 V_ R V_ R V_ R V_ R V_ T V_ T V_ T V_0 T0 V_ T V_ T V_ U V_ U V_ U V_ U V_ V V_ V V_0 V0 V_ V V_ V V_ W V_ Y V0_ J VN_ K V0_ L VN_ M VN_ P VN_ T V_ U VN_ V VIO H VIO J VIO K VIO K VIO K VIO K VIO L VIO M VIO M VIO0 M VIO M VIO N VIO P VIO P VIO P VIO P VIO R VIO T VIO T VIO0 T VIO T VIO U VIO V VIO V VIO V VIO V VIO Y UE SOKET PIN UE SOKET PIN R *K/F_ R *K/F_ 0.U/.V_ 0.U/.V_ Q RHU00N0 Q RHU00N0 0.0U/V_ 0.0U/V_ R 0_ R 0_ 0.0U/V_ 0.0U/V_ 0P/0V_ 0P/0V_ Q MMT0 Q MMT0 U/.V_ U/.V_ 0.0U/V_ 0.0U/V_ R 0_ R 0_ 0.u/0V_ 0.u/0V_ U/.V_ U/.V_.U/.V_.U/.V_ U/.V_ U/.V_ R 00_ R 00_ 0P/0V_ 0P/0V_ 0 U/.V_ 0 U/.V_ R0 0_ R0 0_ R *0_ R *0_ 0.U/.V_ 0.U/.V_ R0 0K_ R0 0K_ Q0 *SS_NL/SOT Q0 *SS_NL/SOT.U/.V_.U/.V_ R *0_ R *0_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS E VSS E VSS E VSS E VSS E VSS E VSS E VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS E VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS0 F VSS H VSS H VSS H VSS H VSS J VSS J VSS J VSS J0 VSS J VSS0 J VSS J VSS J VSS K VSS K VSS K VSS K VSS K VSS K VSS K VSS0 L VSS L VSS L0 VSS L VSS L VSS L VSS L VSS M VSS M VSS VSS0 M VSS N VSS N VSS N0 VSS N VSS N VSS P VSS P VSS P VSS P VSS00 P VSS0 R VSS0 R0 VSS0 R VSS0 R VSS0 T VSS0 T VSS0 T VSS0 T VSS0 T VSS0 T VSS U VSS U VSS U VSS U0 VSS U VSS U VSS U VSS U VSS V VSS0 V VSS V VSS V VSS V VSS V VSS V VSS W VSS Y VSS Y VSS N UF SOKET PIN UF SOKET PIN Q RHU00N0 Q RHU00N0 0P/0V_ 0P/0V_ R 0K_ R 0K_ U/.V_ U/.V_ 0.U/.V_ 0.U/.V_ U/.V_ U/.V_ 0 U/.V_ 0 U/.V_ 00p/0V_ 00p/0V_ U/.V_ U/.V_

7 MEM_M_N MEM_M_ MEM_M_ MEM_M_NK0 MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_NK MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_NK PT_SM PLK_SM MEM_M_T MEM_M_M MEM_M_M MEM_M_M0 MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEMHOT_SOIMM#_ MEM_M_ MEM_M_RESET# MEM_M_NK0 MEM_M_ MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_NK MEM_M_NK MEM_M_T MEM_M_N MEM_M_RESET# MEMHOT_SOIMM# PT_SM MEM_M_T PLK_SM MEMHOT_SOIMM#_ MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M0 MEM_M_M MEM_M_M MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ IM_S0 IM_S IM_S0 IM_S IM_S0 IM_S IM_S0 IM_S 0.VSMVREF_IMM PT_SM (,,,) PLK_SM (,,,) MEM_M_T[0..] () MEM_M_M[0..] () MEM_M_M[0..] () MEM_M_QS0_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS0_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_KE0 (,) MEM_M_KE (,) MEM_M_RS# (,) MEM_M_S# (,) MEM_M_WE# (,) MEM_M0_S#0 (,) MEM_M0_OT0 (,) MEM_M0_OT (,) MEM_M0_S# (,) MEM_M_NK[0..] (,) MEM_M_[0..] (,) MEMHOT_SOIMM# () MEM_M_QS_N () MEM_M_QS_N () MEM_M_KE0 (,) MEM_M_KE (,) MEM_M_QS_N () MEM_M_QS_N () MEM_M_RS# (,) MEM_M_S# (,) MEM_M_WE# (,) MEM_M0_S#0 (,) MEM_M0_OT0 (,) MEM_M0_OT (,) MEM_M_QS_P () MEM_M_QS_P () MEM_M0_S# (,) MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_LK_P () MEM_M_QS0_N () MEM_M_LK_N () MEM_M_QS0_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_NK[0..] (,) MEM_M_[0..] (,) MEM_M_T[0..] () SMR_VREF (,).VSUS.VSUS V 0.VSMVREF_IMM 0.VSMVREF_IMM V.VSUS V 0.VSMVREF_IMM Size ocument Number Rev ate: Sheet of R SOIMMS: / HNNEL 0 Wednesday, June, 00 Size ocument Number Rev ate: Sheet of R SOIMMS: / HNNEL 0 Wednesday, June, 00 Size ocument Number Rev ate: Sheet of R SOIMMS: / HNNEL 0 Wednesday, June, 00 o o SMbus address SMbus address 0 H=. H=. 0 Only for reserved R K/F_ R K/F_ Quanta omputer Inc. PROJET : PF Quanta omputer Inc. PROJET : PF 0 000P/0V_ 0 000P/0V_ 0.U/0V_ 0.U/0V_ T T.U/.V_.U/.V_ 0.U/0V_ 0.U/0V_ R0 0_ R0 0_ 000P/0V_ 000P/0V_ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 SO-IMM (REVERSE) N R SO-IMM SOKET.V SO-IMM (REVERSE) N R SO-IMM SOKET.V R 0K/F_ R 0K/F_ T T R 0K/F_ R 0K/F_ 0.U/0V_ 0.U/0V_ T T R *0_ R *0_ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 SO-IMM (REVERSE) N R SO-IMM SOKET.V SO-IMM (REVERSE) N R SO-IMM SOKET.V R 0_ R 0_.U/.V_.U/.V_ 0.U/0V_ 0.U/0V_ R 0K/F_ R 0K/F_ R K/F_ R K/F_ R 0K/F_ R 0K/F_ T T

8 (,) MEM_M_[0..] (,) MEM_M_NK[0..] MEM_M_[0..] MEM_M_NK[0..] (,) MEM_M_[0..] (,) MEM_M_NK[0..] MEM_M_[0..] MEM_M_NK[0..] 0 SMR_VTERM SMR_VTERM (,) MEM_M_KE0 (,) MEM_M_WE# (,) MEM_M_S# (,) MEM_M0_OT (,) MEM_M0_S# (,) MEM_M_KE (,) MEM_M0_S#0 (,) MEM_M_RS# (,) MEM_M0_OT0 MEM_M_KE0 RP MEM_M_NK MEM_M_ RP MEM_M_ MEM_M_ RP MEM_M_ MEM_M_ RP MEM_M_ MEM_M_0 RP0 MEM_M_NK0 MEM_M_WE# RP MEM_M_S# MEM_M0_OT RP MEM_M0_S# MEM_M_ RP MEM_M_KE MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_NK MEM_M_0 MEM_M0_S#0 MEM_M_RS# MEM_M_ MEM_M0_OT0 RP RP RP RP RP RP _PR PR PR PR PR PR PR PR PR PR PR PR PR PR_ U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS (,) MEM_M_KE0 (,) MEM_M_WE# (,) MEM_M_S# (,) MEM_M0_OT (,) MEM_M0_S# (,) MEM_M_KE (,) MEM_M0_S#0 (,) MEM_M_RS# (,) MEM_M0_OT0 MEM_M_KE0 MEM_M_NK MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_NK0 MEM_M_WE# MEM_M_S# MEM_M0_OT MEM_M0_S# MEM_M_KE MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_NK MEM_M_0 MEM_M0_S#0 MEM_M_RS# MEM_M0_OT0 MEM_M_ RP RP RP RP RP RP RP RP RP RP0 RP RP RP RP _PR PR PR PR PR PR PR PR PR PR PR PR PR PR_ U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS PLE LOSE TO PROESSOR WITHIN. INH PLE LOSE TO PROESSOR WITHIN. INH.VSUS.VSUS 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ PLE LOSE TO SOKET( PER EMI/EM) PLE LOSE TO SOKET( PER EMI/EM) V V R0 *0K/F_ lose R socket R *0K/F_ PU_MEMHOT# (,) U V R *_ (,,,) PT_SM (,,,) PLK_SM V PT_SM PLK_SM 0 +VS 0.U/0V_ MEMHOT_SOIMM# O.S Q0 S SL GN *N00E-G ddress:h *SU+T&R Q *N00E-G V R 0K/F_ MEMHOT_SOIMM# MEMHOT_SOIMM# () PROJET : PF Quanta omputer Inc. Size ocument Number Rev R SOIMMS TERMINTIONS ate: Wednesday, June, 00 Sheet of 0

9 R HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N_LK_H0 HT_PU_N_LK_L0 HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_TL_H0 HT_PU_N_TL_L0 HT_PU_N_TL_H HT_PU_N_TL_L R 00/F_ HT_RXLP HT_RXLN U Y HT_RX0P HT_TX0P Y HT_RX0N PRT OF HT_TX0N V HT_RXP HT_TXP V HT_RXN HT_TXN V HT_RXP HT_TXP V HT_RXN HT_TXN U HT_RXP HT_TXP U HT_RXN HT_TXN T HT_RXP HT_TXP T HT_RXN HT_TXN P HT_RXP HT_TXP P HT_RXN HT_TXN P HT_RXP HT_TXP P HT_RXN HT_TXN N HT_RXP HT_TXP N HT_RXN HT_TXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RX0P HT_RX0N Y HT_RXP Y HT_RXN W HT_RXP W0 HT_RXN V HT_RXP V0 HT_RXN U0 HT_RXP U HT_RXN U HT_RXP U HT_RXN T HT_RXLK0P T HT_RXLK0N HT_RXLKP HT_RXLKN M HT_RXTL0P M HT_RXTL0N R HT_RXTLP R0 HT_RXTLN HT_RXLP HT_RXLN RS0(RX0) HYPER TRNSPORT PU I/F HT_TXP HT_TXN HT_TXP HT_TXN HT_TX0P HT_TX0N HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXLK0P HT_TXLK0N HT_TXLKP HT_TXLKN HT_TXTL0P HT_TXTL0N HT_TXTLP HT_TXTLN HT_TXLP HT_TXLN E E F F F F H H J J K K K K F G G0 H J0 J J K L J M L M P P M H H L L0 M M P R HT_N_PU H0 HT_N_PU L0 HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H0 HT_N_PU L0 HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU_LK_H0 HT_N_PU_LK_L0 HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_TL_H0 HT_N_PU_TL_L0 HT_N_PU_TL_H HT_N_PU_TL_L HT_TXLP HT_TXLN R R 00/F_ HT_PU_N H[..0] HT_PU_N L[..0] HT_PU_N_LK_H[..0] HT_PU_N_LK_L[..0] HT_PU_N_TL_H[..0] HT_PU_N_TL_L[..0] HT_N_PU H[..0] HT_N_PU L[..0] HT_N_PU_LK_H[..0] HT_N_PU_LK_L[..0] HT_N_PU_TL_H[..0] HT_N_PU_TL_L[..0] HT_TXLP HT_TXLN HT_RXLP HT_RXLN HT_PU_N H[..0] () HT_PU_N L[..0] () HT_PU_N_LK_H[..0] () HT_PU_N_LK_L[..0] () HT_PU_N_TL_H[..0] () HT_PU_N_TL_L[..0] () HT_N_PU H[..0] () HT_N_PU L[..0] () HT_N_PU_LK_H[..0] () HT_N_PU_LK_L[..0] () HT_N_PU_TL_H[..0] () HT_N_PU_TL_L[..0] () signals RS0 RX R 00 ohm % R 00 ohm % R.k ohm % R.k ohm % 0 RES HIP.K /W +-%(00) P/N : SF RES HIP 00 /W +-%(00) P/N : S00F00 This block is for UM RS0 only, RX can remove all component U PR OF MEM_0(N) MEM_Q0/VO_VSYN(N) E MEM_(N) MEM_Q/VO_HSYN(N) V MEM_(N) MEM_Q/VO_E(N) E MEM_(N) MEM_Q/VO_0(N) MEM_(N) MEM_Q(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_0(N) MEM_Q0/VO_(N) E MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q(N) Y MEM_(N) MEM_Q/VO_(N) MEM_Q/VO_0(N) MEM_0(N) MEM_Q/VO_(N) E MEM_(N) MEM_(N) MEM_QS0P/VO_IKP(N) MEM_QS0N/VO_IKN(N) W MEM_RSb(N) MEM_QSP(N) Y MEM_Sb(N) MEM_QSN(N) MEM_WEb(N) MEM_Sb(N) MEM_M0(N) MEM_KE(N) MEM_M/VO_(N) V MEM_OT(N) IOPLLV(N) V MEM_KP(N) IOPLLV(N) W MEM_KN(N) IOPLLVSS(N) E MEM_OMPP(N) MEM_OMPN(N) MEM_VREF(N) RS0(RX0) S_MEM/VO_I/F 0 Y V Y 0 E 0 Y W 0 E W E E E E +._IOPLLV_N +.V_IOPLLV *.U/.V_ IOPLLV - memory PLL not applicable to RX0 R 0_ R 0_ 0 *.U/.V_ V..V_N IOPLLV- memory PLL not applicable to RX0 PROJET : PF Quanta omputer Inc. Size ocument Number Rev RS0/RS0-HT LINK I/F / ate: Wednesday, June, 00 Sheet of 0

10 () PIE_RXP0 () PIE_RXN0 () PIE_RXP () PIE_RXN () PIE_RXP () PIE_RXN () PIE_RXP () PIE_RXN () PIE_RXP () PIE_RXN () PIE_S_N_RX0P () PIE_S_N_RX0N () PIE_S_N_RXP () PIE_S_N_RXN () PIE_S_N_RXP () PIE_S_N_RXN () PIE_S_N_RXP () PIE_S_N_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP0 PEG_RXN0 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP0 PEG_RXN0 PIE_RXP0 PIE_RXN0 PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN U GFX_RX0P GFX_RX0N GFX_RXP GFX_RXN GFX_RXP GFX_RXN E GFX_RXP F GFX_RXN G GFX_RXP G GFX_RXN H GFX_RXP H GFX_RXN J GFX_RXP J GFX_RXN J GFX_RXP J GFX_RXN L GFX_RXP L GFX_RXN M GFX_RXP L GFX_RXN P GFX_RX0P M GFX_RX0N P GFX_RXP M GFX_RXN R GFX_RXP P GFX_RXN R GFX_RXP R GFX_RXN P GFX_RXP P GFX_RXN T GFX_RXP T GFX_RXN E GPP_RX0P GPP_RX0N E GPP_RXP GPP_RXN GPP_RXP GPP_RXN V GPP_RXP W GPP_RXN U GPP_RXP U GPP_RXN U GPP_RXP U GPP_RXN PRT OF PIE I/F GFX PIE I/F GPP GFX_TX0P GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TX0P GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GPP_TX0P GPP_TX0N GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN S_RX0P S_TX0P Y S_RX0N S_TX0N S_RXP S_TXP Y S_RXN S_TXN S_RXP PIE I/F S S_TXP S_RXN S_TXN W S_RXP S_TXP Y S_RXN S_TXN PE_LRP(PE_LRP) PE_LRN(PE_LRN) RS0(RX0) E E F F F F H H H H J J K K K K M M M M N N P P _PEG_TXP _PEG_TXN 0 _PEG_TXP _PEG_TXN _PEG_TXP 0 _PEG_TXN 0 _PEG_TXP _PEG_TXN _PEG_TXP 0 _PEG_TXN 0 _PEG_TXP0 _PEG_TXN0 _PEG_TXP 00 _PEG_TXN _PEG_TXP _PEG_TXN 0 _PEG_TXP 0 _PEG_TXN 0 _PEG_TXP _PEG_TXN _PEG_TXP 0 _PEG_TXN 0 _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP 0 _PEG_TXN _PEG_TXP0 _PEG_TXN0 PIE_TXP0_ PIE_TXN0_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ Y PIE_TXP_ 0 Y PIE_TXN_ Y PIE_TXP_ Y PIE_TXN_ V V E E E _TX0P TX0N TXP TXN TXP TXN TXP TXN_ N_PIELRP N_PIELRN EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ R.K/F_ R K/F_ PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP0 PEG_TXN0 PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP0 PEG_TXN0 PIE_TXP0 () PIE_TXN0 () PIE_TXP () PIE_TXN () PIE_TXP () PIE_TXN () PIE_TXP () PIE_TXN () PIE_TXP () PIE_TXN () PIE_N_S_TX0P () PIE_N_S_TX0N () PIE_N_S_TXP () PIE_N_S_TXN () PIE_N_S_TXP () PIE_N_S_TXN () PIE_N_S_TXP () PIE_N_S_TXN ().V_N (0) PEG_RXN[:0] (0) PEG_RXP[:0] TO WLN TO MINI R TO PIE-LN TO EPRESS R TO R REER PEG_RXN[:0] PEG_TXN[:0] PEG_TXN[:0] (0) PEG_RXP[:0] PEG_TXP[:0] PEG_TXP[:0] (0) 0 lose to North ridge lose to North ridge _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN TO lose to North ridge 0 HM@0.u/0V_ HM@0.u/0V_ HM@0.u/0V_ HM@0.u/0V_ HM@0.u/0V_ HM@0.u/0V_ HM@0.u/0V_ HM@0.u/0V_ IV_HMITXP () IV_HMITXN () IV_HMITXP () IV_HMITXN () IV_HMITX0P () IV_HMITX0N () IV_HMILK+ () IV_HMILK- () To HMI ONN RX0/RS0/RS0 difference table (PIE LINK) RS0 RX0/RS0 N_PIELRP R (GN).K (GN) RS0 isplay Port Support (muxed on GFX) GFX_TX0,TX,TX and TX P0 UX0 and HP0 GPP GPP N N GPP GPP P GFX_TX,TX,TX and TX UX and HP PROJET : PF Quanta omputer Inc. Size ocument Number Rev RS0/RS0-PIE I/F / ate: Wednesday, June, 00 Sheet 0 of 0

11 RX0: Powered from the.-v rail and driven by S00 LT_RST#, or S00 LT_RST# or _RST#. RS0: Powered from the.-v rail and driven by S00 LT_RST#, or S00 LT_RST# or _RST#. (,) V () PU_LT_RST# RS0 N_PLTRST# RX0 +N_ORE_ON RX0 North ridge RESET selects Loading of straps from EPROM : use default vaule, default 0 : I Master can load strap values from EEPROM if connected, or use default values if not connected RX0 --RS0_UX_L RS0 -- SUS_TT Enables ebug us acess through memory T/O pads and GPIO. 0 : Enable RS0, efault : isable RS0 (RS0 use VSYN#) Indicates if memory Side port is available or not 0: available RS0, efault : Not available RS0 ( RS0 use HSYN#) For extrnal EEPROM ebug only R 0_ STRP_T Enables ebug us acess through memory T/O pads and GPIO. : Enable RX0, efault 0 : isable RX0 INT_VSYN INT_HSYN N_RST#_IN INT_RT_T INT_RT_LK /0 add K pull up to T /LK to V for RX0 / no stuff for RS0M/M/RX R0 R R0 R0 R.K_.K_ *0K/F_ *0K/F_ *0_ V RS0_UX_L R R INT_TV_/R R R R R0 () () () () () () () () () () () () RX0 K_ RS0 RS0 *K_ RS0/RX0 R *0K/F_.K/F_ K_ K_ only () () () () () () () INT_RT_RE INT_RT_GRN INT_RT_LU () INT_HSYN () INT_VSYN INT_RT_T INT_RT_LK N_PWRG_IN NHT_REFLKP NHT_REFLKN EXT_N_OS.V_N NGFX_LKP NGFX_LKN NGPP_LKP NGPP_LKN SLINK_LKP SLINK_LKN INT_LVS_EIT INT_LVS_EILK IV_HMI_T IV_HMI_LK V V +VG_N RX0 *K_ V R00 RS0.K_ V. R R R0 R INT_LVS_EIT INT_LVS_EILK IV_HMI_T IV_HMI_LK T0 T () RS0 R0.K_ +N_ORE_ON V. VPIEPLL -PIE PLL 0mils width L0 +.V_VPIEPLL LMPGSN(0,.)_ +V_V_N +.V_VI_N +.V_VQ_N INT_RT_RE INT_RT_GRN INT_RT_LU INT_HSYN INT_VSYN T_INT LK_INT _RSET_N +.V_PLLV +.V_PLLV +.V_VHTPLL +.V_VPIEPLL N_RST#_IN N_PWRG_IN N_LT_STOP# N_LLOW_LTSTOP NGFX_LKP NGFX_LKN NGPP_LKP NGPP_LKN SLINK_LKP SLINK_LKN +.V_PLLV 0mils width L +.V_VHTPLL LMPGSN(0,.)_ INT_TV_/R RX0 -->N / RS0 --- L +V_V_N LMPGSN(0,.)_ V- nalog not applicable to RX0 L LMPGSN(0,.)_ 00 0U/.V_ T T T PLLV - Graphics PLL not applicable to RX0 IV@0/F_ IV@0/F_ IV@0/F_ IV@/F_ VHTPLL -HT LINK PLL R 0_ R 0_ T NHT_REFLKP NHT_REFLKN R 0_.U/.V_.U/.V_.U/.V_.U/.V_ N_REFLK_P N_REFLK_N RS0_FT_GPIO.V_N STRP_T RS0_UX_L V. (,) () +.V_PLLV +.V_VI_N LMPGSN(0,.)_ +.V_VQ_N L PU_LT_STOP# () L F E F G H H E F F G G E F E F E F G H E 0 0 E F T T U U V V 0 G R 0_ PU_LT_REQ# LLOW_LTSTOP U V(N) TXOUT_L0P(N) V(N) PRT OF TXOUT_L0N(N) VI(N) TXOUT_LP(N) VSSI(N) TXOUT_LN(N) VQ(N) TXOUT_LP(N) 0 VSSQ(N) TXOUT_LN(G_GPIO0) 0 TXOUT_LP(N) _Pr(FT_GPIO) TXOUT_LN(G_GPIO) Y(FT_GPIO) OMP_Pb(FT_GPIO) TXOUT_U0P(N) TXOUT_U0N(N) RE(FT_GPIO0) TXOUT_UP(PIE_RESET_GPIO) REb(N) TXOUT_UN(PIE_RESET_GPIO) GREEN(FT_GPIO) TXOUT_UP(N) 0 GREENb(N) TXOUT_UN(N) LUE(FT_GPIO) TXOUT_UP(PIE_RESET_GPIO) LUEb(N) TXOUT_UN(N) _HSYN(PWM_GPIO) TXLK_LP(G_GPIO) _VSYN(PWM_GPIO) TXLK_LN(G_GPIO) _S(PE_TLRN) TXLK_UP(PIE_RESET_GPIO) _SL(PE_RLRN) TXLK_UN(PIE_RESET_GPIO) _RSET(PWM_GPIO) VLTP(N) PLLV(N) VSSLTP(N) PLLV(N) PLLVSS(N) VLT_(N) VLT_(N) VHTPLL VLT_(N) VLT_(N) VPIEPLL VPIEPLL VSSLT(VSS) VSSLT(VSS) SYSRESETb VSSLT(VSS) POWERGOO VSSLT(VSS) LTSTOPb VSSLT(VSS) 0 LLOW_LTSTOP VSSLT(VSS) E0 VSSLT(VSS) HT_REFLKP HT_REFLKN I REFLK_P/OSIN(OSIN) REFLK_N(PWM_GPIO) I LVS_IGON(PE_TLRP) E LVS_LON(PE_RLRP) F GFX_REFLKP LVS_EN_L(PWM_GPIO) G GFX_REFLKN I/O GPP_REFLKP GPP_REFLKN I/O GPPS_REFLKP(S_REFLKP) GPPS_REFLKN(S_REFLKN) I_T I_LK _T/UX0N(N) _LK/UX0P(N) UXP(N) UXN(N) STRP_T RSV UX_L(N) RS0(RX0) LMPGSN(0,.)_ V. RT/TVOUT LOKs PM PLL PWR LVTM PLLV - Graphics PLL not applicable to RX0.U/.V_.U/.V_.U/.V_ R 00_ Q *SS_NL/SOT RS0 Q *SS_NL/SOT R 0_ MIS. VI- igital not applicable to RX0 VQ- andgap Reference not applicable to RX0 V. R 0_ RX0 V. R 0_ RX0 TMS_HP(N) HP(N) TVLKIN(PWM_GPIO) THERMLIOE_P THERMLIOE_N +VG_N TESTMOE R *.K_ +VG_N RS0 R0 *.K_ N_LT_STOP# N_LLOW_LTSTOP 0 E V. TEST_EN +.V_VLTP_N +.V_VLT N R R TMS_HP0 SUS_STT#_N R_N_THRM R_N_THRM L L +V_VLT_N INT_TXLOUT0+ () INT_TXLOUT0- () INT_TXLOUT+ () INT_TXLOUT- () INT_TXLOUT+ () INT_TXLOUT- () T0 T INT_TXUOUT0+ () INT_TXUOUT0- () INT_TXUOUT+ () INT_TXUOUT- () INT_TXUOUT+ () INT_TXUOUT- () T T INT_TXLLKOUT+ () INT_TXLLKOUT- () INT_TXULKOUT+ () INT_TXULKOUT- () RS0 only/0 exchange LVS_PWM /LVS_LON EV@.K/F_ EV@.K/F_ IV@.U/.V_ T T R 0_ R.K/F_ RX0 T T IV@LMPGSN(0,.)_ IV@.U/.V_ LMPGSN(0,00M,)_ V. V RS0 INT_LVS_IGON () INT_LVS_LON () For RX0 only SUS_STT# () +.V_VLTP_N VLTP - LVS or VI/HMI PLL not applicable to RX0 +.V_VLT N VLT - LVS or VI/HMI digital not applicable to IV@0.U/0V_ RX0 R R EV@0_ IV@0_ L V +V_VLT_N *LMPGSN(0,00M,)_ *.U/.V_ VLT - LVS or VI/HMI NLOG RS0 only Wednesday, June, 00 ate: Sheet of 0 +VG_N PROJET : PF Quanta omputer Inc. Size ocument Number Rev RS0/RS0-SYSTEM I/F /

12 E G G G H J R L L L L M N P R R R V U V V W W W W W Y E E UF E G E E J J K M L RX0/RS0 POWER IFFERENE TLE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 PIN NME VHT VHTRX RX0 +.V +.V RS0 +.V +.V PIN NME IOPLLV V RX0 N N RS0 +.V +.V PRT / GROUN VHTTX VPIE VG +.V +.V +.V +.V +.V +.V VI VQ PLLV N N N +.V +.V +.V VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT0 VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT0 VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS V_MEM VPIE V N +.V PLLV N +.V +.V VPIEPLL +.V +.V +.V VHTPLL +.V +.V +.V +.V E G G G H J L L L L M0 N P0 R R R R H0 U V W W W Y L M N P P R R T U U U V W W Y E0 K V_MEM VG N N +.V/.V +.V VLTP VLT N N +.V +.V IOPLLV N +.V VLT N N (,,,,,0,,) (,,,,,,,,,,,,,0,,,,,,,,,,0,,,) (,,,,,,,,,) V. V V. V. VHT - HT LINK digital I/O for RX0/RS0 VHTRX - HT LINK RX I/O for RX0/RS0.V_N +.V for RS0M 0. L LMPGSN(0,00M,)_ 0. V. for RS0M+S00 0. L LMPGSN(0,00M,)_ / V. remove VHTTX - HT LINK TX I/O for RX0/RS0 V - RS0 I/O transform V. V. 0.U/.V_ L LMPGSN(0,00M,)_.U/.V_ 0.U/0V_ +.V for RS0M+S00 00m V. L LMPGSN(0,00M,)_ VPIE - PIE TX stage.u/.v_.u/.v_ I/O for RX0/RS0.U/.V_ R0 0_ R 0_ V_MEM For UM RS0 only Not applicable to RX0 memory I/O transform 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0.00 U/0V_ U/0V_ +.V_VHT 0.U/0V_ +.V_VHTRX +.V_VHTTX 0.U/0V_ 0 0.U/0V_ +.V_VPIE 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ +.V_VG_N +.V_V_MEM J K L M P R T H G F0 E E Y0 W V U T R P M J0 P0 K0 M0 L0 W H T0 R0 Y E U0 F G E (,0,,).V_N (0,) N_ORE UE VHT_ VHT_ VHT_ VHT_ VHT_ VHT_ VHT_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_0 VHTTX_ VHTTX_ VHTTX_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_0 VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ PRT / POWER VG_(V_) VG_(V_) V_MEM(N) V_MEM(N) RS0(RX0) VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_0 VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) VG_(N) VG_(N) E F G H J K M L P R T V U K J U J K M L L M M N N P P P R R T T U T J E0 Y H H +.V_V_PIE 0.U/0V_ 0.U/0V_ U/0V_ 0.U/0V_ 0.U/0V_ +.V_V_MEM +V_VG 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0. U/0V_ 0 0.U/0V_ 0.U/0V_.V(0.) 0.U/0V_ R RS0.V(0.0) 0_ V V -.V I/O 0.U/0V_ Not applicable to RX0 VPIE - PIE-E Main power R 0_.U/.V_.V_N V - ore Logic power N_ORE 0U/.V_ 0U/.V_ L.U/.V_ V_MEM For UM RS0 only Not applicable to RX0 memory I/O transform V. LMPGSN(0,00M,)_ PROJET : PF Quanta omputer Inc. Size ocument Number Rev RS0/RS0-POWER/ ate: Wednesday, June, 00 Sheet of 0

13 R0 *0M_ PLE THESE PIE OUPLING PS LOSE TO U Y.KHZ R 0M_ 0 P/0V_ () N_PLTRST# (0,,,,) PLTRST# To RS0 0.U/0V RX0P_ 0.U/0V RX0N_ 0.U/0V RXP_ 0.U/0V RXN_ 0.U/0V RXP_ 0.U/0V RXN_ 0.U/0V RXP_ 0.U/0V RXN RST#_S PIE_N_S_TX0P PIE_N_S_TX0N PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN PIE_LRP_S PIE_LRN_S V. L LMPGSN(0,.)_ +.V_PIE_PV 0m PIE_PV-- PIE PLL POWER 0 0U/.V_ U/0V_ RT_X RT_X P/0V_ (0) PIE_S_N_RX0P (0) PIE_S_N_RX0N (0) PIE_S_N_RXP (0) PIE_S_N_RXN (0) PIE_S_N_RXP (0) PIE_S_N_RXN (0) PIE_S_N_RXP (0) PIE_S_N_RXN (0) PIE_N_S_TX0P (0) PIE_N_S_TX0N (0) PIE_N_S_TXP (0) PIE_N_S_TXN (0) PIE_N_S_TXP (0) PIE_N_S_TXN (0) PIE_N_S_TXP (0) PIE_N_S_TXN R0 R +.V_PIE_VR () SSR_LKP () SSR_LKN T0 T T T0 T T T T T T T T T T T T V. V () LLOW_LTSTOP () PU_PROHOT# () PU_PWRG (,) PU_LT_STOP# (,) PU_LT_RST# T R R R _ R _ *0K/F_ *0K/F_ /F_.0K/F_ SSR_LKP SSR_LKN N_ISP_LKP N_ISP_LKN N_HT_LKP N_HT_LKN PU_HT_LKP PU_HT_LKN SLT_GFX_LKP SLT_GFX_LKN GPP_LK0P GPP_LK0N GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN T T RT_X RT_X LLOW_LTSTOP PU_PROHOT# PU_PWRG PU_LT_STOP# PU_LT_RST# N _RST# V PIE_TX0P V PIE_TX0N V PIE_TXP V PIE_TXN U PIE_TXP U PIE_TXN T PIE_TXP T PIE_TXN U PIE_RX0P U PIE_RX0N U PIE_RXP V PIE_RXN R0 PIE_RXP R PIE_RXN R PIE_RXP R PIE_RXN T PIE_LRP T PIE_LRN P P PIE_PV N PIE_RLKP/N_LNK_LKP N PIE_RLKN/N_LNK_LKN P PU_HT_LKP M PU_HT_LKN M SLT_GFX_LKP M SLT_GFX_LKN J GPP_LK0P J GPP_LK0N L0 GPP_LKP L GPP_LKN M GPP_LKP M0 GPP_LKN PIE_PVSS K N_ISP_LKP K N_ISP_LKN M N_HT_LKP M N_HT_LKN 00MHZ N GPP_LKP P GPP_LKN L J J0 U M_M_M_OS M_X M_X X X RT XTL F LLOW_LTSTP F PROHOT# F LT_PG G LT_STP# G LT_RST# PU S00 Part of PI EXPRESS INTERFE LP RT LOK GENERTOR PI LKS PI INTERFE S00 I TRL(P) S00 (SELFG) P/N : JL0T00 PILK0 PILK PILK PILK PILK PILK/GPIO PIRST# E0# E# E# E# FRME# EVSEL# IRY# TRY# PR STOP# PERR# SERR# REQ0# REQ# REQ# REQ#/GPIO0 REQ#/GPIO GNT0# GNT# GNT# GNT#/GPIO GNT#/GPIO LKRUN# LOK# INTE#/GPIO INTF#/GPIO INTG#/GPIO INTH#/GPIO LPLK0 LPLK L0 L L L LFRME# LRQ0# LRQ#/GNT#/GPIO MREQ#/REQ#/GPIO SERIRQ RTLK INTRUER_LERT# VT P P P P T T N U P V T V U V V T W T R R R U U Y W V Y Y Y Y W U Y W Y U W W V E E E V E E G E H H J J H H V PI_LK_R PI_LK_R PI_LK_R PI_LK_R PIRST#_L PE_GPIO INTE# INTF# INTG# INTH# LP_LK0 LP_LK L0 L L L LFRME# LRQ0#_S LRQ#_S S_GPIO SERIRQ RT_LK INTRUER_LERT# 0MIL R _ R _ R _ R _ R0 _ E_GPIO# () PIRST# ll the PI bus has build-in Pull-UP/own resistors T T T T R 0_ T T T T T0 T00 R _ R _ T T0 T T T T0 L0 (,) L (,) L (,) L (,) LFRME# (,) SERIRQ () RT_LK () RT H0H-0PT VPU () () () () () () PI_LK () PI_LK () PI_LK () PI_LK () L_ON () PIRST# (,) VRT VPU PLK_E (,) PLK_ (,) VRT 0.U/0V_ H0H-0PT R K_ T T_ONN FHS0FS R R.K_ R K_ / M suggest change to V S_GPIO PE_GPIO Maybe can remove G *SHORT_P R0 K_ R+R = (V - 0.V-V)/0.m = k R.K/F_ R0 R0 R0 Q VRT_ MMT0.K/F_ 00K/F_.K_ *.K_ u/0v_ V PROJET : PF Quanta omputer Inc. 0.u/0V_ Size ocument Number Rev S00-PIE/PI/PU/LP / ate: Wednesday, June, 00 Sheet of 0

14 RV N only,an't be install R *.K_ S_TEST0 RV V RV R0 R R S_TEST S_TEST *0K/F_ SWI# SL0/ST0 is V tolerance M datasheet define it R.K_ PLK_SM R PT_SM SL/ST is V/S tolerance M datasheet define it Wlan ard R0 0K/F_ S_SMLK R00 0K/F_ S_SMT RV SL/ST is V/S tolerance M datasheet define it epress card R 0K/F_ S_SLK R 0K/F_ S_ST V *.K_ *.K_.K_ R.K_ lock gen/robson/tv tuner /R/R thermal/ccelerometer SUS_STT# T T T () SUS# () SUS# () NSWON# () S_PWRG_IN () SUS_STT# () () () () () GTE0 RIN# SI# KSMI# T (,) PIE_WKE# () SWI# () PU_THERMTRIP# () W_PWRG RSMRST# T T () IOS_WP# for IOS Write Protect T T () PEEP (,,,) PLK_SM (,,,) PT_SM () PM T T () E_SI# R 0_ R 0_ R 0_ RI# SLP_S SUS# SUS# NSWON# S_PWRG_IN SUS_STT# S_TEST S_TEST S_TEST0 GTE0 RIN# SI# KSMI# SYS_RST# PIE_WKE# SWI#_ PU_THERMTRIP# W_PWRG RSMRST#_ ST_IS Z_SPKR PLK_SM PT_SM S_SMLK S_SMT SES_INT GEVENT# E PI_PME#/GEVENT# E RI#/EXTEVNT0# H SLP_S/GPM# F SLP_S# G SLP_S# H PWR_TN# H PWR_GOO K SUS_STT# H TEST H TEST H TEST0 Y G0IN/GEVENT0# W KRST#/GEVENT# K LP_PME#/GEVENT# K LP_SMI#/EXTEVNT# F S_STTE/GEVENT# J SYS_RESET#/GPM# H WKE#/GEVENT# F LINK/GPM# J SMLERT#/THRMTRIP#/GEVENT# W N_PWRG U RSMRST# S00 PI / WKE UP EVENTS E ST_IS0#/GPIO0 LK_REQ#/ST_IS#/GPIO SMRTVOLT/ST_IS#/GPIO W LK_REQ0#/ST_IS#/GPIO0 V LK_REQ#/ST_IS#/FNOUT/GPIO W0 LK_REQ#/ST_IS#/FNIN/GPIO0 W SPKR/GPIO SL0/GPO0# W S0/GPO# K SL/GPO# K S/GPO# 0 _SL/GPIO Y _S/GPIO LL#/GPIO Y SHUTOWN#/GPIO G R_RST#/GEVENT# USLK/M_M_M_OS US MIS GPIO US. US.0 Part of US_ROMP G US_FSP E US_FSN E US_FSP F US_FSN E US_HSP H US_HSN J0 US_HS0P E US_HS0N F US_HSP US_HSN US_HSP 0 US_HSN 0 US_HSP G US_HSN H US_HSP E US_HSN E US_HSP US_HSN US_HSP US_HSN US_HSP G US_HSN G US_HSP H US_HSN H LK_M_US US_ROMP_S US_FSP US_FSN US_FSP US_FSN R NEW_USP0+ () NEW_USP0- () T_USP+ () T_USP- () USP+ () USP- () USP+ () USP- () USP+ () USP- () WL_USP+ () WL_USP- () _USP+ () _USP- () LK_M_US ().K/F_ T T T T T T To New ard To luetooth To min-card (TV) To M/ US To US board To WLN To amera LK_M_US R *0_ *0P/0V_ for EMI Z_SOUT Z_SYN Z_LK Z_RST# Z_SIN0_R To zalia R _ R _ R0 _ R _ R 0_ *0P/0V_ (,) PU_MEMHOT# (,) THERM_LERT# () NEW_ET# Z_SOUT_UIO () Z_SYN_UIO () *0P/0V_ IT_LK_UIO () *0P/0V_ Z_RST#_UIO () Z_SIN0 () () H0H-0PT PU_MEMHOT#_IN R 0_ SMLERT#_ R 0_ R *0_ S_JTG_TO S_JTG_TK S_JTG_TI S_JTG_RST# Z_RST# () H_UX_RST# T T Z_LK Z_SOUT Z_SIN0_R Z_SIN_R Z_SYN Z_RST# H audio interface is.v voltage V R K_ H_UX_RST# E F E M M J J L M L M L H H0 H F E E US_O#/IR_TX/GEVENT# US_O#/IR_TX0/GPM# US_O#/IR_RX0/GPM# US_O#/IR_RX/GPM# US_O#/GPM# US_O#/GPM# US_O0#/GPM0# Z_ITLK Z_SOUT Z_SIN0/GPIO Z_SIN/GPIO Z_SIN/GPIO Z_SIN/GPIO Z_SYN Z_RST# Z_OK_RST#/GPM# IM_GPIO0 IM_GPIO SPI_S#/IM_GPIO IE_RST#/F_RST#/IM_GPO IM_GPIO IM_GPIO IM_GPIO IM_GPIO H UIO US O INTEGRTE u INTEGRTE u US_HSP US_HSN US_HS0P US_HS0N IM_GPIO IM_GPIO IM_PWM0/IM_GPIO0 SL/IM_GPIO S/IM_GPIO SL_LV/IM_GPIO S_LV/IM_GPIO IM_PWM/IM_GPIO IM_PWM/IM_GPO IM_PWM/IM_GPO IM_GPIO IM_GPIO IM_GPIO0 IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO0 IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO0 IM_GPIO F F E0 E E E G0 G S_SLK S_ST S_SLK S_ST S_GPIO S_GPIO USP+ () USP- () USP0+ () USP0- () T T To US oard To US oard S_GPIO () S_GPIO () SPI/LP define S00 PROJET : PF Quanta omputer Inc. Size ocument Number Rev S00-PI/GPIO/US / ate: Wednesday, June, 00 Sheet of 0

15 ST PORT 0,,, can support HI mode ST ST E-ST ST O () ST_TXP0 () ST_TXN0 () ST_RXN0 () ST_RXP0 () ST_TXP () ST_TXN () ST_RXN () ST_RXP () ST_TXP () ST_TXN () ST_RXN () ST_RXP () ST_TXP () ST_TXN () ST_RXN () ST_RXP () ST_TXP () ST_TXN () ST_RXN () ST_RXP 0 REVF: Reserve for Hitachi O ST PORT, are only support IE mode PLE ST_L RES VERY LOSE TO LL OF S00 NOTE: R0 IS K % FOR MHz XTL,.K % FOR 00MHz INTERNL LOK R0 PLE ST OUPLING PS LOSE TO S00 () ST_LE# PLV_ST-- ST PLL POWER K/F_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ R0 0_ R 0_ U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ *0.0U/V_ *0.0U/V_ *0.0U/V_ *0.0U/V_ ST_TXP0_ ST_TXN0_ ST_RXN0_ ST_RXP0_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_RIS_PN ST_LE# ST_TXP_ ST_TXN_ ST_RXN ST_RXP ST_X ST_X ST_X ST_X V R 0K/F_ +.V_PLLV_ST +V_XTLV_ST XTLV_ST-- ST crystal power 0P/0V_ MHz/0pF/ppm Y R 0M_ 0P/0V_ U ST_TX0P E ST_TX0N 0 ST_RX0N 0 ST_RX0P E0 ST_TXP 0 ST_TXN ST_RXN E ST_RXP ST_TXP ST_TXN E ST_RXN ST_RXP ST_TXP E ST_TXN ST_RXN ST_RXP E ST_TXP ST_TXN ST_RXN E ST_RXP ST_TXP ST_TXN E ST_RXN ST_RXP V ST_L Y ST_X ST_X W ST_T#/GPIO PLLV_ST W XTLV_ST S00 ST PWR SERIL T S00 Part of HW MONITOR SPI ROM T /00/ IE_IORY IE_IRQ IE_0 Y IE_ IE_ Y IE_K# IE_RQ IE_IOR# IE_IOW# IE_S# Y IE_S# Y IE_0/GPIO IE_/GPIO IE_/GPIO E IE_/GPIO IE_/GPIO IE_/GPIO0 E0 IE_/GPIO 0 IE_/GPIO IE_/GPIO E IE_/GPIO 0 IE_0/GPIO 0 IE_/GPIO E IE_/GPIO IE_/GPIO IE_/GPIO E IE_/GPIO0 SPI_I/GPIO G SPI_O/GPIO SPI_LK/GPIO SPI_HOL#/GPIO F SPI_S#/GPIO F LN_RST#/GPIO U ROM_RST#/GPIO J FNOUT0/GPIO M FNOUT/GPIO M FNOUT/GPIO M FNIN0/GPIO0 P FNIN/GPIO P FNIN/GPIO R TEMP_OMM TEMPIN0/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO 0/GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO0 V VSS F G P0 P P P P P P P P P P0 P P P P P ROM_RST# S_FNOUT0 S_FNOUT S_FNTH0 S_FNTH PORT_0_PWR_WN TEMP_OMM TEMPIN0 TEMPIN M_THRM_S m 0 T0 T T T T +V_V_HWM *0.U/0V_ T0 T T T T T T T PIORY () IRQ () P0 () P () P () PK# () PREQ () PIOR# () PIOW# () PS# () PS# () P[0..] () T T T T T T0 T OR_I0 OR_I OR_I OR_I OR_I L 0_ *.U/.V_ 0/ M suggest to connect to GN RV V--H/W monitor nalog power V. 0m) +.V_PLLV_ST L LMPGSN(0,.)_.U/.V_ m 0.U/0V_ V R *0K/F_ OR_I0 R 0K/F_ / oard I define MXM M I Selection Table oard I I I I I " UM x x 0 0 I0 0 V L LMPGSN(0,.)_ m +V_XTLV_ST U/0V_ Place near ball R R0 R *0K/F_ *0K/F_ *0K/F_ OR_I OR_I OR_I R R R 0K/F_ *0K/F_ *0K/F_ " M " M " UM " M " M x x 0 0 x x 0 x x 0 0 x x 0 x x PROJET : PF Quanta omputer Inc. Size ocument Number Rev S00-ST/IE/HWM/SPI / ate: Wednesday, June, 00 Sheet of 0