HOST 200MHz PCIE 100MHz USB 48MHz REF 14MHz BCM5906 PCI-E, 1X PCI-E, 1X USB2.0 (P1) PCI-E, 1X USB2.0 (P4) PG 10,11,12,13 WEB CAM USB2.

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1 SYSTEM LOK IGRM RM Mb RII-SOIMM PG, RII-SOIMM PG, L onnector PG ST - H PG R II MHZ ST0 LS(ch) M+ PI-E, X PG 0,,,, RM Mb RM Mb RM Mb PG M M thlon X.G M ual ore thlon X 0e.G ual ore thlon 0e.G single core PG,,, HT_LINK RS0M FG PG 0,,, _LINK (X) S00 HOST 00MHz PIE 00MHz US MHz REF MHz PI-E, X PI-E, X US.0 (P) PI-E, X US.0 (P) US.0 (P) US.0 (P) LOK GENERTOR IS FN ONTROL M0 Mini ard (WLN) PI Express Mini ard MINI R (T) PI Express Mini ard WE M PG US.0 I/O Ports X PG PG THERML SENSOR PG PG,, RJ PG PG PG PG _ORE LT_RUN +.SUS +.SUS +. SMR SMR_TERM TERM PG PU PU R SUS SUS PU R / H PWR PG PG PG PG 0 ST - O ST G PG PI-E, X PG,,,, LP zalia zalia udio odec L PG 0 R PI Interface PG E ITE PG mplifier Max0 PG 0 mplifier TP PG 0 a PG IN PG SPI Flash ROM PG PS/II K PG MI. PG 0 INT. S.P. H.P PG 0 PG 0 Quanta omputer Inc. PROJET : QU Size ocument Number Rev LOK IGRM Saturday, February, 00 ate: Sheet of

2 oltage Rails Power oltage S0~S S S S tl Signal PI EIES IRQ ROUTING PI EIE ISEL# REQ# / GNT# Interrupts LK Page 0: Page 0: Page 0: Page 0: Page 0: Page 0: Page 0: Page 0: Page 0: Page 0: Page : Page : Page : Page : Page : Page : Page : Page : Page : Page 0: Page : Page : Page : Page : Page : Page : Page : Page : Page : Page 0: Page : Page : Page : Page : Page : Page : Page : Page : Page : Page 0: Page : Page : Page : Page : lock diagram System information lock generator IS M M+ HT I/F M M+ RII MEMORY I/F M M+ TRL & EUG M M+ PWR & GN R SOIMM X R Termination RS0M HT interface RS0M PIE interface RS0M PLL & EIO I/F RS0M Power S00 PIE/PI/RT/LP/PU Interface S00 PI/GPIO/US/ S00 ST/PT Interface S00 POWER & ecoupling S00 Straps L PNEL/WEM M-M(PIE I/F) MM(LS/RG/HMI/T) M-M(MEM I/F) M-M(Thermal/STRP/EEPROM) M-M(POWER/GN) RM*(GR-G) LN M0 US R PI/ ST H/O H_L MINI R FN/ aughter board E ITE IN / (MX00) R.(TPS) PU ORE (MX) N.(RT0) _ORE (OZ) / H(MX0) N ORE(OZ) POWER MNGER IGRM SREW HOLE & EMI History IN PU PU P STK UP LYER : TOP LYER : GN LYER : IN LYER : GN LYER : LYER : IN LYER : GN LYER : OT ST_ON SUS SUS SUSON SUSON.SUS. SUSON MINON MINON.. MINON.. MINON.. MINON.. MINON PU N SMR_TERM _ORE +.LW +.LW y PU _EN _EN PU _EN ST_ON MINON MINON MINON R_ON.. MINON N G N S (INT) N /ZLI N US 0 N R 0 Power On Sequence IN PU/PU PWRTN# PWRTNON# RSMRST# SUS#,SUS# SUSON MINON SUS, R_ON ORE_PU N_PWRG PWROK N E/F/G INT INT PLK0 From From From From PIRST# Quanta omputer Inc. PROJET : QU Size ocument Number Rev SYSTEM INFORMTION Saturday, February, 00 ate: Sheet of

3 LK_ L0 ohm,00m LK_ L U/./ 0U_00 0.U 0.U 0 0.U *0.U 0 0.U 0.U 0.U 0.U U/./ 0.U 0ohm_ 0U_00 Put ecoupling aps close to lock Fen. power pin L LK US LK_ U 0ohm_ L 0ohm_ LK_ R 0K U U *0.U *0.U P Y.MHZ P LK REF.U/0/ 0.U/0/ R0 *M Parallel Resonance rystal LK_XIN LK_XOUT 0 PU _SR _SR _SR _SR TIG _REF HTT GN_PU GN_SR GN_SR GN_SR GN_SR GN_ GN_TIG GN_REF GNHTT XIN XOUT RESET_IN# N GN PULKT0 PULK0 PULKT PULK SRLKT SRLK TIGLKT0 TIGLK0 TIGLKT TIGLK TIGLKT TIGLK TIGLKT TIGLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT SRLK SRLKT0 SRLK0 SRLKT SRLK SRLKT SRLK LK_ PULK_EXT_R PULK#_EXT_R SLINK_LKP_R SLINK_LKN_R RP0 NSR_LKP_R NSR_LKN_R RP PIE_REFLKP_R PIE_REFLKN_R RP SSR_LKP_R SSR_LKN_R GPP_LK0P_R GPP_LK0N_R GPP_LKP_R GPP_LKN_R GPP_LKP_R GPP_LKN_R R *0K RP RP RP RP LK_ R *0K R R0./F./F X X X X X X X R /F PULKP PULKN SLINK_LKP SLINK_LKN NSR_LKP NSR_LKN PIE_REFLKP 0 PIE_REFLKN 0 LK_PIE_WLN LK_PIE_WLN# LK_PIE_LN LK_PIE_LN# SSRLKP SSRLKN LK_PIE_R LK_PIE_R#,, SLK0,, ST0 Ioh = * Iref (.m) oh = 0 ohm R0 /F 0 SMLK SMT IREF LKREQ# LKREQ# LKREQ# MHz_ MHz_0 FS/REF FS0/REF0 FS/REF HTTLK0 LK_M R PE_LKREQ- PE_LKREQ- R USLK R./F R./F R./F R./F R./F R0./F R0./F R0./F R./F R./F R./F R0./F R0./F R./F IS LKREQ# ONTROL SR,, LKREQ# ONTROL SR,, TIG LKREQ# ONTROL SR0, TIG0,, LK_ R R 0K 0K R 0K EXT LK FREQUENY SELET TLE(MHZ) FS FS FS0 PU SRLK [:] HTT PI US OMMENT Hi-Z Hi-Z Hi-Z X X/ X/ Normal THLON operation heck M clock S_OSIN_R R N_OSIN_R R HTREFLK_R R0 R./F R *0 R *0 R *0 S_OSIN N_OS HTREFLK Size ocument Number Rev lock Generator Quanta omputer Inc. PROJET : QU ate: Saturday, February, 00 Sheet of

4 PU HyperTransport Interface LTRUNPU is connected to the _LT_RUN power supply through the package or on the die. It is only connected on the board to decoupling near the PU package. LT==>0. LT_RUN U J LT_0 J LT_0 J LT_0 J LT_0 LT_0 LT_0 LT_0 LT_0 H H H H.U_00 LT_RUN R R 0 HT_IN_P U L0_IN_H L0_OUT_H Y HT_OUT_P 0 0 HT_IN_N L0_IN_L L0_OUT_L Y HT_OUT_N 0 0 HT_IN_P T L0_IN_H L0_OUT_H HT_OUT_P 0 0 HT_IN_N T L0_IN_L L0_OUT_L HT_OUT_N 0 0 HT_IN_P R L0_IN_H L0_OUT_H HT_OUT_P 0 0 HT_IN_N T L0_IN_L L0_OUT_L HT_OUT_N 0 0 HT_IN_P P L0_IN_H L0_OUT_H HT_OUT_P 0 0 HT_IN_N P L0_IN_L L0_OUT_L HT_OUT_N 0 0 HT_IN_P M L0_IN_H L0_OUT_H F HT_OUT_P 0 0 HT_IN_N M L0_IN_L L0_OUT_L E HT_OUT_N 0 0 HT_IN0_P L L0_IN_H0 L0_OUT_H0 F HT_OUT0_P 0 0 HT_IN0_N M L0_IN_L0 L0_OUT_L0 F HT_OUT0_N 0 0 HT_IN_P K L0_IN_H L0_OUT_H H HT_OUT_P 0 0 HT_IN_N K L0_IN_L L0_OUT_L G HT_OUT_N 0 0 HT_IN_P J L0_IN_H L0_OUT_H H HT_OUT_P 0 0 HT_IN_N K L0_IN_L L0_OUT_L H HT_OUT_N 0 0 HT_IN_P U L0_IN_H L0_OUT_H Y HT_OUT_P 0 0 HT_IN_N U L0_IN_L L0_OUT_L W HT_OUT_N 0 0 HT_IN_P R L0_IN_H L0_OUT_H HT_OUT_P 0 0 HT_IN_N T L0_IN_L L0_OUT_L HT_OUT_N 0 0 HT_IN_P R L0_IN_H L0_OUT_H HT_OUT_P 0 0 HT_IN_N R L0_IN_L L0_OUT_L HT_OUT_N 0 0 HT_IN_P N L0_IN_H L0_OUT_H HT_OUT_P 0 0 HT_IN_N P L0_IN_L L0_OUT_L HT_OUT_N 0 0 HT_IN_P L L0_IN_H L0_OUT_H E HT_OUT_P 0 0 HT_IN_N M L0_IN_L L0_OUT_L E HT_OUT_N 0 0 HT_IN_P L L0_IN_H L0_OUT_H F HT_OUT_P 0 0 HT_IN_N L L0_IN_L L0_OUT_L E HT_OUT_N 0 0 HT_IN_P J L0_IN_H L0_OUT_H G HT_OUT_P 0 0 HT_IN_N K L0_IN_L L0_OUT_L G HT_OUT_N 0 0 HT_IN0_P J L0_IN_H0 L0_OUT_H0 H HT_OUT0_P 0 0 HT_IN0_N J L0_IN_L0 L0_OUT_L0 G HT_OUT0_N 0 0 HT_LKIN_P 0 HT_LKIN_N 0 HT_LKIN0_P 0 HT_LKIN0_N./F./F HT_TLIN_P HT_TLIN_N N L0_LKIN_H P L0_LKIN_L N L0_LKIN_H0 N L0_LKIN_L0 L0_TLIN_H L0_TLIN_L HT LINK L0_LKOUT_H L0_LKOUT_L L0_LKOUT_H0 L0_LKOUT_L0 L0_TLOUT_H Y L0_TLOUT_L W HT_PU_TLOUT_P HT_PU_TLOUT_N HT_LKOUT_P 0 HT_LKOUT_N 0 HT_LKOUT0_P 0 HT_LKOUT0_N 0 T T 0 HT_TLIN0_P 0 HT_TLIN0_N U L0_TLIN_H0 L0_TLIN_L0 thlon M Processor Socket L0_TLOUT_H0 L0_TLOUT_L0 W W HT_TLOUT0_P 0 HT_TLOUT0_N 0 LT_RUN.U_00.U_00 0.U 0.U 0P 0P Size ocument Number Rev M M+ HT I/F Quanta omputer Inc. PROJET : QU ate: Saturday, February, 00 Sheet of

5 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS M QS M QS M QS M QS M QS M QS0 M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS M QS M QS M QS M QS M QS M QS0 M QS M M0 M M M M M M M M M M M M M M M M M M0 M M M M M M M M M M M M M M M M PU_M_REF M 0 M M M M M M M M M M 0 M M M 0 M M M M M M M 0 M M M M M M M M_ZP M_ZN TT_SENSE PU_M_REF SMR_TERM.SUS.SUS SMR_TERM M Q[0..] M Q[0..] M QS[0..] M QS#[0..] M QS[0..] M QS#[0..] M M[0..] M M[0..] M S#, M_OT, M_OT, M_OT, M_OT0, M S#0, M [0..], M RS#, M S#, M S#, M S#0, M S#, M S#, M S#, M [0..], M S#, M S#0, M_KE, M_KE, M_KE, M_KE0, M S#, M RS#, M S#, M WE#, M S#, M S#, M S#0, M WE#, M S#, M_LKOUT# M_LKOUT0 M_LKOUT0# M_LKOUT M_LKOUT M_LKOUT# M_LKOUT# M_LKOUT Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : M M+ R II Memory I/F Saturday, February, 00 QU Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : M M+ R II Memory I/F Saturday, February, 00 QU Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : M M+ R II Memory I/F Saturday, February, 00 QU To SOIMM socket (near) To SOIMM socket (Far) thlon M Processor Socket thlon M Processor Socket PLE THEM LOSE TO PU WITHIN " Processor R Memory Interface TT==>. 0P 0P 0.U 0.U.U_00.U_00 000P 000P 0.U 0.U 000P 000P 0.U 0.U 0.U_00 0.U_00 0P 0P R.F R.F 0 0.U 0 0.U 000P 000P T T R K/F R K/F.U_00.U_00 RII: T U RII: T U M_HEK K M_HEK K M_HEK G0 M_HEK G M_HEK L M_HEK L M_HEK H M_HEK0 G M_M J M_M J M_M H M_M J M_M K M_M 0 M_M M_M M_M0 M_M J M_M F M_M F M_M J M_M H M_M M_M E M_M E M_M0 H M_HEK K M_HEK J M_HEK G M_HEK G M_HEK L M_HEK K M_HEK H M_HEK0 H M_T0 G M_T E M_T E M_T H M_T H M_T G M_T E M_T G M_T E M_T G M_T0 F M_T G M_T G M_T F M_T E M_T E M_T F M_T G M_T M_T E M_T0 M_T E M_T E M_T F M_T E M_T M_T F M_T G M_T M_T M_T0 E M_T E M_T F M_T G M_T H M_T J M_T E M_T F M_T J M_T J M_T0 F M_T H M_T G M_T E M_T G M_T J M_T E M_T F M_T E M_T F M_T0 F M_T E M_T G M_T M_T E M_T G M_T E M_T G M_T E M_T M_T0 M_T G M_T G M_T E M_QS_L0 G M_QS_L F M_QS_L M_QS_L M_QS_L G M_QS_L G M_QS_L G M_QS_L E M_QS_H0 F M_QS_H E M_QS_H M_QS_H M_QS_H G M_QS_H G M_QS_H G M_QS_H M_QS_L J M_QS_H J M_T0 M_T M_T M_T M_T F M_T E M_T M_T M_T M_T M_T0 M_T M_T M_T M_T 0 M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T F M_T F M_T M_T M_T0 E0 M_T E M_T J M_T J0 M_T L M_T L M_T G0 M_T H M_T K M_T L M_T0 J M_T H M_T H M_T J M_T K M_T L M_T L M_T J M_T L0 M_T H M_T0 J M_T H M_T L M_T K M_T L M_T L M_T K M_T L M_T G M_T F M_T0 J M_T L M_T L M_T H M_QS_L0 M_QS_L M_QS_L M_QS_L M_QS_L L M_QS_L L M_QS_L J M_QS_L J M_QS_L J0 M_QS_H0 M_QS_H M_QS_H M_QS_H M_QS_H L M_QS_H K M_QS_H K M_QS_H K M_QS_H J 000P 000P 000P 000P U R II: M/TRL/LK U R II: M/TRL/LK TT TT TT TT TT J TT H TT G TT L MEMREF F TT_SENSE E MEMZN H MEMZP J M_S_L M_S_L0 M0_S_L M0_S_L0 M_KE M M_KE0 M M_KE L M_KE0 M M_ M_ N M_ P M_0 Y M_ N M_ R M_ P M_ R M_ R M_ R M_ T M_ U M_ T M_0 W M_NK Y M_NK0 M_RS_L M_S_L M_WE_L M_RS_L M_S_L M_WE_L 0 M_NK M_NK0 M_ E M_ N0 M_ P M_0 M_ P M_ R M_ R M_ R M_ R0 M_ T M_ T M_ U M_ U M_0 0 M_LK_H E0 M_LK_L E M_LK_H G0 M_LK_L G M_LK_H0 M_LK_L0 W M0_LK_H G M0_LK_L G0 M0_LK_H G M0_LK_L H M0_LK_H0 U M0_LK_L0 U M_LK_H L M_LK_L L M_LK_H M_LK_L M_LK_H0 W M_LK_L0 W M0_LK_H J M0_LK_L K M0_LK_H M0_LK_L M0_LK_H0 U M0_LK_L0 U0 M_S_L E M_S_L0 M0_S_L E0 M0_S_L0 M0_OT0 M_OT0 M_NK N M_ M M_ N M0_OT0 M_OT0 M_NK N M_ N M_ N TT K.U_00.U_ P 00 0P R.F R.F 0P 0P R K/F R K/F 0.U 0.U

6 PU_ THLON ontrol and ebug L 0ohm_00m ==>0m _RUN.SUS.SUS.SUS PU SHN PLI-TRL out =0.(+R/R) = 0. (+0K/.K) =. P 0U_00 GN IN O SET PU_ If M SI is not used, the SI pin can be left unconnected and SI should have a 00- (±%) pulldown to SS. R R PR 0K_ PR.K_ P 0U_00 OREF+ OREF- PU_ORE close to PU 0/F PR 0/F PR.SUS LT_RUN T T T T T 00.U_00 0.U PU_HT_RESET# PU_LL_PWROK PU_LTSTOP# PU_SI_R PU_SI_R R.F PU_HTREF PU_HTREF0 R.F place them to PU within " PU_IO_SUS_F_H PU_IO_SUS_F_L PU_LKIN_S_P PU_LKIN_S_N PU_RY 00pF U 0 THERMTRIP_L 0 PROHOT_L RESET_L PWROK LTSTOP_L I L SI I K SI I I HT_REF I HT_REF0 I0 PU_PRESENT_L G _F_H G _F_L PSI_L K IO_F_H N# L IO_F_L N# N# LKIN_H N# LKIN_L RY REQ_L K L E E E L F H H H0 H H_THERMTRIP# H_PROHOT# PU_PRESENT# PU_REQ# R 00 R 00 Q R 0K MMT0 S_THERMTRIP# I I I I I I0 PSI_L is a Power Status Indicator PSI# signal. This signal is asserted when the processor is in a low powerstate. T PSI_L should be connected to the power supply controller, if the controller supports skipmode, or diode emulation mode. PSI_L is asserted by the processor during the and S states..sus PU_SI PU_SI PULKP PULKN R *00 R *00 R0 *0 R *0 0 00P 00P PU_SI_R PU_SI_R R _00F 00 R0 PU_LKIN_S_P PU_LKIN_S_N PU_TEST_SINGLEHIN PU_TEST_URNIN# PU_PRESENT# PU_TEST_H_YPSSLK_H PU_TEST_SNEN PU_TEST0_SNLK PU_TEST_SNLK PU_TEST_SNSHIFTEN PU_TEST_SNSHIFTEN PU_TEST_P PU_TEST_P0 PU_TEST_L_YPSSLK_L PU_TEST_PLLTEST0 PU_TEST_PLLTEST R *00 R 00 R K/F R 0/F R 00 R0 *00 R *00 R *00 R *00 R *00 R *00 R0 0/F R 00 R 00 T T0 T T T T T T0 PU_TMS PU_TK PU_TRST# PU_TI PU_TEST_H_YPSSLK_H PU_TEST_L_YPSSLK_L PU_TEST_PLLTEST0 PU_TEST_PLLTEST PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST_P0 PU_TEST_SNSHIFTEN PU_TEST0_NLOG_T PU_TEST_IERKMON H_THERM H_THERM PU_TEST_GTE0 PU_TEST_RIN0 L H0 J0 L0 0 0 F0 E J F E F H E J G G H J TMS TK TRST_L TI TEST_H TEST_L TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TO TEST_H TEST_L N# N# N# N# TEST TEST TEST TEST TEST0 TEST_H TEST_L TEST TEST TEST0 TEST K0 E E K H J L J J0 H K K G PU_TO PU_TEST_H_FLKOUT_P PU_TEST_L_FLKOUT_N PU_TEST_SNLK PU_TEST_TSTUP PU_TEST_SNSHIFTEN PU_TEST_SNEN PU_TEST0_SNLK PU_TEST_H_PLLHRZ_P PU_TEST_L_PLLHRZ_N PU_TEST_SINGLEHIN PU_TEST_URNIN# PU_TEST0_NLOGOUT PU_TEST0_IG_T R 0.F PLE IT LOSE TO PU WITHIN " ROUTE S 0 Ohm IFFERENTIL PIR T T T T T, PU_PWRG LT_STOP# LT_RST# H_PROHOT# R 0.SUS R 00 R 0.SUS R 0K MMT0 Q0 R0 0 R 0 R 0 R 0 R.K PU_LL_PWROK PU_LTSTOP# PU_HT_RESET# TLERT#.SUS R *0 R *0 R *0 R *0 R 00_ PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO NOTE: HT TERMINTION IS REQUIRE FOR RE. x SILION ONLY. T0 T T0 T T T T T T T T T T T T T0 PU_RS_M0_LK_P PU_RS_M0_LK_N PU_RS_M0_LK_P PU_RS_M0_LK_N L RS0 L RS L RS L0 RS W RS W RS E RS U RS RS E RS MIS RS0 E RS E RS J RS J0 RS RS 0 RS G RS G RS H RS RS0 W0 RS M NPT M SOKET Processor Socket RS RS RS RS RS RS RS RS RS0 RS RS RS RS RS RS RS E0 L K K F F G G G Y Y0 G W F PU_M_RESET# PU_M_RESET# PU_RS_ISTR PU_RS_ISTR0 PU_RS_N_F_P PU_RS_N_F_N PU_RS_ORE_TYPE T T T0 T T T0 T T T T T T T T0 T T R 0 R R 00K_00 R0 *0K R0 *0K THMT THMLK Q *N00E-LF MT MLK Q *N00E-LF R0 0 MT MLK 0.U 0 00P_00 THERM_ H_THERM H_THERM SYS_SHN# R0 0R *0.U U SMLK XP SMT XN -LT -OT GN M0RMZ-RL MSOP-_- THMLK THMT THERM_LERT# Thermal Senser THMLK THMT THERM_LERT#,, SYS_SHN# SYS_SHN# SMUS SLE RESS G (N) G- (PU) R 0 0K Q MEN00E 0.0U_00 SYS_SHN# Q N00E-LF Quanta omputer Inc. PROJET : QU Size ocument Number Rev M M+ TRL & EUG Saturday, February, 00 ate: Sheet of

7 .SUS PU_ORE PU_ORE PU_ORE.SUS.SUS PU_ORE PU_ORE PU_ORE.SUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : M M+ PWR & GN Saturday, February, 00 QU Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : M M+ PWR & GN Saturday, February, 00 QU Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : M M+ PWR & GN Saturday, February, 00 QU upg0 Top iew OTTOMSIE EOUPLING L thlon Sg PROESSOR POWER N GROUN EOUPLING ETWEEN PROESSOR N IMMs PLE LOSE TO PROESSOR S POSSILE /Modify thlon M Processor Socket thlon M Processor Socket IO==>. U/._ U/._ 0P 0P 0P 0P UH GN UH GN SS H SS H SS H SS H SS H SS H SS H SS0 H0 SS J SS J SS J SS J SS J SS J SS J SS J SS J SS0 J SS J SS K SS K SS K SS K0 SS K SS K SS K SS K SS0 K0 SS K SS Y SS N SS N SS N SS N SS P SS P SS P SS0 P0 SS P SS P SS P SS P SS P0 SS P SS R SS R SS R SS0 R SS R SS R SS R SS R SS R SS T SS T0 SS T SS T SS0 T SS T SS T0 SS T SS U SS U SS U SS U SS U SS U SS0 U SS U SS U SS U SS U SS SS SS 0 SS SS SS00 SS0 SS0 0 SS0 SS0 W SS0 W SS0 W SS0 W SS0 W SS0 W SS0 W SS W SS Y SS Y0 SS Y SS W SS Y0 SS Y SS K SS K SS0 K SS K0 SS L SS L SS L SS L SS L SS L SS L SS L SS0 L SS M SS M0 SS M SS M SS M SS M SS M0 SS M SS N SS0 N SS N SS N SS N SS N SS N SS H 0.U 0.U 0 0.U 0 0.U.U_00.U_00 0 0U_00 0 0U_00 0 0U_00 0 0U_00 0 0U_00 0 0U_00 U/._ U/._ 0 U/._ 0 U/._ U/._ U/._ U/._ U/._ U/._ U/._ U/._ U/._ 0.U 0.U 0 0U_00 0 0U_00 U/._ U/._ 0.0U 0.0U U/._ U/._ 0.U 0.U 0U_00 0U_00 0U_00 0U_00 0.U 0.U 0 0.U 0 0.U 0 0U_00 0 0U_00 0P 0P 0P 0P UG GN UG GN SS SS SS SS SS SS SS SS SS SS0 SS SS SS SS SS SS SS SS SS 0 SS0 SS SS SS SS 0 SS SS SS SS SS SS0 SS SS SS SS SS SS 0 SS SS SS SS0 0 SS SS SS E SS E SS E SS E SS F SS F SS F SS0 F0 SS F SS F SS F SS F SS F0 SS F SS F SS F SS F SS G0 SS G SS H SS H SS H SS H0 SS H SS H SS H SS0 H SS H0 SS K SS K SS K SS K SS Y SS Y SS K0 SS K SS0 K SS K SS K SS K0 SS L SS SS SS SS SS SS0 SS 0 SS SS SS SS SS 0 SS SS SS SS00 SS0 0 SS0 SS0 SS0 SS0 SS0 0 SS0 E SS0 F SS0 F SS0 F SS F SS F0 SS F SS F SS F SS F SS F0 SS G SS G SS0 H SS H0 U/._ U/._ 0.U 0.U 0 0U_00 0 0U_00 U/._ U/._ U/._ U/._ 0.U 0.U.U_00.U_00 0.U 0.U U/._ U/._.U_00.U_00 0.0U 0.0U UE POWER UE POWER E0 F F G G G H H 0 E 0 E E E0 F F F F G G G0 0 G H H H J J J J J J0 0 J J K K K K K K K K 0 K L L L L0 L Y Y L L 0 L M M M M M M M M M 0 N N0 N N N N P P P P 00 P 0 P 0 P 0 R 0 R 0 R 0 R0.U_00.U_00 U/._ U/._ U/._ U/._ 0.U 0.U 0 0U_00 0 0U_00 0U_00 0U_00 UF POWER UF POWER 0 R 0 R 0 R 0 R R0 T T T T T T T T 0 T T U U0 U U U U U0 0 W W W W0 0 W W W W W0 Y Y Y Y Y 0 Y Y Y E 0 F L0 L M M N0 N P P R 0 T U W Y IO IO IO IO 0 IO IO IO IO 0 IO M IO0 M IO M IO M0 IO P IO P IO P IO P0 IO T IO T IO T IO0 T0 IO IO IO IO 0 IO Y IO Y IO Y IO Y IO F0 0 0U_00 0 0U_00 0.0U 0.0U

8 S_ M Q0 M Q M M 0 M M M Q M M M M Q M M_LKOUT M 0 M M_LKOUT# M_LKOUT M M M_LKOUT# M M M Q MREF_IM M Q0 M MREF_IM M Q M Q M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q M Q M Q M Q M_LKOUT0# M_LKOUT M_LKOUT0 M_LKOUT# M Q M Q M Q M Q S_ S0_ M Q M Q M Q M M M0 M Q MREF_IM M M M M M M M M M M M QS0 M M M M M QS M QS M QS M QS M QS M QS M QS M Q M Q M Q M Q M Q M Q0 M Q M M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q S_ S0_ M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M 0 M Q M Q M M Q M M Q0 M M M Q M Q M M M Q0 M Q M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M M M M M M0 M M M M M M M M M QS# M M QS M QS M QS M QS M QS M QS M QS0 M QS M M M Q M Q M M M Q M Q M_LKOUT# M M 0 M Q M M Q M_LKOUT0 M M Q M_LKOUT# M_LKOUT M_LKOUT M_LKOUT# M Q M Q M Q M Q M M Q M_LKOUT0# M Q M Q M Q M_LKOUT M Q M Q M Q M Q S_ S0_ S0_ SMR_REF.SUS.SUS.SUS.SUS.SUS.SUS.SUS M S#, M WE#, M S#0, M S#, M S#, M QS[0..] M_KE, M_KE, SLK0,, M_OT, M_OT, M M[0..] M S#, M WE#, M S#0, M S#, M RS#, M_LKOUT# M_LKOUT# M_LKOUT M_LKOUT M S#, M S#0, M S#, M M[0..] M RS#, M [0..], M QS[0..] M S#, M S#, M Q[0..] M [0..], M_LKOUT# M_LKOUT0# M_LKOUT M S#0, M QS#[0..] SLK0,, M_LKOUT0 M S#, M S#, M Q[0..] M_OT, M_OT0, M S#, M QS#[0..] ST0,, M_KE, M_KE0, ST0,, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RII SOIMM x Saturday, February, 00 QU Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RII SOIMM x Saturday, February, 00 QU Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RII SOIMM x Saturday, February, 00 QU.This part should not contain any substances which are specified in SS-00-.Purchase ink, paint, wire rods and molding resins only from the business partners that Sony approves as Green Partners. ES S_ : 0 (H=) (H=.) For EMI S_ : 00 /0 change N footprint (ddr-as0a-nfst-f-0 0U_00 0U_00 0.U_00 0.U_00 0.U 0.U 0.U 0.U.P.P *0.U 0 *0.U 0 0.U 0.U *0.U *0.U R K/F R K/F 0 0.U 0 0.U *0.U *0.U 0.U 0.U.U_00.U_00 R0 *.K R0 *.K 0.U 0.U *0U_00 *0U_00 R *0 R *0 0.P 0.P R *0 R *0 *0U_00 *0U_00 0.U 0 0.U U 0 0.U 0U_00 0U_00 0.U 0.U 0.U 0.U R0 K/F R0 K/F 0.U 0.U 0.U 0.U 0.P 0.P SO-IMM N RII_SOIMM_R SO-IMM N RII_SOIMM_R Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 REF RS 0 S WE 0 S0 0 S S0 S 00 S SL spd SS0 SS SS SS SS SS SS SS SS SS SS0 SS SS SS SS 0 SS SS SS SS SS SS SS SS SS SS0 SS SS SS SS SS SS SS SS SS0 0 SS SS SS SS SS0 SS SS SS SS SS SS SS SS 0 SS QS0 QS QS QS QS QS QS QS OT0 OT SS SS SS SS 0 SS SS SS SS SS0 GuidePin 0 GuidePin 0 0.U 0.U 0.U 0 0.U 0 0.U 0.U R *.K R *.K R 0 R 0 0.U 0.U 0.U 0.U 0.U 0.U R 0 R 0 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U 00 0.U 00 0.U R 0 R 0 0.U 0.U U U.P.P 0.U 0.U R.K R.K R *.K R *.K SO-IMM N RII_SOIMM_R SO-IMM N RII_SOIMM_R Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 REF RS 0 S WE 0 S0 0 S S0 S 00 S SL spd SS0 SS SS SS SS SS SS SS SS SS SS0 SS SS SS SS 0 SS SS SS SS SS SS SS SS SS SS0 SS SS SS SS SS SS SS SS SS0 0 SS SS SS SS SS0 SS SS SS SS SS SS SS SS 0 SS QS0 QS QS QS QS QS QS QS OT0 OT SS SS SS SS 0 SS SS SS SS SS0 GuidePin 0 GuidePin 0 0.U 0.U *0.U *0.U

9 SMR_TERM, M_KE0, M_KE, M_KE, M_KE R _ R _ R _ R _, M_OT0, M_OT, M_OT, M_OT R _ R _ R _ R0 _, M S#0, M S#, M S#, M WE#, M S#, M RS# R _ R _ R _ R0 _ R _ R _ SMR_TERM.SUS SMR_TERM, M S#0, M S#, M S# R0 _ R _ R0 _ *0U_00 *0U_00, M WE#, M S#, M RS# R0 _ R0 _ R _ 0.U 0 0.U 0.U 0.U 0.U 0 0.U 0.U 0.U 0.U *0.U 0 *0.U 0.U 0.U 0.U 0.U 0.U *0.U 0.U 0 0.U 0.U *0.U 0.U 0 0.U 0.U *0.U 0.U 0 0.U R _, M S#0 0.U R _, M S# 0.U R _, M S# 0.U R0 _, M S# 0.U 0.U R _, M S#0 0.U R0 _, M S# 0.U R00 _, M S# 0.U R _, M S# 0.U 0.U 0.U, M [0..] 0 0.U M R _ 0.U M 0 R _ 0.U M 0 RP 00-X 0.U M M RP 00-X M M RP 00-X M M RP 00-X M M RP0 00-X M M RP 00-X M M M RP 00-X, M [0..] M M 0 M M M M M M M M M M M 0 M M M RP 00-X RP 00-X RP 00-X RP 00-X RP 00-X RP 00-X R0 _ R _ RP 00-X Size ocument Number Rev RII TERMINTION Quanta omputer Inc. PROJET : QU ate: Saturday, February, 00 Sheet of

10 0 U HT_PKG HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT0_P HT_OUT0_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT_P HT_OUT_N HT_OUT0_P HT_OUT0_N HT_LKOUT_P HT_LKOUT_N HT_LKOUT0_P HT_LKOUT0_N HT_TLOUT0_P HT_TLOUT0_N R0.R_ HT_RXLP R.R_ HT_RXLN R R R R U U U U W W0 0 0 Y T R U U U W W Y W P P HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RX0P HT_RX0N HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RX0P HT_RX0N HT_RXLKP HT_RXLKN HT_RXLK0P HT_RXLK0N HT_RXTLP HT_RXTLN HT_RXLP HT_RXLN PRT OF HYPER TRNSPORT PU I/F HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TX0P HT_TX0N HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TX0P HT_TX0N HT_TXLKP HT_TXLKN HT_TXLK0P HT_TXLK0N HT_TXTLP HT_TXTLN HT_TXLP HT_TXLN P P P P M M M M L L G G J0 J F F N N L M K K J K G H F F E F E E L L J J N P HT_TXLP HT_TXLN HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN0_P HT_IN0_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN_P HT_IN_N HT_IN0_P HT_IN0_N HT_LKIN_P HT_LKIN_N HT_LKIN0_P HT_LKIN0_N HT_TLIN0_P HT_TLIN0_N R 00R_ RS0M Quanta omputer Inc. PROJET : QU Size ocument Number Rev RS0M HT LINK I/F Saturday, February, 00 ate: Sheet of 0

11 U 0 PIE_RXP[..0] 0 PIE_RXN[..0] 0 PIE_TXP[..0] 0 PIE_TXN[..0] PIE_RXP[..0] PIE_RXN[..0] PIE_TXP[..0] PIE_TXN[..0] 0 PIE_RXP0 0 PIE_RXN0 0 PIE_RXP 0 PIE_RXN 0 PIE_RXP 0 PIE_RXN 0 PIE_RXP 0 PIE_RXN 0 PIE_RXP 0 PIE_RXN 0 PIE_RXP 0 PIE_RXN 0 PIE_RXP 0 PIE_RXN 0 PIE_RXP 0 PIE_RXN 0 PIE_RXP 0 PIE_RXN 0 PIE_RXP 0 PIE_RXN 0 PIE_RXP0 0 PIE_RXN0 0 PIE_RXP 0 PIE_RXN 0 PIE_RXP 0 PIE_RXN 0 PIE_RXP 0 PIE_RXN 0 PIE_RXP 0 PIE_RXN 0 PIE_RXP 0 PIE_RXN GPP_RX0P_LN GPP_RX0N_LN GPP_RXP_WLN GPP_RXN_WLN GPP_RXP_MINIR GPP_RXN_MINIR G G J J J J L L L L M M M M P P P P R R R R U U W W Y Y W E 0 E0 Y GFX_RX0P GFX_RX0N GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RX0P GFX_RX0N GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GFX_RXP GFX_RXN GPP_RX0P GPP_RX0N GPP_RXP GPP_RXN GPP_RXP GPP_RXN PRT OF PIE I/F GFX PIE I/F GPP GFX_TX0P GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TX0P GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GPP_TX0P GPP_TX0N GPP_TXP GPP_TXN GPP_TXP GPP_TXN J GFX_TXP0 H GFX_TXN0 K GFX_TXP K GFX_TXN K GFX_TXP L GFX_TXN L GFX_TXP L GFX_TXN N GFX_TXP N GFX_TXN P GFX_TXP P GFX_TXN P GFX_TXP R GFX_TXN R GFX_TXP R GFX_TXN T GFX_TXP U GFX_TXN GFX_TXP GFX_TXN GFX_TXP0 W GFX_TXN0 W GFX_TXP W GFX_TXN Y GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN E GFX_TXP E GFX_TXN GPP_TX0P_ GPP_TX0N_ GPP_TXP_ E GPP_TXN_ GPP_TXP_ E GPP_TXN_ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ *0.U/0/ 0.U/0/ 0.U/0/ 0.U/0/ 0.U/0/ 0.U/0/ 0.U/0/ PIE_TXP0 0 PIE_TXN0 0 PIE_TXP 0 PIE_TXN 0 PIE_TXP 0 PIE_TXN 0 PIE_TXP 0 PIE_TXN 0 PIE_TXP 0 PIE_TXN 0 PIE_TXP 0 PIE_TXN 0 PIE_TXP 0 PIE_TXN 0 PIE_TXP 0 PIE_TXN 0 PIE_TXP 0 PIE_TXN 0 PIE_TXP 0 PIE_TXN 0 PIE_TXP0 0 PIE_TXN0 0 PIE_TXP 0 PIE_TXN 0 PIE_TXP 0 PIE_TXN 0 PIE_TXP 0 PIE_TXN 0 PIE_TXP 0 PIE_TXN 0 PIE_TXP 0 PIE_TXN 0 GPP_TX0P_LN GPP_TX0N_LN GPP_TXP_WLN GPP_TXN_WLN GPP_TXP_MINIR GPP_TXN_MINIR Place these caps close to connector GPP_RXP GPP_RXN GPP_TXP GPP_TXN _RX0P _RX0N W W S_RX0P S_RX0N PIE I/F S S_TX0P S_TX0N E 0 _TX0P TX0N_ 0.U/0/ 0.U/0/ _TX0P _TX0N _RXP _RXN S_RXP S_RXN S_TXP S_TXN _TXP TXN_ 0.U/0/ 0.U/0/ _TXP _TXN _RXP _RXN W W S_RXP S_RXN S_TXP S_TXN E _TXP TXN_ 0.U/0/ 0.U/0/ _TXP _TXN _RXP _RXN S_RXP S_RXN S_TXP S_TXN E _TXP TXN_ 0.U/0/ 0.U/0/ _TXP _TXN R R *0K_ *.K_ PE_ISET(PE_LI) PE_PL(PE_LRP) PE_TXISET(N) PE_NL(PE_LRN) E R R R_ K PKG RS0M Quanta omputer Inc. PROJET : QU Size ocument Number Rev RS0M PIE LINK I/F Saturday, February, 00 ate: Sheet of

12 HTP==>.m(min)/.0m(MX). HTP L. R 0R_ I I==>0m(min)/0m(MX) 0ohm_ *0U/./.U/0/.U/0/ PLL==>.m(min)/.m(MX). PLL L 0ohm_ 0 *0U/./.U/0/ Q==>0.m(min)/0.m(MX). Q L0 0ohm_ *0U/./ _N==>.m(min)/.m(MX) PLL.U/0/ N Thermal Senser PU.U/0/ _N L ohm,00m.u/0/ *0.U//. R0 R 0K_ 0K_ LT_STOP#_N, LT_STOP# Q MMT0 Q PLL HTP N_RST#, N_PWRG LLOW_LTSTOP HTREFLK N_OS NSR_LKP NSR_LKN SLINK_LKP SLINK_LKN R0 *0.U// *K_ MREQ# N_LS_LK N_LS_T N_THERM N_THERM R R R R R0 _N I T T T0 T0 T0 T0 T T T T R L 0ohm,00m R R N_THERM N_THERM T T STRP_T R.K_ 0K_ T_SWITH PLL *K_FT_GPIO0 LO_ROM# *K_FT_GPIO *K_FT_GPIO *K_FT_GPIO *K_FT_GPIO *0R_ R_ STRP_T U G SSN H SSN 0 I 0 SSI Q SSQ 0 Y OMP E RE F GREEN G LUE SYN HSYN 0 PLL 0 PLLSS HTP HTPSS RS0M RT/TOUT 0 SYSRESET# LT_STOP#_N POWERGOO LTSTOP# LLOW_LTSTOP HTTSTLK HTREFLK RSET SL S TLKIN PLL PM PWR OSIN OSOUT(PLL) F GFX_LKP E GFX_LKN G S_LKP G S_LKN FT_GPIO0 FT_GPIO FT_GPIO FT_GPIO FT_GPIO FT_GPIO MREQ# I_LK I_T THERMLIOE_P THERMLIOE_N TMS_HP _T TESTMOE STRP_T PRT OF LOKs MIS. EUG LS TXOUT_L0P TXOUT_L0N TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_U0P TXOUT_U0N TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXLK_LP TXLK_LN TXLK_UP TXLK_UN LP LPSS LR_ LR_ LR_ LR_ LSSR LSSR LSSR LSSR LSSR LSSR LSSR LSSR LS_IGON LS_LON LS_LEN EUG_ EUG_ EUG_0 EUG_ EUG_0 EUG_ EUG_ EUG_ EUG_ TXOUT_L0P R *0 TXOUT_L0N R0 *0 TXOUT_LP R *0 TXOUT_LN R *0 H TXOUT_LP R *0 G TXOUT_LN R *0 TXOUT_LP R *0 E TXOUT_LN R *0 TXOUT_U0P R *0 TXOUT_U0N R *0 TXOUT_UP R *0 TXOUT_UN R *0 TXOUT_UP R0 *0 TXOUT_UN R *0 TXOUT_UP R *0 TXOUT_UN R *0 TXLK_LP TXLK_LN TXLK_UP TXLK_UN R *0 E R *0 H R *0 G R *0 LP==>.m(min)/.m(MX) E F F E G F E E E E IGON LON T N_TXLOUT0+ N_TXLOUT0- N_TXLOUT+ N_TXLOUT- N_TXLOUT+ N_TXLOUT- N_TXLOUT+ N_TXLOUT- N_TXUOUT0+ N_TXUOUT0- N_TXUOUT+ N_TXUOUT- N_TXUOUT+ N_TXUOUT- N_TXUOUT+ N_TXUOUT- N_TXLLKOUT+ N_TXLLKOUT- N_TXULKOUT+ N_TXULKOUT- LR==>0.m(min)/.m(MX) L LR==>.m(min)/.m(MX) T0 T0 T0 T T T0 T T0 T0 0.U// 0 0.U//.U/./ R 0.U// 0R_ LP L0. 0ohm_.U/./ GN_LPSS. 0ohm_ L 0ohm_ R.U/./ GN_LSSR 0R_ GN_LPSS 0.U// *0.U// U 00P/0/ THERM_N_ N_THERM N_THERM XP XN SMLK SMT -LT SYS_SHN# -OT GN M0RMZ-R MSOP-_- /0 change U P/N:L00000 R 0K_ LO_ROM#: LO ROM STRP ENLE THMLK R *0K_ STRP_T THMT High, LO ROM STRP ISLE R 0K_ T_SWITH THERM_LERT#,, Low, LO ROM STRP ENLE / R to link (Therm_lert# must push Hi) Quanta omputer Inc. PROJET : QU Size ocument Number Rev RS0M PLL & EIO I/F ate: Saturday, February, 00 Sheet of

13 ... _PKG _PKG R O PLL LT_RUN.. HT_PKG _PKG N_ORE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RS0M POWER Saturday, February, 00 QU Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RS0M POWER Saturday, February, 00 QU Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RS0M POWER Saturday, February, 00 QU 0 ohm() For EMI : ecrease 00MHz frequency _HT==>.m(min)/0.0m(MX) _==>0.0m(min)/0.m(MX) _==>.m(min)/.0m(mx) R==>0.m(min)/0.m(MX) R==>.m(min)/.m(MX) PLL==>.m(min)/.m(MX) ==>.m(min)/.0m(mx) ==>.m(min)/.m(mx) L 0ohm,00m L 0ohm,00m U/0/ U/0/ 0.U// 0.U// U/0/ U/0/ U/0/ U/0/ 0 U/0/ 0 U/0/ L ohm,00m L ohm,00m U/0/ U/0/.U/0/.U/0/ 0U/./ 0U/./ U/0/ U/0/ U/0/ U/0/ L 0R_ L 0R_ L 0ohm,00m L 0ohm,00m U/0/ U/0/ SS SS U/0/ U/0/ U/0/ U/0/ U/0/ U/0/ U/0/ U/0/ GROUN PR OF UE RS0M GROUN PR OF UE RS0M SS SS F SS SS E SS G SS Y SS P SS R SS E SS0 M SS J SS G SS J SS L SS L SS L0 SS L SS M SS M0 SS0 M SS M SS N SS N SS L SS P SS P0 SS P SS R SS0 R SS R0 SS W SS Y SS SS U0 SS H SS W SS Y SS SS0 SS G SS SS SS SS SS SS F SS SS SS H SS G SS0 J SS H SS J SS F SS L SS M SS M SS J SS0 P SS T SS N SS R SS U SS T SS U SS U SS0 Y SS W SS SS Y SS Y SS Y SS R SS SS SS0 SS SS SS SS 0 SS G SS Y SS SS P SS E SS E0 SS M SS Y SS Y SS SS R SS SS E SS T SS T SS0 E SS H SS SS F SS SS M SS SS H SS SS M SS R SS 0U/./ 0U/./ 0U/./ 0U/./ U/0/ U/0/ U/0/ U/0/ L 0ohm,00m L 0ohm,00m L 0R_ L 0R_ U/0/ U/0/ 0U/./ 0U/./ 0 U/0/ 0 U/0/ SS SS U/0/ U/0/ U/0/ U/0/ 0.U// 0.U// L 0ohm, L 0ohm, U/0/ U/0/ *U/0/ *U/0/.U/./.U/./ 00U/./ 00U/./ POWER PRT OF U RS0M POWER PRT OF U RS0M _HT E _HT _HT _HT _HT E _HT Y _HT W _HT _HT _HT0 _HT 0 _HT _HT _HT _HT E _ J _ J PLL_ E G _ E E M _ F _ L _0 E W _ L _ L _ L _ M _ R _ M _ N _ N _ N _0 J _ H _ P _ P _ R _ E U PLL_ F _ R R_ R_ E SSPLL_ F SSPLL_ G R_ R_ R_ E _ U _ U _0 P _ L _ J _ 0 _ G0 0 _0 _ HT_PKG _PKG M _PKG _ E _ U _ U SS SS L 0ohm,00m L 0ohm,00m 0U/./ 0U/./.U/0/.U/0/ 0U/./ 0U/./ 0U/./ 0U/./ 0 U/0/ 0 U/0/ 0 00U/./ 0 00U/./ U/0/ U/0/ U/0/ U/0/ *U/0/ *U/0/ U/0/ U/0/ U/0/ U/0/ 0.U// 0.U// 0U/./ 0 0U/./ 0 0.U// 0.U// 0.U// 0.U// 0 U/0/ 0 U/0/

14 R 0 LINK_RST# R PILK0_R PLK_R N_RST# G0 R R 0 _RST# PILK0 U PILK_R PLK_ PLK_R, 0, PIE_RST# Part of R0 R0 0 PILK T PILK_R PLK_E PLK_ LP_RST# SSRLKP J PIE_RLKP PILK U R PILK_R PILK_ PLK_E For EMI SSRLKN J R PIE_RLKN PILK PILK_R PILK PILK_ PLK_R 0.U _RX0P_ PILK W R 0P PILK_R PILK PLK RX0P P 0P 0.U _RX0N_ PIE_TX0P PILK U T PILK_R PLK_E _RX0N P R 0P 0 0.U _RXP_ PIE_TX0N PILK S_SPIF_R PILK _RXP M T 00 0.U _RXN_ PIE_TXP SPIF_OUT/PILK/GPIO T PILK _RXN M 0P 0 0.U _RXP_ PIE_TXN PIRST# RXP K 0 0.U _RXN_ PIE_TXP PIRST# J _RXN K 0.U _RXP_ PIE_TXN _RXP H [0..], 0.U _RXN_ PIE_TXP 0 _RXN H PIE_TXN 0/ROM W /ROM Y _TX0P T PIE_RX0P /ROM W PIRST# TX0N T /ROM W R0 PIE_RX0N PIRST# _TXP T PIE_RXP /ROM _TXN T PIE_RXN /ROM Y _TXP M PIE_RXP /ROM _TXN M PIE_RXN /ROM R0 _TXP M PIE_RXP /ROM.K Stuff L in -test _TXN M PIE_RXN /ROM 0 PIE_P R PIE_LRP 0/ROM T E R.0K PIE_LRN PIE_LRP /ROM J PIE_R E PIE_LRN /ROM R 0 PIE_LI /ROM E PIE_LI /ROM E PIE_PWR PIE_P==>.m(MX) L 0ohm_ /ROM U T-P--T-0-P PIE_P /ROM0 /ROM J U PIE Power 0 PIE_PSS /ROM PU 0U U 0.U /ROM H 0 RT F PIE_R_ 0/ROM F PIE_R_ /ROM J F PIE_R_ /ROM G R PIE_R_ /ROM H G RT *0R PIE_R PIE_R_ PIE_PWR G PIE_R_ H PIE_R==>.0m(MX) G U_00 L PIE_R_ J PIE_R_ H Modify 0 for EMI J 0ohm_ PIE_R_ L G 0 0 PIE_R_0 L 0 U 0U 0U 0.U 0.U U U U 0 R PIE_R_ JP 0.U U U L G 0_00 PIE_R_ N PIE_R_ E0#/ROM0 /E0# E#/ROM F /E# E#/ROMWE# J /E# PU PU _S PIE_PWR PIE_PWR /E# T R E# G PQ O0 FRME# 0mil *0 FRME# P* ESEL#/ROM0 H ESEL# PIEPWR_ON IRY# R IRY# G R0 R TRY# R0-SOKET 00K_00 R0 TRY#/ROMOE# 0R M_ PR 0R_ PR/ROM F STOP# Y STOP# 0.U PERR# G PERR# SERR# PIE_PWR_ SERR# REQ0# J REQ0# REQ# REQ# E T REQ# *SS REQ# G T REQ# T PIE_PWR_ REQ#/GPIO0 H REQ# R REQ#/GPIO H T GNT0# GNT# GNT0#,,,0, MINON Q0 GNT0# T0 MEN00E GNT# F GNT# GNT# H T GNT# 0K T Q GNT#/GPIO Q GNT# T 0 MEN00E GNT#/GPIO G MEN00E LKRUN# /Modify T 0.U LKRUN# G LOK# F PI_LOK# LKRUN# T0 INTE# INTE#/GPIO INTE# INTF# PU_PWR_S INTF#/GPIO F INTF# INTG# K_X INTG#/GPIO F T INTH# X INTH#/GPIO F T R.K U0 S00 S xmm PI EXPRESS INTERFE PI INTERFE PI LKS - normal - clear MOS R *0M Y.KHZ R 0M P K_X K_X P PU_PWRG, LT_STOP# PU_SI PU_SI LLOW_LTSTOP LT_RST# R0 0K T T0 T T K_X R0 0 T T T T X XTL PU_PG/LT_PG W INTR/LINT0 W NMI/LINT W INIT# SMI# SLP#/LT_STP# IGNNE#/SI 0M#/SI Y FERR# STPLK#/LLOW_LTSTP H PU_STP#/PSLP_# PSLP_O#/GPIO W PRSLPR LT_RST#/PRSTP#/PROHOT# S00 PU LP L0 L L L LFRME# LRQ0# LRQ#/GNT#/GPIO MREQ#/REQ#/GPIO SERIRQ RTLK RT_IRQ#/GPIO T RT_GN RT G G H H F J H W F F E LP_RQ0# LP_RQ# R *0 RT_LK 0 U L0, L, L, L, LFRME#, T T0 MREQ# SERIRQ, T T RT SERIRQ MREQ# R *0K R *0K 0 *P *0.U /0 hange Y footprint like Y (XTL-_X_-_X_) Quanta omputer Inc. PROJET : QU Size ocument Number Rev S00 PIE/PI/PU/LP ate: Saturday, February, 00 Sheet of

15 S_OSIN SLK ST S_THERMTRIP# GPM# S_STTE SWI# SUS_STT# NSWON# SUS# SUS# SI# SLK0 ST0 L_ON GPIO_S0 KSMI# RIN# GTE0 GPIO_S0 SUS 0 Z_ITLK_UIO 0 Z_SOUT_UIO 0 Z_SIN0 0 Z_SYN_UIO 0 Z_RESET#_UIO R * R.K R0.K R.K R *0K R *0K R *0K R *0K R *0K R *.K R *.K R *0K R0.K R0.K R0 0K R00 *.K R0 *0K R *0K R *0K R *0K R 0K R 0K R 0K R 0K R *0K R0 *0K R00 *0K R0 *0K R0 *0K R0 *0K *0P +.LW US_OP# US_OP# US_OP# US_OP# US_OP# US_OP# US_OP# US_OP# US_OP# US_OP0# Z_ITLK Z_SOUT Z_SIN Z_SIN0 Z_SYN Z_RST# GTE0 RIN# SWI# KSMI#, PIE_WKE# T S_THERMTRIP# PI_PME# SI# SUS# SUS# NSWON# SPWROK RSMRST# S_OSIN IOS_WP# T T T T L_ON 0 SPEKER,, SLK0,, ST0 SLK ST T T T T /0 change US Power from cc to SUS R 0 *P R0 R R * R R 0K R 0.U 0 0.U T T T T US_OP# US_OP# US_OP# US_OP# US_OP# US_OP0# T _SOUT T T0 T00 T PI_PME# SI# SUS# SUS# NSWON# SUS_STT# S_TEST S_TEST S_TEST0 GTE0 RIN# SWI# KSMI# S_STTE GPM# GPM#_S S_THERMTRIP# GPIO0_S0 GPIO_S0 GPIO_S0 GPIO_S0 L_ON GPIO_S0 SLK0 ST0 SLK ST GPIO_S0 GPIO_S0 GPIO0_S0 GPIO_S US_OP# US_OP# US_OP# US_OP# US_OP# US_OP# US_OP# US_OP# US_OP# US_OP0# Z_ITLK Z_SOUT Z_SIN Z_SYN Z_RST# Z_SIN0 U0 E RSMRST# OS / RST M_OS ST_IS0#/GPIO0 ROM_S#/GPIO GHI#/ST_IS#/GPIO W_PWRG/GPIO SMRTOLT/ST_IS#/GPIO SHUTOWN#/GPIO SPKR/GPIO SL0/GPO0# S0/GPO# SL/GPO# F S/GPO# _SL/GPIO _S/GPIO SSMUXSEL/ST_IS#/GPIO0 LL#/GPIO S00 S xmm PI_PME#/GEENT# Part of RI#/EXTENT0# F SLP_S# SLP_S# E PWR_TN# PWR_GOO SUS_STT# F TEST E TEST G TEST0 F G0IN G KRST# LP_PME#/GEENT# LP_SMI#/EXTENT# S_STTE/GEENT# F SYS_RESET#/GPM# E WKE#/GEENT# LINK/GPM# G SMLERT#/THRMTRIP#/GEENT# ZLI US O GPIO US_O#/SLP_S/GPM# US_O#/Z_OK_RST#/GPM# US_O#/GEENT# US_O#/GEENT# US_O#/R_RST#/GPM# US_O#/GPM# US_O#/GPM# US_O#/GPM# US_O#/GPM# US_O0#/GPM0# N Z_ITLK M Z_SOUT K Z_SIN/GPIO L Z_SYN K Z_RST# L _ITLK/GPIO L _SOUT/GPIO L Z_SIN0/GPIO J Z_SIN/GPIO J Z_SIN/GPIO M _SYN/GPIO0 L _RST#/GPIO E N N N E N N T N N N PI / WKE UP EENTS US INTERFE US PWR USLK US_ROMP US_TEST US_TEST0 US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP+ US_HSM- US_HSP0+ US_HSM0- TX_0 TX_ TX_ TX_ TX_ RX_0 RX_ RX_ RX_ RX_ SS SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_0 SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_0 SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_ SS_US_0 SS_US_ SS_US_ SS_US_ 0 H G E E G H E E G H G H E G H 0 0 E E F F F F F F F G G H H J J J J J J US_ROMP R0 * *0P R USLK.K_00F T T T T USP+ T T00 USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP0+ USP0- _US 0U_00.U_00 S_TEST0 S_TEST S_TEST US power 0 0.U U R 0.U RX==>0.m(MX) TX==>.m(MX) 0 U 0U_00 U U U 0.U 0.U 0 +._ ==>0.m(MX) L R R 0.U *.K *.K *.K L FM0-0.U 0.U +.LW R0 *0K +.LW LMPGSN_ R *0K R *0K S U// 0 0.U// 0 0.U// 0 0.U// 0 0.U// /0 add xxxxxxxx Quanta omputer Inc. PROJET : QU Size ocument Number Rev S00 PI/GPIO/US/ ate: Saturday, February, 00 Sheet of

16 / change Y P/N to meet L.(G000) ST_X ST_X PLL_ST==>.m(MX) XTL_ST==>.m(MX) _ST==>.m(MX) /0 change Y P/N:G000 P P Y Mhz R 0M ST_TXP0 ST_TXN0 ST_RXN0 ST_RXP0 ST_TXP ST_TXN ST_RXN ST_RXP ST_LE# PLL_T XTL_T _ST ST Power L0 LMPGSN S L LMPGSN_ 0.0U 0.0U 0.0U 0.0U T T T T0 T T T T R U U K/F XTL_T PLL_T ST_TXP0_ ST_TXN0_ ST_TXP_ ST_TXN_ U U ST_L U0 H ST_RX- J ST_RX+ H ST_TX0+ J ST_TX0- H0 ST_RX0- J0 ST_RX0+ H ST_TX+ J ST_TX- H ST_RX- J ST_RX+ H ST_TX+ H ST_TX- H ST_RX- J ST_RX+ J ST_TX+ H ST_TX- F ST_L ST_X ST_X ST_X ST_X ST_T#/GPIO PLL_ST_ J0 PLL_ST_ XTL_ST E _ST_ E _ST_ E _ST_ E _ST_ F _ST_ F _ST_ G _ST_ G _ST_ H _ST_ H _ST_0 J _ST_ J _ST_ J _ST_ J _ST_ J _ST_ SS_ST_ SS_ST_ SS_ST_ SS_ST_ SS_ST_ SS_ST_ SS_ST_ SS_ST_ SS_ST_ E SS_ST_0 E SS_ST_ F SS_ST_ F SS_ST_ F SS_ST_ F SS_ST_ G SS_ST_ G SS_ST_ G SS_ST_ G SS_ST_ G SS_ST_0 G SS_ST_ G SS_ST_ G SS_ST_ G0 SS_ST_ G SS_ST_ H0 SS_ST_ H SS_ST_ S00 S xmm SERIL T Part of SERIL T POWER SPI ROM HW MONITOR T /00 IE_IORY IE_IRQ IE_0 IE_ IE_ IE_K# IE_RQ IE_IOR# IE_IOW# IE_S# IE_S# IE_0/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO0 IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_0/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO0 SPI_I/GPIO SPI_O/GPIO SPI_LK/GPIO SPI_HOL#/GPIO SPI_S#/GPIO LN_RST#/GPIO ROM_RST#/GPIO FNOUT0/GPIO FNOUT/GPIO FNOUT/GPIO FNIN0/GPIO0 FNIN/GPIO FNIN/GPIO TEMP_OMM TEMPIN0/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO IN0/GPIO IN/GPIO IN/GPIO IN/GPIO IN/GPIO IN/GPIO IN/GPIO IN/GPIO0 SS Y W W E F G H J J H G G F F E J J G G G G M T N P W P P P T T L M M P M N M T T T T T T T T T T T T0 T T T T T T T T0 T T T T T T T S00_FOUT0 TEMP_OMM HWM_GN T T T T T _HWM -LN_RST R *0K T T T T T R0 0 T T T T T T T T T T T 0.U L L TLERT# 0.uF_. R0 0 *0R_00m 0R_00m PU ==>0m(G)/0.m(MX) S00 _S L FM0- _ST 0U_00 0U_00 0.U 0.U 0.U 0.U 0.U U/./ 0 U/0/ U/0/ Quanta omputer Inc. PROJET : QU Size ocument Number Rev S00 H ate: Saturday, February, 00 Sheet of

17 +.LW PU ST_ON / R for HW Lose Q *TEU R 0 R *0K *0.U out =0.(+R/R) = 0. (+0K/0K) =. 0U_00 GN IN PLI-TRL Q * NTR0PTG U SHN O SET R R *U R 0K_ R 0K_ *0U 00 +.LW 0U_00 R *0R_ Q *N00E-LF +.LW. R 0 R00 R 0 R00 +.LW 0.U 0U 00 PU_PWR ==>.m(mx) _S 0 0U 00 0.U 0U 00 _REF R 0 0U U U +.LW.SUS. _S Q==>.m(MX) _S S_. ==>0.m(MX) US_PHY_. ==>.m(mx) ==>.m(mx) S_.==>.0m(MX) 0U 00 U PU_PWR_S R *0 R 0 K_. ==>.m(g)/.m(mx) K_. ==>.m(g)/.m(mx) SS + 0 0U/. K/F U 0U 00 0.U U U U 0 U 0.U _REF ==>0.m(MX) U 0.U L LMPGSN_ L LMPGSN_ U U U 0.U _REF *0.U U 0 0.U U 0.U 0.U U U/./ 0.U.U _REF K_. K_..U U U/./ 0.U U0 S00 S xmm Q_ SS_ Q_ SS_ Q_ Part of SS_ Q_ SS_ L Q_ SS_ L Q_ SS_ M Q_ SS_ P Q_ SS_ P Q_ SS_ T Q_0 SS_0 Q_ SS_ W Q_ SS_ W Q_ SS_ W Q_ SS_ W Q_ SS_ Q_ SS_ Q_ SS_ Q_ SS_ Q_ SS_ Q_0 SS_0 Q_ SS_ E Q_ SS_ E Q_ SS_ E Q_ SS_ H Q_ SS_ J Q_ SS_ J Q_ SS_ J Q_ SS_ SS_ M _ SS_0 M _ SS_ N _ SS_ N _ SS_ N _ SS_ R _ SS_ R _ SS_ U _ SS_ U _ SS_ U _0 SS SS_0 _ SS_ SS_ S_._ SS_ S_._ SS_ F S_._ SS_ J S_._ SS_ J S_._ SS_ K S_._ SS_ SS_ G S_._ SS_0 H S_._ SS_ H S_._ SS_ H S_._ SS_ SS_ US_PHY_._ SS_ US_PHY_._ SS_ US_PHY_._ SS_ 0 US_PHY_._ US_PHY_._ PIE_SS_ PIE_SS_ PU_PWR PIE_SS_ PIE_SS_ E _REF PIE_SS_ PIE_SS_ K_. PIE_SS_ PIE_SS_ K_. PIE_SS_ PIE_SS_0 SSK PIE_SS_ PIE_SS_ PIE_SS_ PIE_SS_ PIE_SS_ PIE_SS_ PIE_SS_0 PIE_SS_ PIE_SS_ PIE_SS_ PIE_SS_ PIE_SS_ PIE_SS_ PIE_SS_ PIE_SS_ PIE_SS_ PIE_SS_ PIE_SS_0 U PIE_SS_ PIE_SS_ T PIE_SS_ PIE_SS_ T PIE_SS_ PIE_SS_ T PIE_SS_ PIE_SS_ T PIE_SS_0 PIE_SS_ T PIE_SS_ PIE_SS_ P PIE_SS_ PIE_SS_ S00 POWER 0 E F F G J J L L M M M M N N P P P R R R T T U U W W Y E E G J J J F G G G H J J J K L L L L L M M M N N P P P P P Quanta omputer Inc. PROJET : QU Size ocument Number Rev S00 POWER/EOUPLING ate: Saturday, February, 00 Sheet of

18 REQUIRE STRPS R *.K R R R R *0K 0K *0K 0K _SOUT PILK PILK, PLK_R PLK_ S00 Internal P 0K R *0K R 0K R *0K R 0K R *0K PLK_R PLK SOUT PILK PILK PI_LK0 PI_LK PULL HIGH USE EUG STRPS USE INT. PLL PU IF=K EFULT ROM TYPE: H, H = PI ROM H, L = SPI ROM PULL LOW IGNORE EUG STRPS EFULT USE EXT. MHZ EFULT PU IF=P L, H = LP ROM EFULT L, L = FWH ROM EUG STRPS R R R R R R 0K 0K 0K 0K 0K 0K,,,,,, R *.K R *.K R *.K R0 *.K R *.K R *.K PI_ PI_ PI_ PI_ PI_ PI_ PULL HIGH USE LONG RESET EFULT USE PI PLL EFULT USE PI LK EFULT USE IE PLL EFULT USE EFULT PIE STRPS EFULT OOTFILTIMER ISLE EFULT PULL LOW USE SHORT RESET YPSS PI PLL YPSS PI LK YPSS IE PLL USE EEPROM PIE STRPS OOTFILTIMER ENLE Quanta omputer Inc. PROJET : QU Size ocument Number Rev S00 STRPS ate: Saturday, February, 00 Sheet of

19 KLIGHT ONTROL L ONNETOR L R.K_ R.K_ ON, N_PWRG L_ON LON EXT_LS_LON R R R 0K_ SS SS *0R_ 0R_ R *0K_ R0 *0K_ 0.U// ISPON U0 TSH0FU *000P/0/ LS_LK EMI 0 *000P/0/ LS_T *000P/0/ SHIEL GN SHIEL GN SHIEL GN SHIEL GN TXULKOUT+ TXULKOUT- TXUOUT0+ TXUOUT0- TXUOUT+ TXUOUT- TXUOUT+ TXUOUT- TXUOUT+ TXUOUT L_ON0-00x-0p-ldv TXLOUT0+ TXLOUT0- TXLOUT+ TXLOUT- TXLLKOUT+ TXLLKOUT- TXLOUT+ TXLOUT- TXLOUT+ TXLOUT- SHIEL GN SHIEL GN SHIEL GN SHIEL GN L EXT_ISP_ON /0---del R0,R(white screen issue) /0---exchange, to R,R(white screen issue) /---del R, R(HW LOSE), N_PWRG Q0 TEU IGON_R IGON PU L N_PWRG_ PNEL ONTROL hange F= fuse (P/N:K00WFU00)(L INRUSH URRENT=) Q MEN00E SUS 0.U// SUS IGON_R /0 change the footprint to SOT_-_- Q MEN00E R 0K_ R R 0 00P/0/ 0R_ *0R_ R R_ R 0K_ Q MEN00E R *0K_ MER POWER F0 F *POLY_SWITH POLY_SWITH f-_x_-_ f-_x_-_ K0TPU0 K0TPU0 Q *O0 Q IN IN _POWER + OUT T0IGU--T GN ON/OFF GN 0U/0/ 000P/0/ 0.U// F _PWR R0 L 0U/./ 0.U// FOR EMI GPU_LS_T GPU_LS_LK GPU_TXLOUT0- GPU_TXLOUT0+ GPU_TXLOUT- GPU_TXLOUT+ GPU_TXLOUT- GPU_TXLOUT+ GPU_TXUOUT0- GPU_TXUOUT0+ GPU_TXUOUT- GPU_TXUOUT+ GPU_TXUOUT- GPU_TXUOUT+ GPU_TXLLKOUT- GPU_TXLLKOUT+ GPU_TXULKOUT- GPU_TXULKOUT+ GPU_TXLOUT- GPU_TXLOUT+ GPU_TXUOUT- GPU_TXUOUT+ N 0-000G ISPON J- IN_L R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R0 0 R 0 R 0 R 0 R0 0 R 0 MI_LK _PWR LS_T LS_LK TXUOUT0- TXUOUT0+ TXLOUT0- TXLOUT0+ TXUOUT- TXUOUT+ TXLOUT- TXLOUT+ TXLLKOUT- TXLLKOUT+ TXUOUT- TXUOUT+ TXLOUT- TXLOUT+ TXULKOUT- TXULKOUT+ TXLOUT- TXLOUT+ TXUOUT- TXUOUT+ WE M MOULE *P/0/ 0.U// L R 0 R 0 R 0 R 0 R0 0 R 0 R 0 R 0 TO INERTER POWER 0U// 0R_ F 0.U// *000P/0/ R *0 R *0 R *0 R *0 USP+ USP- R0 R *0 R *0 R *0 R *0 R0 *0 R *0 R *0 R *0 R *0 R *0 R *0 R *0 R *0 R *0 R *0 R *0 R *0 R *0 R R 0.U// J 0R_ 0R_ US F US F# 0U// IN N_LS_T N_LS_LK N_TXLOUT0- N_TXLOUT0+ N_TXLOUT- N_TXLOUT+ N_TXLOUT- N_TXLOUT+ N_TXUOUT0- N_TXUOUT0+ N_TXUOUT- N_TXUOUT+ N_TXUOUT- N_TXUOUT+ N_TXLLKOUT- N_TXLLKOUT+ N_TXULKOUT- N_TXULKOUT+ N_TXLOUT- N_TXLOUT+ N_TXUOUT- N_TXUOUT+ 0.U// /0 change the footprint to SOT_-_- _POWER_ON# USP+ USP- 0 MI_LK 0 MI_T *0ohm,00m USP+ L USP- R0 R R US F US F# _PWR *0R_ *0R_ 0R_ N Quanta omputer Inc. PROJET : QU Size ocument Number Rev L PNEL/WEM ate: Saturday, February, 00 Sheet of

20 PIE_TXP[..0] PIE_TXP[..0] PIE_RXP[..0] PIE_TXN[..0] PIE_TXN[..0] PIE_RXN[..0] PIE_RXP[..0] PIE_RXN[..0] 0 U PIE_TXP PIE_TXN K J PIE_RX0P PIE_RX0N PRT OF PIE_TX0P PIE_TX0N G G0 _PEG_RXP _PEG_RXN 0.U// 0.U// PIE_RXP PIE_RXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP0 PIE_TXN0 PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN J J H H G G F E E E PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN P I - E X P R E S S I N T E R F E PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN F F0 F F W W0 _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP0 _PEG_RXN0 _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN U// 0.U// 0.U// 0.U// 0.U// 0.U// 0.U// 0.U// 0.U// 0.U// 0.U// 0.U// 0.U// 0.U// 0.U// 0.U// 0.U// 0.U// PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP0 PIE_RXN0 PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_TXP PIE_TXN Y Y PIE_RX0P PIE_RX0N PIE_TX0P PIE_TX0N W W _PEG_RXP _PEG_RXN U// 0.U// PIE_RXP PIE_RXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN W W U PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN 0 _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN 0 0.U// 0.U// 0.U// 0.U// PIE_RXP PIE_RXN PIE_RXP PIE_RXN Quantat Lenovo M-M+ J000T J000T M-M J0000T J0000T PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP0 PIE_TXN0 U U T T R R PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN U U0 U U R R0 _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP0 _PEG_RXN0 0.U// 0.U// 0.U// 0.U// 0.U// 0.U// PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP0 PIE_RXN0 EMI P. PIE_REFLKP PIE_REFLKN, PIE_RST# PIE_REFLKP PIE_REFLKN PIE_RST# lock J PIE_REFLKP J0 PIE_REFLKN SM us K N_SM_T K N_SMLK M PERST M-M+ alibration PIE_LRN PIE_LRP N_RM_0 N_RM_ N TT N_FN_TH G J F G K K R K_ R.K_ +. PIE_ Size ocument Number Rev M-M PI-E *0.U// *0.U// Quanta omputer Inc. PROJET : QU ate: Saturday, February, 00 Sheet 0 of

21 +.(00m) 0 ohm/00m. +.(00m). +.(0m).. +_.. _ORE. +.(m) +.(m) ohm/ ohm/ L 0 ohm/00m +.(m) +.(m) L L L L _ORE(m) L +.(00m) L L L ohm,00m 0ohm,00m U/0/ 0ohm,00m 0U/./ 0ohm,00m 0U/./ ohm,00m 0ohm,00m 0U/./ *U/./ 0ohm,00m 00 0U/./ 0ohm,00m 0U/./ ohm,00m 0U/./ 0U/./ LR_M L_M 0 U/0/ U/0/ LP_M 0.U// 0.U// U/0/ U/0/ U/0/ U/0/ 0 U/0/ _M U/0/ 0.U// 0 0.U// 0.U// _M 0U/./ PLL_P 0 0.U// PIE_P_M 0.U// MP 0.U// PLL_ 0.U// J H K L M N N N N M P P M R R M J J L K PIE_P_M R EXT_LS_LON GPU_TXLK_UP GPU_TXLK_UN GPU_TXOUT_U0P GPU_TXOUT_U0N GPU_TXOUT_UP GPU_TXOUT_UN GPU_TXOUT_UP GPU_TXOUT_UN GPU_TXOUT_UP GPU_TXOUT_UN GPU_TXLK_LP GPU_TXLK_LN GPU_TXOUT_L0P GPU_TXOUT_L0N GPU_TXOUT_LP GPU_TXOUT_LN GPU_TXOUT_LP GPU_TXOUT_LN GPU_TXOUT_LP GPU_TXOUT_LN 0R_ R0 R0 R0 R0 R R0 R R R R R R R0 R0 R R R R R R NOTE:Single channel LS interfaces must use the lower LS channel(txout_lxx) 0U/./ UF PRT OF LR_ LR_ L_ L_ LSSR_ LSSR_ LSSR_ LSSR_ LSSR_ LSSR_ LSSR_ LSSR_ LSSR_ LSSR_0 LSSR_ LSSR_ LSSR_ LSSR_ LP LPSS M-M+ ontrolry_l LS channel IGON TXLK_UP TXLK_UN TXOUT_U0P TXOUT_U0N TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXLK_LP TXLK_LN TXOUT_L0P TXOUT_L0N TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN G J K L N N P R G H K L R P N N P R P R P R R *0K_ R R EXT_LS_LON EXT_ISP_ON +_. 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0R_ 0K_ *0R_ R R_ R R_ GPU_TXULKOUT+ GPU_TXULKOUT- GPU_TXUOUT0+ GPU_TXUOUT0- GPU_TXUOUT+ GPU_TXUOUT- GPU_TXUOUT+ GPU_TXUOUT- GPU_TXUOUT+ GPU_TXUOUT- GPU_TXLLKOUT+ GPU_TXLLKOUT- GPU_TXLOUT0+ GPU_TXLOUT0- GPU_TXLOUT+ GPU_TXLOUT- +_ GPU_TXLOUT+ +_ GPU_TXLOUT- GPU_TXLOUT+ GPU_TXLOUT- R 0K_ THERM_ST THERM_SLK RM_STRP0 RM_STRP RM_STRP RM_STRP GPIO0 GPIO GPIO GPIO GPIO GPIO GPIO SOUT_GPIO SIN_GPIO SLK GPIO GPIO GPIO ORE.I0 LT#_GPIO R ORE.I SS#_GPIO 0 0.U// R *0K_ 0K_ R0 R R REFG T IP H0 PSYN LI K_.K_.K_ GFX_TF0 T T T T0 for IT PLL_P PIE_P_M M L J H M0 L0 J0 H0 M L J L K M J K M N P G H H H J J J K K L L L M M N P R N R P N R P P R N P R G F F E E E F F G G F F G P R P R R0 P0 M U IP_0 IP_ IP_ IP_ IP_ IP_ IP_ IP_ H_0 H_ PHTL PLK0 IPLK PSYN LI S SL IP / I PNTL MP_0 PNTL MP_ PNTL_0 PNTL_ PNTL_ PLK PT_0 PT_ MULTI_GFX PT_ EXTERNL PT_ TMS PT_ PT_ PT_ PT_ PT_ PT_ PT_0 PT_ PT_ PT_ PT_ PT_ PT_ PT_ PT_ PT_ PT_0 PT_ PT_ PT_ GPIO_0 GPIO_ GENERL GPIO_ PURPOSE GPIO_ I/O GPIO_ GPIO_ GPIO_ GPIO LON GPIO ROMSO GPIO ROMSI GPIO_0_ROMSK GPIO_ GPIO_ GPIO_ GPIO HP GPIO PWRNTL_0 GPIO SSIN GPIO THERML_INT GPIO HP GPIO TF GPIO_0_PWRNTL_ GPIO EN GPIO ROMS GPIO LKREQ GPIO JMOE GPIO TI GPIO TK GPIO TMS GPIO TO GEN_ GEN_ GEN_ GEN HP GEN_E GEN_F GEN_G REFG PLL_P PLL_PSS PIE_P PRT OF TXM_P0P TXP_P0N INTEGRTE TMS/P P_P P_PSS TX0M_PP TX0P_PN TXM_PP TXP_PN TXM_PP TXP_PN TXM_P0P TXP_P0N TXM_PP TXP_PN TXM_PP TXP_PN TXM_PP TXP_PN P_P P_PSS P_R_ P_R_ P_R_ P_R_ P_SSR_ P_SSR_ P_SSR_ P_SSR_ P_SSR_ P_SSR_ P_SSR_ P_SSR_ P_SSR_ P_SSR_0 P_LR N_TP N_TPSS HP R R G G HSYN SYN RSET SSQ I SSI R R G G Y OMP SYN HSYN Q SSQ I SSI RSET N N0 R0 P0 R P R P R P R P R P R P M L H G N N0 P R N P R N N N N N N N G H G G R P R0 P0 R P N N0 N R P R P M L M L M L K K K L M M L K H G J R R0 R R0 R0 SYN HSYN I TP P_R P_R EXT_G_RE EXT_G_GRN EXT_G_LU _M I _M Q 0R_ 0R_ R_ R_ 0R_ U/0/ U/0/ U/0/ R R R SYN HSYN EXT_HSYN EXT_SYN 0 U/0/ U/0/ 0.U// 0.U// 0.U// 0R_ 0R_ 0R_ 0 0.U// 0.U// 0 ohm/00m L L L L L 0U/./ 0U/./ 0U/./ +.(0m) 0ohm,00m.. +.(00m) 0ohm,00m +.(00m). INSTLL P/_R TO +.(00m) FOR Mx 0 0U/./ 0U/./ 0ohm,00m +.(0m) 0ohm,00m +.(m) 0ohm,00m...P/0/ Y MHZ R M_ MP MME-XT_XTLI MME-XT_XTLO PLL_ R P G MP MPSS XTLIN XTLOUT PLL_ PLL LOKS P UX T LK T LK T_P_UXN LK_P_UXP M L J H J J.K_.K_.K_.K_ GPU_LS_T GPU_LS_LK R R R R0 +_ +_ +_ +_. TO LEEL SHIFT LOGI REQUIRE, USE ON Mx (Only for MX,so,remove MX Level shift).p/0/ - + THERM_LERT# G K M TS_FO MINUS PLUS THERML T_P_UXN LK_P_UXP H G.K_.K_ R R +_ +_, RE TOLERNT ON Mx M-M+,, THERM_LERT# THERM_LERT# Quanta omputer Inc. PROJET : QU Size ocument Number Rev M-M LS\RG\TMS Saturday, February, 00 ate: Sheet of

22 M_Q[..0] M_Q[..0] M_M[..0] M_RQS[..0] M_WQS[..0] M_M[..0] M_0 M_ M_ M_M[..0] M_RQS[..0] M_WQS[..0] M_M[..0] M_0 M_ M_. R 00R_ MREF R 00R_ 0.U//. M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q U Part of P Q_0 P Q_ P Q_ P Q_ M Q_ K Q_ K Q_ K Q_ M Q_ M Q_ L Q_0 L Q_ J Q_ J Q_ H Q_ H Q_ K Q_ J Q_ J0 Q_ J Q_ F Q_0 F Q_ 0 Q_ Q_ G Q_ G Q_ G Q_ F Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ 0 Q_ 0 Q_ J Q_0 H Q_ F Q_ Q_ J Q_ G Q_ F Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ H Q_ F Q_ E Q_ Q_ J Q_0 G Q_ E Q_ Q_ N MREF N MREFS M N_ M-M+ MEMORY INTERFE write strobe read strobe M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_0 M_ QMb_0 QMb_ QMb_ QMb_ QMb_ QMb_ QMb_ QMb_ QS_0 QS_ QS_ QS_ QS_ QS_ QS_ QS_ QS_0 QS_ QS_ QS_ QS_ QS_ QS_ QS_ OT0 OT LK0 LK LK0b LKb RS0b RSb S0b Sb S0b_0 S0b_ Sb_0 Sb_ KE0 KE WE0b WEb G F E J E 0 E G M K G0 E H G M0 K G E F M K G E E E H 0 0 G H F M_M0 M_M M_M M_M M_M M_M M_M M_M M_M M_M M_M0 M_M M_M M_ M_0 M_ M_M0 M_M M_M M_M M_M M_M M_M M_M M_RQS0 M_RQS M_RQS M_RQS M_RQS M_RQS M_RQS M_RQS M_WQS0 M_WQS M_WQS M_WQS M_WQS M_WQS M_WQS M_WQS M_OT0 M_OT M_LK0 M_LK M_LK0# M_LK# RS0# RS# S0# S# S0_0# S0_# S_0# S_# KE0 KE WE0# WE# T M_OT0 M_OT M_LK0 M_LK M_LK0# M_LK# RS0# RS# S0# S# S0_0# T S_0# T KE0 KE WE0# WE# QS[..0] QS#[..0]. R 00R_ R 00R_. MREF 0.U// R R R R R0 UG H Q_0 G Q_ E Q_ Q_ H Q_ G Q_ F Q_ 0 Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ J0 Q_ H0 Q_ F0 Q_ Q_ G Q_0 G Q_ F Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ M Q_ M Q_ N Q_ N Q_ R Q_ R Q_ T Q_ T Q_ M Q_0 M Q_ P Q_ P Q_ R Q_ R Q_ R Q_ U Q_ U Q_ U Q_ U Q_0 Q_ Y Q_ Y Q_ Q_ Q_ U Q_ U Q_ U Q_ Q_ W Q_0 W Q_ W Q_ W Q_ MREF MREFS K_ M0.K_ TESTEN.K_ TEST_MLK 0R_ TEST_YLK *0K_ MEMTEST H PLLTEST M-M+ Part of M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_0 M_ MEMORY INTERFE write strobe read strobe QMb_0 QMb_ QMb_ QMb_ QMb_ QMb_ QMb_ QMb_ QS_0 QS_ QS_ QS_ QS_ QS_ QS_ QS_ QS_0 QS_ QS_ QS_ QS_ QS_ QS_ QS_ OT0 OT LK0 LK LK0b LKb RS0b RSb S0b Sb S0b_0 S0b_ Sb_0 Sb_ KE0 KE WE0b WEb RM_RST H H J J J J G J F F J J J F G G 0 E P R W J 0 F P P W H 0 E P P W K K K K K E E L M E K F M MEM_RST# R.K_. R 00R_ R 00R_ MREFS 0.U// IIER RESISTORS R R MREF TO. 00R 0.R MREF TO GN 00R 00R MREF oltage *Q 0.*Q R 00R_ R 00R_ MREFS 0.U// Size ocument Number Rev M-M MEMORY I/F Quanta omputer Inc. PROJET : QU ate: Saturday, February, 00 Sheet of