Z05 SYSTEM BLOCK DIAGRAM

Size: px
Start display at page:

Download "Z05 SYSTEM BLOCK DIAGRAM"

Transcription

1 Z0 SYSTEM LOK IGRM PU ORE / VN (ISL) PGE N_ORE.V (RT0) PGE.V_N (RT0) PGE RII-SOIMM PGE RII-SOIMM PGE RII /00 MHz RII /00 MHz M Griffin SG Processor Lion Sabie P (upg)/w PGE,,, PU THERML SENSOR PGE PU Fan PGE R II SMR_VTERM.VSUS(TPSREGR) PGE HT LINK SYSTEM POWER (ISL) PGE SYSTEM HRGER (ISL) PGE LVS PGE RT PGE LVS RT NORTH RIGE & SOUTH RIGE PI-E Mini PI-E ard PGE PIE X (Wireless LN) Express ard PIE X (NEW R) LN ROOM MM (0/00/GagaLN) PGE PGE PIE X RJ PGE MPM US.0 X X US US ST - H PGE O(ST) PGE ST0 ST mm X mm, pin G US 0,, US US US 0 X X X X US.0 Ports luetooth P-cam Fingerprint PGE, PGE PGE PGE ard Reader Realtek RTSE ( in ) PGE US X.MHz PGE,,,0,,, zalia LP zalia udioontroller RealTek L PGE 0 M. PGE 0 RJ PGE P STK UP LYER : TOP LYER : Keyboard PGE K (WPE) PGE udio mplifier PGE 0 Int MI PGE 0 LYER : IN LYER : IN LYER : V LYER : OT Touch Pad SPI ROM PGE PGE Speaker SPIF/Phone Jack Line in MI Jack PGE 0 PGE PGE PGE Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev lock iagram Friday, March 0, 00 ate: Sheet of PF created with FinePrint pdffactory Pro trial version

2 HT_RX#[..0] <> HT_RX#[..0] <> HT_TX[..0] HT_RX[..0] <> HT_RX[..0] <> HT_TX#[..0] HT_TX[..0] HT_TX#[..0] PROESSOR HYPERTRNSPORT INTERFE VLT_x N VLT_x RE ONNETE TO THE LT_RUN POWER SUPPLY THROUGH THE PKGE OR ON THE IE. IT IS ONLY ONNETE ON THE OR TO EOUPLING NER THE PU PKGE VLT_RUN U HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# E E E F G G G H J K L L L M N N E F F F G H H H K K L M M M N P VLT_0 VLT_ VLT_ VLT_ L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L HT LINK VLT_0 VLT_ VLT_ VLT_ L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L E E E E W W V U U U T R Y W V V V U T T.U_ HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX#.V_HT Note:on MP,(HT=.V) and PU(HT=.V) and therefore cannot be connected to the same HT power rail. L FJHS00_0 L FJHS00_0 0 ohm() VLT_RUN 0.U_.U_.U_.U_ 0P_ LYOUT: Place bypass cap on topside of board NER HT POWER PINS THT RE NOT ONNETE IRETLY TO OWNSTREM HT EVIE, UT ONNETE INTERNLLY TO OTHER HT POWER PINS PLE LOSE TO VLT0 POWER PINS 0P_ <> HT_PU_UPLK0 <> HT_PU_UPLK#0 <> HT_PU_UPLK <> HT_PU_UPLK# J J J K L0_LKIN_H0 L0_LKIN_L0 L0_LKIN_H L0_LKIN_L L0_LKOUT_H0 L0_LKOUT_L0 L0_LKOUT_H L0_LKOUT_L Y W Y Y HT_PU_WNLK0 <> HT_PU_WNLK#0 <> HT_PU_WNLK <> HT_PU_WNLK# <> <> HT_PU_UPTL0 <> HT_PU_UPTL#0 <> HT_PU_UPTL <> HT_PU_UPTL# N P P P L0_TLIN_H0 L0_TLIN_L0 L0_TLIN_H L0_TLIN_L L0_TLOUT_H0 L0_TLOUT_L0 L0_TLOUT_H L0_TLOUT_L R R T R HT_PU_WNTL0 <> HT_PU_WNTL#0 <> HT_PU_WNTL <> HT_PU_WNTL# <> NO STU for HT R */F_ VLT_RUN R */F_ thlon Sg SOKET PIN thlon Sg Processor Socket SOKET PIN Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev M Griffin HT I/F ate: Monday, February, 00 Sheet of PF created with FinePrint pdffactory Pro trial version

3 E V_VTT_SUS_PU IS ONNETE TO THE V_VTT_SUS POWER SUPPLY THROUGH THE PKGE OR ON THE IE. IT IS ONLY ONNETE ON THE OR TO EOUPLING NER THE PU PKGE Processor R Memory Interface SMR_VTERM SMR_VTERM MEM:T <> M Q[0..] M Q[0..] <> M Q0 M Q0 PLE THEM LOSE TO U M Q M_T0 M_T0 G M Q.VSUS M Q M_T M_T F M Q PU WITHIN " M Q M_T M_T H 0 M Q VTT VTT W0 0 MEM:M/TRL/LK M Q M_T M_T G 0 G H M Q VTT VTT M Q M_T M_T 0 M Q VTT VTT 0 E R0 M Q M_T M_T H 0 M Q VTT VTT 0 M Q M_T M_T R./F_ M Q M_ZP VTT 0 K/F_ M Q M_T M_T E F0 M Q M_ZN MEMZP PU_VTT_SUS_F M Q M_T M_T H.VSUS E0 M Q MEMZN VTT_SENSE Y0 T M Q0 M_T M_T E R./F_ M Q0 MEM_M_RESET# PU_M_VREF M Q M_T0 M_T0 E M Q T H RSV_M MEMVREF W 0 M Q M_T M_T H M Q MEM_M_RESET# M Q M_T M_T E M Q <> M OT0 T M0_OT0 RSV_M T M Q M_T M_T F M Q <> M OT V 00 R0 M OT0 M0_OT M Q M_T M_T M Q T U M OT M_OT0 M0_OT0 W M OT0 <> 000P_ M Q M_T M_T G M Q T V M_OT M0_OT W.U_ K/F_ M OT0 M OT <> 0 M Q M_T M_T G M Q M_OT0 Y T M Q M_T M_T M Q <> M S#0 T0 M0_S_L0 M Q M_T M_T M Q <> M S# U M S#0 <> M S#0 M0_S_L M0_S_L0 V M Q0 M_T M_T E0 M Q0 T0 U0 M S# <> M S# M_S_L0 M0_S_L W 0 M S#0 M Q M_T0 M_T0 E M Q T V0 M_S_L M_S_L0 U T 0 M Q M_T M_T F M Q M Q M_T M_T M Q <> M KE0 J M_KE0 M_KE0 J M KE0 <> M Q M_T M_T M Q <> M KE J0 M_KE M_KE H M KE <> E M Q M_T M_T F0 E M Q M Q M_T M_T F M Q T0 N M_LK_H M_LK_H P T G M Q M_T M_T H M Q T N0 M_LK_L M_LK_L R T G M Q M_T M_T J M Q <> M LKOUT E M_LK_H M_LK_H M LKOUT <> M Q M_T M_T E M Q <> M LKOUT# F M_LK_L M_LK_L M LKOUT# <> M Q0 M_T M_T E M Q0 <> M LKOUT Y M_LK_H M_LK_H F M LKOUT <> G M Q M_T0 M_T0 H0 M Q <> M LKOUT# M_LK_L M_LK_L F M LKOUT# <> G P M Q M_T M_T H M Q T0 M_LK_H M_LK_H R T P0 M Q M_T M_T Y M Q T M_LK_L M_LK_L R T M [0..] <> M Q M_T M_T M Q <> M [0..] M 0 N M 0 M Q M_T M_T M Q M M_0 M_0 P E M0 M M Q M_T M_T M Q M M_ M_ N N M M Q M_T M_T W M Q M M_ M_ P M M M Q M_T M_T W M Q M M_ M_ N M M M Q M_T M_T Y M Q M M_ M_ N E L0 M M Q0 M_T M_T M Q0 M M_ M_ L M M M Q M_T0 M_T0 Y0 M Q M M_ M_ N L M M Q M_T M_T 0 M Q M M_ M_ L E0 L M M Q M_T M_T M Q M M_ M_ M F0 K M M Q M_T M_T M Q M 0 M_ M_ K F R M 0 M Q M_T M_T M Q M M_0 M_0 T F L M M Q M_T M_T M Q M M_ M_ L 0 K0 M M Q M_T M_T M Q M M_ M_ L 0 V M M Q M_T M_T Y M Q M M_ M_ W K M M Q M_T M_T M Q M M_ M_ J E K M M Q0 M_T M_T W M Q0 M_ M_ J M Q M_T0 M_T0 W M Q M S#0 <> M Q M_T M_T Y M Q <> M S#0 R0 M_NK0 M_NK0 R F M S# <> M Q M_T M_T Y M Q <> M S# R M_NK M_NK U M Q M_T M_T M Q <> M S# J M_NK M_NK J M S# <> F M Q M_T M_T F M Q M Q M_T M_T M Q <> M RS# R M_RS_L M_RS_L U M RS# <> F M Q M_T M_T M Q <> M S# T M_S_L M_S_L U M S# <> M Q M_T M_T M Q <> M WE# T M_WE_L M_WE_L U M WE# <> M Q M_T M_T Y Y M Q M Q0 M_T M_T W E M Q0 M Q M_T0 M_T0 F M Q M Q M_T M_T F M Q thlon Sg SOKET PIN M Q M_T M_T M Q M_T M_T thlon Sg Processor Socket SOKET PIN M QS0 M QS0 M QS#0 M_QS_H0 M_QS_H0 G M QS#0 <> M LKOUT <> M LKOUT M QS M_QS_L0 M_QS_L0 H M QS M QS# M_QS_H M_QS_H G M QS# M QS M_QS_L M_QS_L G M QS.pF_ M QS# M_QS_H M_QS_H.pF_ M QS# M QS M_QS_L M_QS_L M QS <> M LKOUT# <> M LKOUT# F PLE LOSE TO PROESSOR PLE LOSE TO PROESSOR M QS# M_QS_H M_QS_H G E M QS# M QS M_QS_L M_QS_L G M QS <> M LKOUT WITHIN. INH <> M LKOUT WITHIN. INH M QS# M_QS_H M_QS_H M QS# M QS M_QS_L M_QS_L F M QS M QS# M_QS_H M_QS_H F M QS#.pF_ M QS M_QS_L M_QS_L 0.pF_ E M QS M QS# M_QS_H M_QS_H Y M QS# <> M LKOUT# <> M LKOUT# M QS M_QS_L M_QS_L W F M QS M QS# M_QS_H M_QS_H W E M QS# M_QS_L M_QS_L W To reverse SOIMM socket <> M M[0..] M M0 M M M M M M M M M M M M M M E E U M_M0 M_M M_M M_M M_M M_M M_M M_M M_M0 M_M M_M M_M M_M M_M M_M M_M E E F Y Y M M0 M M M M M M M M M M M M M M To normal SOIMM socket M M[0..] <>.U_.U_ SMR_VTERM.U_.U_.U_.U_.U_.U_ 000P_ 000P_ 0 000P_ 000P_ 0P_ 0P_ 0P_ 0 0P_ <> M QS[0..] M QS0 M QS M QS M QS M QS M QS M QS M QS thlon Sg SOKET PIN thlon Sg Processor Socket SOKET PIN M QS0 M QS M QS M QS M QS M QS M QS M QS M QS[0..] <> <> M QS#[0..] M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS#[0..] <> Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev M Griffin RII MEMORY I/F Monday, February, 00 ate: Sheet of E PF created with FinePrint pdffactory Pro trial version

4 THLON ontrol and ebug.v LYOUT: ROUTE V TRE PPROX. 0 mils WIE (USE x mil TRES TO EXIT LL FIEL) N 00 mils LONG. If M SI is not used, the SI pin can be left unconnected and SI should have a 0- ( %) pulldown to VSS. R0 0_ PU_V_RUN.V L LMPG0SN_ 00U-.V_ 0.U_ PU_V_RUN 0.U_ 0 00P_ <> <> PU_LKP PU_LKN.VSUS PU_LKP PU_LKN R 0_ R 0_ R R place them to PU within." VLT_RUN *0_ *K/F_ 00P_ R /F_ 00P_ PU_SI PU_SI PU_LERT PU_V_RUN Keep trace from resisor to PU within 0." keep trace from caps to PU within." PU_LKIN_S_P PU_LKIN_S_N R R./F_./F_ PU_HT_RESET# PU_HT_PWRG PU_HT_LTSTOP# PU_LT_REQ#_PU PU_SI PU_SI PU_LERT PU_HTREF0 PU_HTREF PU_SI <> PU_SI <> F F F0 F F E R P U V V LKIN_H LKIN_L RESET_L PWROK LTSTOP_L LTREQ_L SI SI LERT_L HT_REF0 HT_REF KEY KEY SV SV THERMTRIP_L PROHOT_L MEMHOT_L THERM THERM M W F W W PU_SV_R PU_SV_R PU_THERMTRIP# PU_PROHOT# PU_MEMHOT# PU_THERM PU_THERM.VSUS R0 00_ PU_THERMTRIP# PU_PROHOT#.VSUS.VSUS Q MMT0 R 0_ R 00_.V R.V R0 0_ R R *.K_ Q MMT0 *0_ *.K_ PWROK_E <,> THERM_SYS_PWR <,0> MP_THERMIP# <> E_PROHOT# <> MP_PROHOT# <>.VSUS R 00_ <> <> <> <> PU_V0_F_H PU_V0_F_L PU_V_F_H PU_V_F_L.VSUS PU_RY PU_TMS PU_TK PU_TRST# PU_TI F E Y G0 F V0_F_H V0_F_L V_F_H V_F_L RY TMS TK TRST_L TI VIO_F_H VIO_F_L VN_F_H VN_F_L REQ_L TO W Y H G E0 PU_REQ# E PU_TO VIO_F_H <> T PU_VN_RUN_F_H <> PU_VN_RUN_F_L <> PU_MEMHOT# R *00_ R *0_ Q *MMT0 PUMEMHOT# <> <> <> HTPU_PWRG HTPU_STOP# R 0_ R 0_.VSUS R 00_.VSUS PU_HT_PWRG PU_HT_LTSTOP# R 00_.U_ lose PU Sockt /0/0' Implement on -test T T R0 *0/F_ R0 *0/F_ T T T T T T T T T R 0_ PU_TEST_TSTUP PU_TEST_PLLTEST PU_TEST_PLLTEST0 PU_TEST_H_YPSSLK_H PU_TEST_L_YPSSLK_L PU_TEST_SNEN PU_TEST0_SNLK PU_TEST_SNLK PU_TEST_SNSHIFTEN PU_TEST_SNSHIFTEN PU_TEST_SINGLEHIN PU_TEST_NLOGIN H0 G E E F E E F TEST TEST TEST TEST_H TEST_L TEST TEST0 TEST TEST TEST TEST TEST TEST RSV RSV RSV RSV RSV TEST_H TEST_L TEST TEST TEST TEST TEST TEST0 TEST TEST_H TEST_L RSV0 RSV RSV RSV RSV J PU_TEST_H_PLLHRZ_P H PU_TEST_L_PLLHRZ_N PU_TEST_P E PU_TEST_P F PU_TEST_P PU_TEST_P0 K PU_TEST_H_FLKOUT_P PU_TEST_L_FLKOUT_N H H T T T T T T T T0 route as differential as short as possible testpoint under package PU_SV_R PU_SV_R R 0_ R0 0_ VI Override ircuit R K_.VSUS R K_ Serial VI lock PU SV <> Serial VI ata PU SV <> <> HTPU_RST#.VSUS R0 0_ PU_HT_RESET# thlon Sg SOKET PIN thlon Sg Processor Socket SOKET PIN HTPU_PWRG R 0_ R *0_ R *0_ PU_PWRG_SVI <> R 00_ VFIX MOE PU_LT_REQ#_PU R 0_ HTPU_REQ# HTPU_REQ# <>.VSUS SV SV Voltage Output(PU Power) 0 0.V 0.V 0.0V 0.V /0/0' Mount 00 ohm on -test PU H/W MONITOR /0/0' Reserve 0 ohm for PU thermal issue on -test V R0 R *0_ PU_THERM /F_ 00P_ PU_THERM 0 mil trace / 0 mil space MIL V_THM.U_ ddress H U V XN XP -OVT G -LT SMT SMLK R 0K_ KSMT KSMLK Q V V R 0K_ N00E To S GPIO To FN PUFN#_ON <> V R.K_ THERM_LERT# <> R.K_ Q N00E V Q N00E MT_PU <> MLK_PU <> PU_TEST_SINGLEHIN PU_TEST_SNSHIFTEN PU_TEST_P0 PU_TEST_P PU_TEST_PLLTEST PU_TEST_PLLTEST0 PU_TEST0_SNLK PU_TEST_SNEN PU_TEST_SNSHIFTEN PU_TEST_SNLK R R R R R R R R00 *00_ *00_ *00_ *00_ *00_ *00_ *00_ R 00_ *00_ R0 00_.VSUS /0/0' Mount 00 ohm on -test R *0_ PU_HT_RESET# R *0_ R0 *0_ R *0_ R 00_.VSUS V R 0K_ Q MMT0 HT ONNETOR PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO R K/F_ H_HTPU_RST# T T T T T0 T T T.VSUS N *SP-00-0-P-LV HT RSV RSV0 REQ_L RY 0 TK TMS TI TRST_L TO 0 V_PRO_IO_ V_PRO_IO_RESET_L KEY Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev M Griffin TRL & EUG Monday, February, 00 ate: Sheet of 0 0 PF created with FinePrint pdffactory Pro trial version

5 E PROESSOR POWER N GROUN UF J VSS VSS J VSS VSS J0 PU_ORE0 PU_ORE VSS VSS J PU_ORE0 VSS VSS J UE VSS VSS0 J VSS VSS J VSS VSS G P K V0_ V_ VSS VSS H P0 K V0_ V_ VSS VSS J R K 0 V0_ V_ VSS0 VSS J R K U-.V_ U-.V_.U_.0U_ 0P_ V0_ V_ VSS VSS J R K V0_ V_ VSS VSS J R K V0_ V_ VSS VSS K T K V0_ V_ VSS VSS K0 T L V0_ V_ VSS VSS0 K T L PU_ORE //0' el, 0, and V0_ V_ VSS VSS K T0 L0 V0_0 V_0 VSS VSS L T L V0_ V_ VSS VSS L T L V0_ V_ VSS VSS L U L V0_ V_ VSS0 VSS L U E L V0_ V_ VSS VSS L U E M 0 V0_ V_ VSS VSS L U E M U-.V_ U-.V_.U_.0U_ 0P_ V0_ V_ VSS VSS M U E V0_ V_ VSS VSS M V E M V0_ V_ VSS VSS0 M V E N V0_ V_ VSS VSS M0 V0 E N V0_0 V_0 VSS VSS N V N0 V0_ V_ VSS VSS N V N PU_VN_RUN V0_ V_ VSS VSS N W N V0_ V_ VSS0 VSS Y P V_ VSS VSS PU_VN_RUN K P VN_ V_ VSS VSS M P VN_ V_ VSS VSS P P VN_ VSS VSS T Y VN_ VIO.VSUS P VSS VSS00 V V R VN_ VIO VSS VSS0 V R0 U-.V_ U-.V_ U-.V_ VIO VSS VSS0.VSUS H V R VIO VIO VSS VSS0 J V R VIO VIO VSS VSS0 K U T VIO VIO VSS0 VSS0 K T T VIO VIO VSS VSS0 K T T VIO VIO0 VSS VSS0 K T T VIO VIO VSS VSS0 L T T VIO VIO VSS VSS0 M R T VIO VIO VSS VSS0 M P U VIO VIO VSS VSS M P U VIO0 VIO VSS VSS M P U EOUPLING ETWEEN PROESSOR N IMMs VIO VIO VSS VSS N P U0 VIO VIO VSS VSS U VSS0 VSS E U PLE LOSE TO PROESSOR S POSSILE VSS VSS F U thlon Sg SOKET PIN VSS VSS F U VSS VSS.VSUS thlon Sg F V VSS VSS F V Processor Socket VSS VSS0 F V VSS VSS SOKET PIN F V VSS VSS F V VSS VSS F V VSS VSS F V.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.0U_.0U_ 0P_ VSS0 VSS H VSS VSS W H VSS VSS Y H VSS VSS Y H VSS VSS N J VSS M Sg Griffin upg thlon Sg SOKET PIN thlon Sg Processor Socket SOKET PIN Top View F Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev M Griffin PWR & Monday, February, 00 ate: Sheet of E PF created with FinePrint pdffactory Pro trial version

6 E E MEM_SMLK MEM_SMT M Q0 M Q MEM_SMT M M 0 M M M M M M Q MEM_SMLK M M 0 M M M M M M Q M Q0 M Q M MVREF_IM M Q M Q M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q M Q MVREF_IM MEM_SMLK M Q M Q M Q M Q M Q M Q M Q M Q M Q M M M0 M Q0 MVREF_IM M Q M M M M M M M M M M M QS0 M M M M M QS M QS M QS M QS M QS M QS M QS M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M 0 M Q M Q M M Q M M Q M M M Q M Q M M Q M M Q M Q M Q M Q M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M M M M M M0 M M M M M M M M M QS# M M QS M QS M QS M QS M QS M QS M QS0 M QS M Q M M M Q M Q0 M M M Q M Q M Q M M 0 M M Q M M Q M Q M Q M Q M M Q M Q0 MEM_SMT M Q M Q M Q M Q M Q M Q M OT M M M S#0 M M KE0 M S#0 M 0 M M WE# M KE0 M M KE M M S#0 M OT M M M M M M M M M 0 M M M M M M M S# M S# M WE# M RS# M M OT0 M S# M RS# M 0 M 0 M S#0 M S# M S# M S# M M M M OT0 M M KE M M M S# M M S# MSM_T <> MSM_LK <>.VSUS V V SMR_VTERM.VSUS SMR_VTERM V V.VSUS.VSUS.VSUS.VSUS.VSUS SMR_VREF V SMR_VTERM V V M [0..] <> M KE0 <> M KE <> M RS# <> M S# <> M WE# <> M S#0 <> M S# <> M OT0 <> M Q[0..] <> M LKOUT <> M LKOUT# <> M LKOUT <> M LKOUT# <> M OT <> M S# <> M S# <> M S#0 <> M QS#[0..] <> M QS[0..] <> M M[0..] <> M LKOUT <> M LKOUT# <> M LKOUT <> M LKOUT# <> M OT0 <> M KE0 <> M KE <> M OT <> M [0..] <> M S# <> M S#0 <> M S# <> M QS#[0..] <> M QS[0..] <> M M[0..] <> M RS# <> M S# <> M WE# <> M Q[0..] <> M S#0 <> M S# <> Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R-II SOIMM* Monday, February, 00 Z0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R-II SOIMM* Monday, February, 00 Z0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R-II SOIMM* Monday, February, 00 Z0 REVERSE (H=.) REVERSE (H=.) R K/F_ R K/F_ T T RP X_ RP X_.U_.U_.U_.U_.U_.U_ 0 U-.V_ 0 U-.V_ R _ R _.U_ 0.U_ 0 RP X_ RP X_ RP X_ RP X_.U_ 0.U_ 0.U_.U_ RP X_ RP X_.U_.U_.U_ 0.U_ 0 *0U-.V_ 0 *0U-.V_ 0 R _ R _ RP X_ RP X_.U_.U_.U_.U_ R K/F_ R K/F_ RP X_ RP X_.U_.U_.U_.U_.U_.U_ R0 *0_ R0 *0_.U_.U_ RP X_ RP X_ RP X_ RP X_.U_.U_.U_.U_.U_.U_.U_.U_.U_ 0.U_ 0.U_.U_ R 0_ R 0_.U_.U_ *0U *0U *.U_ 0 *.U_ 0.U_.U_.U_.U_.U_.U_ RP X_ RP X_ U-.V_ U-.V_ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 SO-IMM J RII_SOIMM_R H. SO-IMM J RII_SOIMM_R H. RP X_ RP X_.U_.U_.U_.U_.U_.U_.U_.U_ R _ R _ *.U_ *.U_ Q0 *N00E Q0 *N00E.U_.U_.U_.U_ R 0_ R 0_ RP X_ RP X_.U_.U_.U_.U_ RP X_ RP X_ *.U_ *.U_.U_.U_ T T RP X_ RP X_ RP0 X_ RP0 X_.U_.U_ RP *.KX_ RP *.KX_ *.U_ 0 *.U_ 0.U_.U_ RP X_ RP X_ 0 *0U 0 *0U RP X_ RP X_ T T U_ U_ RP X_ RP X_ *.U_ *.U_.U_.U_ *.U_ 0 *.U_ 0.U_.U_ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 SO-IMM J RII_SOIMM_R H. SO-IMM J RII_SOIMM_R H. RP X_ RP X_ R _ R _.U_.U_ RP X_ RP X_.U_.U_.U_.U_ *0U-.V_ 0 *0U-.V_ 0.U_.U_.U_.U_ RP X_ RP X_.U_.U_.U_.U_ *0U-.V_ *0U-.V_.U_.U_.U_.U_.U_.U_.U_.U_ R 0_ R 0_.U_ 0.U_ 0.U_.U_ Q *N00E Q *N00E RP X_ RP X_.U_.U_ R 0K_ R 0K_ R _ R _.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_ T T.U_.U_ *.U_ *.U_.U_.U_.U_ 0.U_ 0.U_.U_ R0 _ R0 _ RP X_ RP X_.U_.U_ RP X_ RP X_ RP X_ RP X_ *.U_ *.U_ RP0 X_ RP0 X_ *0U-.V_ *0U-.V_ PF created with FinePrint pdffactory Pro trial version

7 <> HT_TX[..0] <> HT_TX#[..0] HT_RX[..0] <> HT_RX#[..0] <> U FG-NVII-MP JMP0T0 HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# F G H J J K K L G F L K L K J K E F G H J L K E E HT_MP_RX0_P HT_MP_RX0_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX0_P HT_MP_RX0_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N SE OF HT HT_MP_TX0_P HT_MP_TX0_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX0_P HT_MP_TX0_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N K J K L K L L K K L K L H J L0 M0 G H F G H J E F E F G 0 0 E F HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# MP_PROHOT# R 00_.VSUS <> HT_PU_WNLK0 <> HT_PU_WNLK#0 <> HT_PU_WNLK <> HT_PU_WNLK# J H L K HT_MP_RX_LK0_P HT_MP_RX_LK0_N HT_MP_RX_LK_P HT_MP_RX_LK_N HT_MP_TX_LK0_P HT_MP_TX_LK0_N HT_MP_TX_LK_P HT_MP_TX_LK_N K J G H HT_PU_UPLK0 <> HT_PU_UPLK#0 <> HT_PU_UPLK <> HT_PU_UPLK# <> 0m m m <> HT_PU_WNTL0 H <> HT_PU_WNTL#0 G <> HT_PU_WNTL <> HT_PU_WNTL# MP_THERMIP# <> MP_THERMIP# MP_PROHOT# <> MP_PROHOT# L TI00U00_.V_PLL_HT V.U_ R.U_ L TI00U00_.V_N.U_.V_HT_PLL 0U-.V_ L TI00U00_.V_N.U_.V_PLL_PU.U_.V_HT_PLL R 0/F_ HTMP_OMP_VM R0 0/F_ HTMP_OMP_ L HT_MP_RXTL0_P HT_MP_RXTL0_N HT_MP_RXTL_P HT_MP_RXTL_N THERMTRIP#/GPIO_ PROHOT#/GPIO_0.V_LL_HT.V_PLL_HT.V_PLL_PU HT_MP_OMP_V HT_MP_OMP_ HT_MP_TXTL0_P HT_MP_TXTL0_N HT_MP_TXTL_P HT_MP_TXTL_N HT_MP_REQ# HT_MP_STOP# HT_MP_RST# HT_MP_PWRG LKOUT_00MHZ_P LKOUT_00MHZ_N LKOUT_MHZ.V_HT_.V_HT_.V_HT_ K0 J0 0 L M K Y Y Y HTPU_REQ# LKOUT_MHz.V_HT_ 0 HT_PU_UPTL0 <> HT_PU_UPTL#0 <> HT_PU_UPTL <> HT_PU_UPTL# <> T0 HTPU_REQ# <> HTPU_STOP# <> HTPU_RST# <> HTPU_PWRG <> PU_LKP <> PU_LKN <> L TI00U00_.V_N 00m.V_N R 0_.U_ PU_SVREF G R.K/F_MP_TERM_J PU_SVREF LK00_TERM_.V_HT_.V_HT_.V_HT_.V_HT_ V V W W U_.V_HT_ U_.U_ U-.V_ L PY00T_.V_N 0m U_ U_.U_.U_ U-.V_ PF created with FinePrint pdffactory Pro trial version Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev MP HyperTransport us ate: Monday, March 0, 00 Sheet of

8 U FG-NVII-MP F G F F 0 0 F F F F H H H H H H K K K K K K J J0 K K0 PE0_RX0_P PE0_RX0_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX0_P PE0_RX0_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N SE OF PIE PE0_TX0_P PE0_TX0_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX0_P PE0_TX0_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N 0 0 E E0 F F0 G G0 H H0 H H [LN] [NEW R] [MINI R-] <,,> PIE_WKE# <> PIE-LN_RXP <> PIE-LN_RXN <> LN_LKREQ# <> PIE-NEW_RXP <> PIE-NEW_RXN <> NEW_LKREQ# <> PPE# <> PIE-MINI_RXP <> PIE-MINI_RXN <> MINI_LKREQ# 0m 0m.V_N.V_N.V_PLL_HT L 0 L H PE_WKE#/GPIO_ PE0_PRSNTX T0 U PE0_PRSNT_# PE0_PRSNTX T0 U0 PE0_PRSNT_# PE0_PRSNTX T0 U PE0_PRSNT_# PE0_PRSNTX T0 U PE0_PRSNT_# L PE_RX_P L0 PE_RX_N W PE_LKREQ# W PE_PRSNT# M PE_RX_P M PE_RX_N LN_LKREQ# U PE_LKREQ# U PE_PRSNT# N PE_RX_P N PE_RX_N NEW_LKREQ# U PE_LKREQ# S PPE#_R U PE_PRSNT# N0 PE_RX_P N PE_RX_N MINI_LKREQ# R PEE_LKREQ#/GPIO_ U PEE_PRSNT# P PE_RX_P P0 PE_RX_N T PEF_LKREQ#/GPIO_ V PEF_PRSNT# P PE_RX_P P PE_RX_N U PEG_LKREQ#/GPIO_ V0 PEG_PRSNT# MLG00NJ_.V_PLLPE_SS.U_.U_.V_PLLPE_SS U.V_PLL_PE_SS MLG00NJ_.V_PLLPE R0.V_PLL_PE.U_ R N/.V_PLL_PE.U_.V_PLL_HT P0 N/.V_PLL_PE_SS PE_LK_OMP V PE_LK_OMP.U_ R *.K/F_ <00mil Remove R for Nvidia suggest. PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PEE_REFLK_P PEE_REFLK_N PE_TX_P PE_TX_N PEF_REFLK_P PEF_REFLK_N PE_TX_P PE_TX_N PEG_REFLK_P PEG_REFLK_N.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_.V_PE_ PE_RST0# PE_RST# R R0 M M T T M M T T0 M M T T M0 M T T P P T T P P P R W W V V W Y Y Y Y W Y W Y W0 W PIE-LN_TXP_ PIE-LN_TXN_ LK_PIE-LN R LK_PIE-LN_#_R PIE-NEW_TXP_ PIE-NEW_TXN_ LK_PIE_NEW_R LK_PIE_NEW#_R PIE-MINI_TXP_ PIE-MINI_TXN_ LK_PIE_MINI_R LK_PIE_MINI#_R.V_PE.V_PE R *0_.U_ 0.U_ U_.U_.U_.U_ R _ R _.U_.U_ R _ R _.U_.U_ R _ R0 _ U_ 0.U_ L 0_ U-.V_ U_ PIE_RST# <>.U_ PIE-LN_TXP <> PIE-LN_TXN <> LK_PIE-LN <> LK_PIE-LN# <> PIE-NEW_TXP <> PIE-NEW_TXN <> LK_PIE_NEW <> LK_PIE_NEW# <> PIE-MINI_TXP <> PIE-MINI_TXN <> LK_PIE_MINI <> LK_PIE_MINI# <>.V_N U-.V_ dd 0R resistor, The resistor should only be stuffed for MP [LN] 00m00m U-.V_ [R Reader] [NEW R] [MINI R-] L0 U-.V_ m00m PY00T_.V_N PIE_RST# <,> LK_PIE-LN *0P_ For EMI LK_PIE-LN# *0P_ LK_PIE_MINI LK_PIE_MINI# *0P_ *0P_ LK_PIE_NEW *0P_ LK_PIE_NEW# *0P_ PF created with FinePrint pdffactory Pro trial version Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev MP PI-Express us Monday, March 0, 00 ate: Sheet of

9 REQ0# REQ# REQ# REQ# REQ# E0 G0 J0 M E U FG-NVII-MP PI_REQ0# PI_REQ#/FNRPM PI_REQ#/GPIO_0/RS_SR# PI_REQ#/GPIO_/RS_TS# PI_REQ#/GPIO_/RS_SIN# MP SE OF PI_GNT0# PI_GNT#/FNTL PI_GNT#/GPIO_/RS_TR# PI_GNT#/GPIO_/RS_RTS# PI_GNT#/GPIO_/RS_SOUT# F0 H0 K0 L0 F GNT0# T V PI/LP PULL-UP RP.KX_0PR INT# INT# INT# EVSEL# TRY# INT# PERR# 0 REQ# V INT# INT# INT# INT# L K J J H G F E G E J K L G J E H F L J K PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_INTW# PI_INTX# PI_INTY# PI_INTZ# PI PI_E0# PI_E# PI_E# PI_E# PI_EVSEL# PI_FRME# PI_IRY# PI_PR PI_PERR#/GPIO_/RS_# PI_SERR# PI_STOP# PI_PME#/GPIO_0 PI_RESET0# PI_RESET# PI_RESET# PI_LK0 PI_LK PI_LK PI_LK PI_LK PI_LKIN K K F K L J H J J K K EVSEL# FRME# IRY# PERR# SERR# STOP# PI_PME# PIRST_R# IERST_R# PIRST# R T T *_ PIRST# <> PI_LK R T PI_LK T PI_LK T PI_LK T PI_LK R _ PI_LKIN L:match to within 000 = Length of PI feedback and onboard devices = V RP.KX_0PR STOP# SERR# IRY# FRME# 0 PI_PME# R *.K_ LKRUN# R0.K_ LOK YPSS LP_LK_E REQ# REQ# REQ0# REQ# V *P_ V TRY# K PI_TRY# <> LKRUN# <> SERIRQ R0 T00 T0 0K_ LRQ# LRQ#0 SERIRQ P F0 L K K K J L L J K L J J L K G0 PI_LKRUN#/GPIO_ LP_RQ#/GPIO/FNRPM LP_RQ0#/GPIO_0 LP_SERIRQ IE_T_P0/WUS_T0 IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P IE_T_P IE_T_P0 IE_T_P IE_T_P IE_T_P IE_T_P IE_T_P IE LP LP_FRME# LP_PWRWN#/GPIO_/EXT_NMI# LP_RESET0# LP_RESET# LP_0 LP_ LP_ LP_ LP_LK0 LP_LK IE_R_P0/WUS_STOP IE_R_P/WUS_RX_EN IE_R_P/WUS_TX_EN IE_S_P#/WUS_PHY_RESET# IE_S_P# IE_K_P# L G E H J K J LFRME#_R LP_P# LP_RST# LP_RST# L0_R L_R L_R L_R LP_LK_E_R PI_LK_EUG R T T R _ R0 _ R0 _ R _ R _ R0 _ R0 _ R0 _ LFRME# <,,> PLTRST# <,> L0 <,> L <,> L <,> L <,> LP_LK_E <> PI_LK_EUG <> PI_LK_EUG R PI_LKIN *P_ *P_ V R R R.K_ 0K_.K_ PREQ K IE_INTR H0 PIORY K0 L0 LE_ET_P F IE_REQ_P/WUS_PLK IE_INTR_P/WUS_PHY_TIVE IE_RY_P/WUS_T_EN IE_IOR_P#/WUS_SERIL_T LE_ET_P/GPIO_ IE_IOW_P#/WUS STTUS IE_OMP_PV IE_OMP_ J0 M K IE_OMP_V R0 IE_OMP_V_ /F_ V R0 K_ R /F_ PF created with FinePrint pdffactory Pro trial version Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev MP PI/LP/IE Monday, February, 00 ate: Sheet of

10 U FG-NVII-MP R R0 0K_ 0K_ 0 0 E F G J0 J RGMII_RX0/MII_RX0 RGMII_RX/MII_RX RGMII_RX/MII_RX RGMII_RX/MII_RX RGMII_RX/MII_RXLK RGMII_RXTL/MII_RXV MII_RXER/GPIO_ MII_OL/MSM_T MII_RS/MSM_LK SE OF LN.V_UL_RMGT.V_UL_RMGT RGMII_TX0/MII_TX0 RGMII_TX/MII_TX RGMII_TX/MII_TX RGMII_TX/MII_TX RGMII_TXLK/MII_TXLK RGMII_TXTL/MII_TXEN L N J K L L H K V_UL.V_UL R0 V_UL.V_UL 0K_ R 0K_ LN_INT RGMII/MII_INTR/GPIO RGMII/MII_M RGMII/MII_MIO K0 L0 MIO R 0K_.V_UL.V_UL N.V_PLL_M_UL RGMII/MII_PWRWN#/GPIO_ MII_OMP_PV MII_OMP_ UF_MHZ MII_RESET# MII_VREF G H0 RGMII_VREF R 0K_ R /F_.0U_ RG RSET K RG VREF RG RSET RG VREF RG RE RG GREEN RG LUE INT_RT_R <> INT_RT_G <> INT_RT_ <> INT_RT_R INT_RT_G INT_RT_ R R R 0/F_ 0/F_ 0/F_ m.v_n L TI00U00_.U_ 0.U_.V_PLL_ISP E H N E F TV RSET TV VREF.V_PLL_ISP TV_XTLIN TV_XTLOUT S RG HSYN RG VSYN _LK0 _T0.V_RG_ G H G H E V.U_.U_ L *.U_ HSYN <> VSYN <> RTLK <> RTT <> TI00U00_ V m 00m.V_N 0m mm m L V <> L_KLT_TRL <> INT_LVS_LON <> INT_LVS_IGON.V V.V_PLLPE_SS TI00U00_.U_ R0 R R R0 T T T0 T T T0 T T T T *.K_ *.K_ MP_GPIO MP_GPIO HMI_TXP_ HMI_TXN_ HMI_TX0P_ HMI_TX0N_ K J HMI_TXP_ M0 HMI_TXN_ L0 HMI_TXP_ K0 HMI_TXN_ J0 HP_ROM_SLK HP_ROM_ST HPLUG_ET HPLUG_ET L 0_.U_ 0 *U_.V_IFP.U_ L TI00U00_ 0 *.U_.V_PLL_IFPP.U_ 0.U_ U0.U_.U_ 0K_ 0K_ R *K/F_.V_P_V H HMI_RSET HMI_VPROE *.0U_ U T E E L M E L K K GPIO_/FERR/SYS_SERR/IGPU_GPIO_* GPIO_/NFERR/SYS_PERR/IGPU_GPIO_* L_KL_TL L_KL_ON L_PNEL_PWR HMI_TX_P/ML0_LNE_P HMI_TX_N/ML0_LNE_N HMI_TX0_P/ML0_LNE_P HMI_TX0_N/ML0_LNE_N HMI_TX_P/ML0_LNE_P HMI_TX_N/ML0_LNE_N HMI_TX_P/ML0_LNE0_P HMI_TX_N/ML0_LNE0_N UX_H0_P UX_H0_N HPLUG_ET HPLUG_ET.V_IFP.V_IFP.V_IFP_HV.V_HMI_PLL_HV.V_PLL_P.V_P_V HMI_RSET HMI_VPROE FLT PNEL.V_TV_ TV RE TV GREEN TV LUE IFP_TX_P IFP_TX_N IFP_TX0_P IFP_TX0_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N _LK _T _LK _T IFP_RSET IFP_VPROE F E0 E 0 0 J J E E F0 F G0 G H H0 L J L K 0 R 0_ V R 00//-Edison add, follow NV recommend. *0_ INT_TXLOUT INT_TXLOUT- UM_HMI_LK UM_HMI_T IFP_RST IFP_VPROE T0 T0 R R *.U_ TXLLKOUT <> TXLLKOUT- <> TXLOUT0 <> TXLOUT0- <> TXLOUT <> TXLOUT- <> TXLOUT <> TXLOUT- <> L_EILK <> L_EIT <> 0K_ 0K_ R *K/F_ V [LVS] PF created with FinePrint pdffactory Pro trial version Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev MP LN and Graphics ate: Monday, February, 00 Sheet 0 of

11 .V_N.V_N [ST H] [ST O].VSUS ST_TXP_ ST_TXN_ 0m m 0m 0m 0m R 0_ L.V_N.V_N.V_N.V_SP_ PY00T_ <> ST_TXP0 <> ST_TXN0 <> ST_RXN0 <> ST_RXP0 <> ST_TXP <> ST_TXN <> ST_RXN <> ST_RXP <> ST_LE# 0.U_ L0 0 L L 0U-.V_ 0U-.V_.U_ 0.U_ 0.U_.0U_ ST_TXP0_ E.0U_ ST_TXN0_ E.0U_.0U_ MLG00NJ_.V_PLL_SP_V 0U-.V_.U_ MLG00NJ_.U_.V_PLL_SP_SS.U_ TI00U00_.U_.V_PLL_LEG.U_ 0.U_.U_.U_.V_SP_ ST_THRM.U_ R.K/F_ G G E E G G H H J J K K W V P E E E E 0.U_ E0 J UE FG-NVII-MP ST_0_TX_P ST_0_TX_N ST_0_RX_N ST_0_RX_P ST TX_P ST TX_N ST RX_N ST RX_P ST_0_TX_P ST_0_TX_N ST_0_RX_N ST_0_RX_P ST TX_P ST TX_N ST RX_N ST RX_P ST_LE#/GPIO_.V_PLL_SP_V.V_PLL_SP_SS.V_PLL_LEG.V_SP_.V_SP_.V_SP_.V_SP_.V_SP_.V_SP_.V_SP_.V_SP_.V_SP_ ST_TERMP ST SE OF US US0_P US0_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N RSV RSV RSV RSV US_O0#/GPIO_ US_O#/GPIO_ US_O#/GPIO_ US_O#/GPIO_/MGPIO_ US_O#/GPIO_/MGPIO_.V_PLL_US.V_US_UL.V_US_UL US_RIS_ U U U U U U V V W W W W W W Y Y T T T T T P Y Y T USP USP- USP USP- USO#0 USO# USO# USO# USO#.V_US_PLL 0.U_.V_US_UL US_RIS_ L.U_.U_ R /F_ USP0 <> USP0- <> USP <> USP- <> USP <> USP- <> USP <> USP- <> USP <> USP- <> USP <> USP- <> USP <> USP- <> USP <> USP- <> TI00U00_ L0.U_ 00//: Page the resistor R from 0ohm change to ohm(follow NV suggest) V INT LEFT US- INT LEFT US- ard Reader RN0 USO# USO#0 USO# USO# R NEW R TI00U00_ LUETOOTH EXT US(PJ) MINI R- V_S 0KX_PR 0K_ m VSUS 0m US PULL-OWN USP RN USP- USP0 RN USP0- USP RN USP- ST_TXP T G ST TX_P US0_P USP0 <> ST_TXN G ST TX_N US0_N USP USP0- <> Fingerprint RN T USP ST_RXN USP T F ST RX_N US_P.U_.U_.U_.U_.U_.U_.U_.U_ ST_RXP USP- USP- T F ST RX_P US_N RN USP US_P USP US_N USP- USP RN USP-.V- coupling capacitor for ST US_P USP USP- USP RN Placement put near ST trace that L ST_0_TX_P US_N L ST_0_TX_N USP- cross through.v and US_P USP K ST_0_RX_N US_N USP- L ST_0_RX_P RSV USP RN RSV USP- USP RN USP- USP- RN USP USP0- RN USP0 USP RN USP- USP RN USP- USP RN USP- USP RN USP- KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev MP ST and US ate: Sunday, March 0, 00 Sheet of PF created with FinePrint pdffactory Pro trial version

12 E_SI# KSMI# R R *0K_ *.K_ <0> <0> H_SIN0 H_SIN V T T T T T T0 H_SIN MP_GPIO MXM_PRESENT# MP_GPIO MXM_RUNPWROK PE_RST_MXM# P N R M M0 UF FG-NVII-MP H_ST_IN0/GPIO_ H_ST_IN/GPIO_/MGPIO_0 H_ST_IN/GPIO_/MGPIO_ GPIO_/PWRN_OK/SPI_S GPIO_/NMI/PS_LK0 GPIO_/SMI#/PS_T0 GPIO_/SI/PS_LK GPIO_/INIT#/PS_T SE OF H H_OK_EN#/GPIO_ H_OK_RST#/GPIO H_ST_OUT/GPIO_ H_ITLK H_RESET# H_SYN/GPIO_ SLP_S# SLP_RMGT# SLP_S# R P R MP_GPIO MP_GPIO H_SOUT H_ITLK H_RESET# H_SYN R T T H_SOUT H_SYN H_ITLK H_RESET# *K_ SUSR# R 0_ SLP_RMGT# SUSR# R T 0_ H R _ R _ R _ R _ R _ R _ R _ R _ EMI Solution H_SOUT H_SYN H_RESET# H_ITLK R00 0_ SUS# <> SUS# <> H_SOUT_O <0> H_SOUT_M <0> H_SYN_O <0> H_SYN_M <0> H_ITLK_O <0> H_ITLK_M <0> H_RESET#_O <0> H_RESET#_M <0> 0P_ 0P_ 0P_ 0P_ MP STRPPING H_RESET# (LN) 0 MII RGMII (EFULT) H_SOUT_R, LFRM# (IOS) 00 LP (EFULT) 0 PI IOS 0 SPI IOS RESERVE (SPI) MP_SPKR (oot MOE) 0 USER TLE (EFULT) SFE TLE H_SYN_R (SIO LOK) 0.MHz (EFULT) MHz SPI_O, SPI_LK (SPI LOK) 00 MHz 0 MHz 0 MHz MHz V_S R0 R 0K_ *0K_ H_RESET# <> ST-O_PRESENT# <> <> <> GTE0 <> RIN# <> E_SI# <> KSMI# SM_INTRUER# MP_LI# T R 0_ T SIO_PME# RI# PM_T# M K K M P P L P N0 GPIO_/SUS_STT/LMTR_EXT_TRIG# 0GTE/GPIO_/FNTL KRRSTIN#/GPIO_/FNRPM SIO_PME#/GPIO_/SPI_S EXT_SMI#/GPIO_ RI#/GPIO INTRUER# LI# LL# MIS MP_VI0/GPIO_ MP_VI/GPIO_ MP_VI/GPIO_ SPKR H H H K R VORE.I0_R R_PPE# R_WKE# T T T *K_ MP_SPKR <0> V V V V R R R R R R R R *.K_.K_ *.K_.K_ *0K_ 0K_ *0K_ 0K_ H_SOUT MP_SPKR H_SYN LFRME# <,,> V W W0 Y0 0 W Y FI_RSV0 FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV SM_LK0 SM_T0 SM_LK/MSM_LK SM_T/MSM_T SM_LERT#/GPIO_ THERM#/GPIO_ E G E F F K SM_LERT# PLK_SM <,> PT_SM <,> MSM_LK <> MSM_T <> THERM_LERT# <> V_S V_S R R0 R R 0K_ *0K_ *0K_ 0K_ MP_SPI_O MP_SPI_LK <> NSWON# elay 0ms <> RTRST# after S powerok <> RSMRST# <,> PWROK_E <,> HWPG_.V <,0> HWPG_.V <,> PU_OREPG U_ R _ R R0 P_ P_ T T T T *0K_ K_ Y MHZ PWRTN# RSTTN# R 0_ HT_VL MP_TI MP_TO MP_TMS MP_TRST# MP_TK XTL XTL R0 P M L T0 M P M U T T U T H H PWRTN# RSTTN# RT_RST# PWRG_S PWRG MEM_VL MP_VL/HT_VL PU_VL JTG_TI JTG_TO JTG_TMS JTG_TRST# JTG_TK XTLIN XTLOUT THERM_SI/GPIO_/MSM_LK THERM_SI/GPIO_/MSM_T THERM_LERT#/GPIO_/PWR_LE# FNRPM0/GPIO_0 FNTL0/GPIO_ FNTL/GPIO_ MPV_EN/HTV_EN PUV_EN SPI_S0/GPIO_0 SPI_LK/GPIO_ SPI_I/GPIO_ SPI_O/GPIO_ SUS_LK/GPIO_ UF_SIO_LK F F F N M K K M J P J MP_GPIO ORI0 ORI ORI HTV_EN MP_GPIO0 MP_SPI_LK EMIL_LE# MP_SPI_O SUS_LK_R SIO_LK R T T T T K_ PU_SI <> PU_SI <>.VSUS HTV_EN <,0> PU_VRON <> cer Suggest Reserve HP EEPROM 00//0 HP EEPROM R *.K_ R *.K_ V_S HP_WP PLK_SM PT_SM *.u/v_ U V 0 WP SL N S *T P_ P_ R *0M_ Y LK_KX LK_KX.KHz H H XTLIN_RT XTLOUT_RT SM/I PULL-UP PLK_SM R.K_ PT_SM R.K_ SM_LERT# R.K_ V_S TEST_MOE_EN PKG_TEST P P0 TESTMOE_EN R K_ NO PN N 00//-Edison: Removethese part R, R, R, R,, Q, Q MSM_LK MSM_T R R.K_.K_ V V_S 0 PF created with FinePrint pdffactory Pro trial version R00 0K_ R0 *0K_ R 0K_ R *0K_ R 0K_ R0 ORI0 ORI ORI *0K_ M/ I for "/" I0 I I M/ " 0 0 X 0 0 " 0 0 " U 0 " ual ore PU & MXM 0 " ual ore PU & UM " Single ore PU & UM *MP JTG HEER Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev MP H/SM/PMU/GPIO Sunday, March 0, 00 ate: Sheet of

13 .V_UL V_UL VRT RT_HG RT_HG RT_HG VRT_ VRT_ RTRST# SM_INTRUER# <> RTRST# <>.V_S V_S V N_ORE VRT VPU VPU VRT V_UL.V_UL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : MP POWER//RT Monday, February, 00 Z0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : MP POWER//RT Monday, February, 00 Z0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : MP POWER//RT Monday, February, 00 Z0 MP POWER PLNE/ & YPSS 0m RT 0MIL 0MIL 0MIL 0m 0m 0m.U_.U_ L G M M N U0 U M L H P L J V M M N N0 G R M E G F F E G J F M T0 U J J E T P G G N 0 J T H E N Y E Y J J J U N M R R U H M P T N R E J P Y T Y J T F J V E 0 F0 F V G0 G J E0 J J L E E N J V0 E E P H F R R N H G L N F M N V R M W J T T SE OF FG-NVII-MP UH SE OF FG-NVII-MP UH.U_.U_ U-.V_0 U-.V_0 R0 K_ R0 K_ U_ U_.U_.U_.U_.U_ R 0_ R 0_ 0.U_ 0.U_.U_.U_.U_.U_ R0 0_ R0 0_.U_.U_.U_.U_.U_.U_ R K/F_ R K/F_ *U_ *U_ Q MMT0 Q MMT0 U-.V_ U-.V_ U_ U_ R 0K/F_ R 0K/F_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_ U_ U_.U_.U_.U_.U_.U_.U_ N RT-T_ONN N RT-T_ONN.U_.U_.U_.U_ N.V_UL N.V_UL V0.0V.0V 0.0V W.0V.0V.0V.0V.0V W.0V.0V.0V.0V V.0V.0V U.0V Y.0V W.0V0 Y.0V U.0V U.0V Y0.0V.0V.0V V.0V Y.0V Y0.0V W0.0V V.0V0.0V N.V_VT L.V_UL L.V_UL H.V F.V G.V J.V R J G G R H R M K N H V L P L V F F M E H F M M V F Y G N R V E U E M Y E H PWR/ SE OF UG FG-NVII-MP PWR/ SE OF UG FG-NVII-MP G *SHORT_ P G *SHORT_ P.U_.U_ H00H H00H U-.V_ U-.V_.U_.U_.U_.U_ H00H H00H R.K/F_ R.K/F_.U_.U_.U_.U_ R 0K/F_ R 0K/F_ R M_ R M_ R.K/F_ R.K/F_.U_.U_.U_.U_ 0.U_ 0.U_ PF created with FinePrint pdffactory Pro trial version

14 LVS SINGLE_H N TXLLKOUT- _L L_V TXLLKOUT RIGHTNESS.U_ TXLOUT0- TXLOUT0 V TXLLKOUT _PWR 0 0 TXLLKOUT- TXLOUT- TXLOUT L_ON TXLOUT0 <> L_ON RIGHTNESS TXLOUT0- TXLOUT- L_EILK R 0_ TXLOUT L_EIT 0 0 TXLOUT L TXLOUT- <> USP- USP-_R V R.K_ <> USP USP_R TXLOUT R0.K_ TXLOUT- *RFM00M 0 0 L_EILK R 0_ ON0X_0 L_EILK L_EIT L_EIT <0> TXLLKOUT- <0> TXLLKOUT <0> TXLOUT0- <0> TXLOUT0 <0> TXLOUT- <0> TXLOUT <0> TXLOUT- <0> TXLOUT <0> L_EILK <0> L_EIT R *0_ R 0_ R0 0_.U-V L 000P_ L_KLT_TRL <0> E_L_KLT_TRL <> EMI Solution *000P_ *000P_ L POWER V lose to LVS ONN. MER MOULE POWER V _PWR U R 0_ <0> INT_LVS_IGON R 0_.U_ ISP_ON IN IN ON/OFF T0 OUT LV_.U_ R 0_ 0U-.V_.U_.0U_ L_V 0U-.V_ Q *O 0U-.V_ 000P_ V R EUSE UR'S SUGGESTION, *.K_ TIE HNGE FROM TO HIGH. onfirm by Joms R 0K_ Q *TEU _POWERON <> RT V NHW RTV N <0> INT_RT_R <0> INT_RT_G <0> INT_RT_ <0> HSYN <0> VSYN <0> RTLK INT_RT_R INT_RT_G INT_RT_ HSYN VSYN RTLK INT_RT_R INT_RT_G INT_RT_ R R R 0/F_ 0/F_ 0/F_ 0 0P_ 0P_ L L L 0P_ K0LL0_ K0LL0_ K0LL0_ 0P_ 0P_ RT_R RT_G RT_ 0P_ 0 RT_ONN T_ RTHSYN RTVSYN LK_ RTV.U_ RTVSYN *0P_ RTHSYN *0P_ <0> RTT RTT LK_ 0P_ V U R *0_ R 0_ RT_SENSE# <> T_ 0P_ 0 V.U_.U_ RTV.U_ INT_RT_R INT_RT_G INT_RT_ V_SYN V_ YP V_VIEO VIEO_ VIEO_ VIEO_ M00 SYN_OUT SYN_OUT SYN_IN SYN_IN _IN _IN _OUT _OUT 0 VSYN HSYN VSYN HSYN RTLK RTT LK_ T_ L L R R M00: L0000W0 IP: L00000 LM0SN_ LM0SN_.K_.K_ RTVSYN RTHSYN V R.K_ RTV R.K_ TV Out (SVHS) MiniIN -pin elete TVOUT MiniIN Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev LVS/RT/P-amera Monday, February, 00 ate: Sheet of PF created with FinePrint pdffactory Pro trial version

15 Giga LN MM/M V_LN.V_LN V_LN.V_LN R R.V_LN.V_LN <> <>.U_ L 00-00m L 00-00m L 00-00m L 00-00m <> <> <> <>.U_ 0mil 0mil 0mil R R 0mil R PIE-LN_RXP PIE-LN_RXN PIE-LN_TXP PIE-LN_TXN LK_PIE-LN LK_PIE-LN# @0_.UV_ M : 0.uF apacitor M : 0 ohm Resistor 0.U_.U_.U_.U_.U_ R R V/V_IO VL PIE_SS_V.U_.U_ TXP_E TXN_E PIE_WKE_R# LN_PERST# U V V V V V V VL VL GPHY_PLLV PIE_PLLV PIE_V PIE_V PIE_ VIO VIO VIO VIO VIO VP MM/M 0mm X 0mm -Pin QFN ISV XTLV V V V VL VL PIE_TXP PIE_TXN PIE_RXP PIE_RXN WKE# PERST# REFLK REFLK- TR- TR TR- TR TR- TR TR0- TR0 LINKLE# SP00LE# SP000LE# TRFFILE# GPIO 0 0 URT_MOE GPIO_SERILI GPIO0_SERILO 0mil ISV XTLV V LINKLE# R0 LN_TLE#.U_.U_ TXP_ TXP_ TXN TXP LN_TXN LN_TXP LN_TXN LN_TXP TX0N TX0P L L L M_WP.U_.U_ R 0_ 00-00m 00-00m 00-00m TXP_ TXP_ LN_TXN LN_TXP LN_TXN LN_TXP V R R R R R R R R R R0 R R @0_ TXP VL TXP VL VH TXN TXN TXP VH TXN TXN TXP VL VH elete LN within OK Selector P_ V_LN V Y MHZ R R0 R LN_XTL LN_XTL K/F_ K/F_.K_ R 0_ R UX_PRES VM_PRES _PWR PLK_SM_LN PT_SM_LN.K/F_ XTLO R VUXPRSNT VMINPRSNT _PWR SM_LK SM_T XTLO XTLI R SLK SI SO S# N/(ENERGY_ET) VP M_SL R SI R M_S S# R R ENERGY_ET_R R @0_ *.K_ *.K_.K_ *.K_ R 0_ V_LN ENERGY_ET <>.V_LN VIO_.V_LN LN_V TX0P TX0N Transformer elta- LFE-R:GIGIT U TT T T- MT MX MX- LN_MT0 LN_MX0 LN_MX0- /0/0' hange PN form 0Z0LN0 to 0Z0LN0 on -test P_ <> LN_LKREQ# V_S Q *TEU LN_LKREQ# V_S R K_ R 0_ N(LK_REQ#) MMKMLG/M REGTL REGTL REG_ R R LN REGTL LN_V TXP TXN LN_V TXP TXN TT T T- TT T MX- T- MT MX MT MX MX- 0 LN_MT LN_MX LN_MX- LN_MT LN_MX LN_MX- <,,> PIE_WKE# PIE_WKE_R# LN_V 0 TT MT LN_MT <> <> PIRST# PIE_RST# R0 0_ R V_LN *0_ R 0_ LN_PERST# LN POWER EEPROM V_LN.U_.U_ 0.U_.U_ TXP TXN T LFE-R MX T- MX- LN_MX LN_MX- R _ R _ LNMT_G R _ R _ <,> PT_SM FOR SF Q *N00E R 0_ RP *.KX_ PT_SM_LN 0 0.V_LN L U-.V_.U_ *@K0HS 0. V_LN 0mil VIO_ V_S R.K_ R *.K_ R *.K_ R0 *.K_ M_WP M_SL M_S.U_ U V 0 WP SL N S T V_LN V_LN R 0_ R 0_ RINGL TIPL LN_LINKLE# LN_V 0 LN_V RJ- N RING TIP LE_GREEN LE_P_ LE_ORNGE LE_YEL 000P-KV_0 EMI Solution LN_LINKLE# LN_TLE# <,> PLK_SM LN_LKREQ# Q *N00E R 0_ V_LN PLK_SM_LN V_LN.V_LN V_LN R0 R0 0mil *_0.U_ mil LN REGTL 0mil LN_REG_V mil LN REGTL 00.U_ Q MMJT 0mil.V_LN 0U-.V_.U_.U_.U_.U_.U_ EEPROM Strapping SO SI S# SLK c 0 *0P-KV_0 *0P-KV_0 EMI solution TIPL RINGL 0P_ N 0P_ FI_SP_HF_JE LN_TLE# LE_P_ 0 0P_ 0P_ LN_MX0 TX/0 LN_MX0- TX-/0- LN_MX RX/ LN_MX N/ LN_MX- N/- LN_MX- RX-/- LN_MX N/ LN_MX- N/- RJ-&RJ- Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev GigaLN M/RJ & RJ Friday, March 0, 00 ate: Sheet of PF created with FinePrint pdffactory Pro trial version

16 VPU 0 <,> USON#.U_ U IN OUT IN OUT OUT EN# - O# R0 *.K/F_ USPWR 00U-.V_ 000P_ LI SWITH V *0u/0V_ TPS0GNR R0 00K_ R.K_ <> USP0- <> USP0 L WM-0-00T USP0-_R USP0_R /0/0' Implement ES diode on -test 0 Z0-0H_ES Z0-0H_ES N SYUIN_US LEFT US elete IR Function 00/0/ VPU nda GPIO list have internal PU VSUS R *0K_ SS Q INT_LVS_LON <0> E_FPK# <> <> USP- <> USP L WM-0-00T USP-_R USP_R /0/0' Implement ES diode on -test Z0-0H_ES USPWR 00U-.V_ Z0-0H_ES 0 000P_ N SYUIN_US LEFT US R0 *0K_ 0.U_ SS R0 0_ R0 0_ *SS LI# TEU L_ON <> MP_LI# <> LI# <> MR R0 0_ VPU PU M LUETOOTH LUETOOTH MOULE ONNETOR VSUS T_POWER Power oard FN <> T_POWERON# H H-P P *EMIP 00// add <> USP <> USP- <> T_LE T_POWER T_LE H h-cd0p- EMI solution P *EMIP H H-P- ME-00 U_ H h-tcbcdp H H h-tcbcdp h-tcbcdp H h-tcbcdp H h-cdp P *EMIP P P *ME-P *ME-P 0U-.V_ P *EMIP H h-cdp P *ME-P P0 *EMIP H h-tcbexdp- H H-P- H H-P- P *EMIP P *EMIP P *EMIP.P_ H0 h-cdp H h-cdp H h-tpbpsdp- H h-cdp- H0 h-cdp- H H h-tcbcdp h-tcbcdp H H h-tcbcdp h-tcbcdp Q0 O H h-cdp P N0 *EMIP H h-cdn.p_ T_ONN P *EMIP P *EMIP P *ME-P 00// add P P P *ME-P *ME-P *ME-P 000P_ H H-P- H H-scdp- P *EMIP H0 h-cdp- H H-P- H H-P- H h-cdp- H h-cdp- H h-cdp- P0 P P P P P 0/ PF created with FinePrint pdffactory Pro trial version *ME-P *ME-P *ME-P *ME-P *ME-P *ME-P Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev US/T/LI/HOLE Sunday, March 0, 00 ate: Sheet of

17 MINI-ard MINI-ard Port-.V V L WS_LKR K0LM-T_ *0P_ 0 L.U_.U_ V_MINI K0LM-T_ 0 N.V *00U-.V_.U_ If M.P must N all debug R.V WS_TR 0 R *0_ <,> PLTRST# WS_LKR.V R *0_ <> PI_LK_EUG LE_WPN# T RF_LE# LE_WLN# LE_WWN# R *0_ 0 US_ US_- <> PIE-MINI_TXP PETp0 <> PIE-MINI_TXN PETn0 SM_T SM_LK 0 R *0_.V <> PIE-MINI_RXP PERp0 VSUS_MINI <> PIE-MINI_RXN PERn0.Vaux R 0_ PERST# S 0 V_MINI V.U_ VSUS VSUS_MINI *.U_ RF_LE# <> USP <> USP- <> PT_SM <,> PLK_SM <,> PIE_RST# <,> RF_EN <>.U_ 0.U_ elete MINI-ard Port- <> <> <> <,,> LK_PIE_MINI LK_PIE_MINI# MINI_LKREQ# PIE_WKE# R 0_ MINI_REQ_LK REFLK REFLK- LKREQ# WKE# 0.V.V RP 0X_ RP0 0X_ R 0_ LFRME# <,,> L <,> L <,> L <,> L0 <,> Q MINIPI_E_ONN_WL *TEU VSUS New card NEW R'S POWER SWITH PIE_WKE# V_S <> R 0_ PPE#_E <> <> <> <> Q *TEU <> <> <> PIE-NEW_TXP PIE-NEW_TXN PIE-NEW_RXP PIE-NEW_RXN LK_PIE_NEW LK_PIE_NEW# <> PPE# NEW_LKREQ# <> <> R 0_ PPE# NEW_V PERST# NEW_VUX NEW_.V NEW_SMT NEW_SMLK PUS# USP USP- N PETp0 0 PETn0 PERp0 PERn0 0 REFLK REFLK- PPE# LKREQ#.V.V PERST#.VUX WKE# 0.V.V SM_T SM_LK RESERVE RESERVE PUS# US_ US_- 0 U TPSPWG NEW_V V..VOUT..VOUT V_S NEW_VUX UXIN UXOUT.V NEW_.V..VOUT..VOUT PIE_RST# SYSRST# STY# PPE# SHN# PPE# PUS# PUS# RLKEN PERST# N PERST# 0 O# 0 PPE# : ( Internal Pull Up, active low when card support PIE ) PUS# : ( Internal Pull Up, active low when card support US ) SHN# : ( Internal Pull Up ) NEW_V /0/0' el R and for reset issue on -test EXPR-FOXONN V_S V.V Q N00E RP.KX_ PT_SM NEW_SMT.U_.U_.U_.U_.U_ NEW_V Q NEW_VUX NEW_V NEW_.V N00E 0 0 PLK_SM NEW_SMLK.U_.U_.U_.U_.U_.U_ Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev MINI PI-E card & NEW R Sunday, March 0, 00 ate: Sheet of PF created with FinePrint pdffactory Pro trial version

18 TP SWITH E-KEY ST H LEFT# SW MISKI_SWITH_. SW <,> MX0 MY0 <,> MISKI_SWITH_. N RXP RXN TXN TXP ST_RXN0_ ST_RXP0_.0U_.0U_ ST_TXP0 <> ST_TXN0 <> ST_RXN0 <> ST_RXP0 <> RIGHT# SW MISKI_SWITH_. MX0 MY0:E-Key.V.V.V 0 V V V RSV V 0 V V ST-H HV.0U_.0U_.U_ HV.U_.U_ R 0_ 00U-.V_ V <> TPT <> TPLK TP ONN V L KP0HST. TP_V V mil R R.U_ N.K_.K_ L LZ0-0MT 0. TPT_R L LZ0-0MT 0. TPLK_R RIGHT# 0 TPT P_ 0 LEFT# TPLK P_ TOUH_P_TP_P EMI solution near connector O (ST) N RXP RXN TXN TXP ST_RXN_ ST_RXP_.0U_.0U_ ST_TXP <> ST_TXN <> ST_RXN <> ST_RXP <> P ST-O_PRESENT# <> V V 0 V_O R.K_ M ST-O V_O 00mil L0 0_ V 000P_.U_.U_.U_ 00U-.V_ PF created with FinePrint pdffactory Pro trial version Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev ST-H & ST-O&TP Monday, February, 00 ate: Sheet of

19 E V_R VSUS IN R REER 0 X_/MS_0/S_0 ()S-V *0U-.V_.U_ *.U_.U_.U_ S_ ()S-T0 X_RE#/S_ ()S-T 0 X_WE#/S_ ()S-T ()X-V S_LK ()S-T X_# S_M ()S-LK ()X- X_R/# S_# ()S-M ()X-R/ X_RE#/S_ S_WP# S- ()X-RE X_E# S-WP ()X-E X_LE ()X-LE X_LE ()X-LE X_WE#/S_ ()X-WE X_WP# ()X-WP V_R R0 00K/F_ R 0_ R_RST# X_LE X_LE U_ X_/MS_0/S_0 S-V S_ S-T0 X_RE#/S_ S-T U_.U_ X_WE#/S_ S-T X-V VREG S_M S_LK X_# S_M S-T V_PLL S_M S-LK X- X_R/# R0.K/F_ X_0 S_# S-M X-R/ X_RE#/S_ RREF S_T/X_0/MS_ S_WP# S-/ X-RE X_E# V_R X_ MS_SLK X_LE S_LK/X_/MS_LK R 0_ S-WP X-E N R 0_ S_LK X-LE X_LE S-VSS X-LE X_WE#/S_ <> USP- M V V_R S-VSS X-WE 0 X_WP# <> USP P S- X-WP.U_ X_0 X_/MS_ X_/MS_0/S_0 MS-V X-0 X_ S_T/X_/MS_ X_/MS_ MS-T0 X- X_/MS_ V_R X_/MS_ X_/MS_ N N 0 MS-T X- 0 0 X_/MS_ MS-T X- X_ RTSE-GR V_R MS_# MS_SLK MS-T X- X_/MS_S V_IN MS_INS# MS_# MS-SLK X- X_/MS_0/S_0 V_X X_/MS_ X_/MS_S MS-INS X- X_/MS_ R_V S_T/X_/MS_ MS-S X-.U_ 0.U_ R 0_ VREG V_R.U_ 0 U VREG V R0 P_ Y *0M_ MHz LK_MX XTLI LK_MX0 XTLO G_PLL P_ MOE_SEL MOE_SEL R_RST# X_E# X_RE#/S_ X_WE#/S_ X_R/# X_WP# S_T0/X_/MS_0 X_/MS_ X_/MS_S X_/MS_ X_/MS_S EMI Solution MS_SLK S_LK X_/MS_0/S_0 X_/MS_0/S_0 X_/MS_ X_/MS_ X_/MS_ MS_SLK MS_# X_/MS_S V_X V_X V_X V_X X_0 X_ X_/MS_ X_/MS_ X_ X_/MS_S X_/MS_0/S_0 X_/MS_ XTL_TR GPIO0 EEO EES EESK EEI 0 X_# S_WP S_# MS_ X_ MS_ RST# X_LE X_E# X_LE 0 S_T/X_RE# S_T/X_WE# X_RY S_T/X_WP#/MS_ *P_ *P_ 0 N ()MS-V ()MS-T0 ()MS-T ()MS-T ()MS-T ()MS-SLK ()MS-INS ()MS-S ()S/()MS/()X- ()S/(0)MS/()X- *R_REER_TTN 0 N MS-VSS MS-VSS PROONN-MXP N (0)X-0 ()X- ()X- ()X- ()X- ()X- ()X- ()X- 0 SIO- SIO- XG- X- V_R R0 *0_ X_# S_WP# S_# MS_ X_ MS_ X_/MS_ X_ R0 *0_ R 0_ S_ RREER POWER T T T0 T T MOE_SEL 0mil V_X R *0K_ *p/0v_.u_.0u_.0u_.0u_ R/ = 0K/pF => R0 Reside R/ = N / N => R Reside PF created with FinePrint pdffactory Pro trial version Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev RTSE -ard Reader Monday, March 0, 00 ate: Sheet of E

20 OE(L/LS-V) L L R 0_ O SPK OUT FRONT-L FRONT-R EP /0/0' Empty on -test R *L@0_ MUTE_L MI-VREFO-R R.K_ MI-VREFO MI-VREFO-L R0.K_ L_VREF 0U-.V_ V_O MI_R MI_L O OE(L) Power V L TI00G.U_.U_.U_ V_O 0U-.V_ O U *G-JTEU R *0_ V VEN VEN VOUT 0 0.U_ 0U-.V_ J R *K_ INT MI array N MI_INTL INT_MI *P_ O 00.U_ O R.K_ MI-VREFO HP Jack O V_O R SURR-L 0K/F_ L_JREF 0 U FRONT-R MONO-OUT V SURR-L JREF FRONT-L Sense N MI-VREFO-R GPIO MI-VREFO 0 LINE-VREFO MI-VREFO-L VREF VSS V LINE-R LINE-L MI-R MI-L LINE-R LINE-L MI-R MI-L 0.U_.U_ U-V_ U-V_ LINE-R_ <> LINE-L_ <> MI_R <> MI_L <> Vo=.*(RR)/R=.V EMI suggest / R *K_ R 0_ R 0_ V_V O SURR-R SURR-R VSS N N N L/LS_V -R 0 - -L MI-R MI-L MI_INT_R MI_INT_L 0 0 U-V_ U-V_ MI_INTL O *.U_ P_ *.U_ R 0_.U_.U_.U_ 000P_ R *0K_ R 0K_ R *0K_ R *0K_ R *0K_ R *0K_ G_Lv G_Lv G_ttack G_ON/OFF G_Recovery G_Recovery <> SPIF_OUT EP R 0_ MUTE_L L SPIF_OUT_ K00LL 0. MI-LK EP SPIFO V MI-//GPIO0 MI-//GPIO VSS ST-OUT IT-LK VSS ST-IN V SYN RESET# PEEP N N Sense SENSE SENSE <> O P_ *.U_ O P_ 000P_ 000P_ O R 0K_ O R *0K_ R 0K_ R 0K_ R 0K_ R 0K_ 0 V.V R 0_ R *0_ Z_V 0U-.V_.U_ V 0 0U-.V_ 0.U_ Z_SIN PEEP Z_V R _ H_RESET#_O <> H_SYN_O <> H_SIN0 <> G-attack-time selection G_ttack ( pin) ttack time ms ms G ON/OFF selection G_ON/OFF ( pin) G ON/OFF ON OFF G-recovery-time selection G_Recovery (0 pin) G_Recovery ( pin) Recovery Time.0 s.0 s.0 s.0 s G-on-level selection G_Lv ( pin) G_Lv ( pin) G ON Level Output Po (RL= ohm). dv. W.0 dv.0 W. dv 0. W.0 dv 0. W R 0_ 0P_ 0P_ EMI Solution H_ITLK_O <> V_V O V_O H_SOUT_O <> M N R *0_ V_S M RSV R 0_ VSUS <> H_SOUT_M _SO RSV.V <> H_SYN_M H_SIN_M _SYN R _ <> H_SIN _SI 0 <> H_RESET#_M _RST# _LK H_ITLK_M <> SP_STY ON/OFF & HP_STY ON/OFF SP_STY ( pin) HP_STY ( pin) SP_STY ( pin) HP_STY ( pin) SP_STY ON/OFF ON OFF OFF OFF HP_STY ON/OFF ON OFF OFF OFF G_Lv G_Lv G_ttack G_ON/OFF G_Recovery 0 U G_Lv G_Lv V G_ttack G_ON/OFF V_P G_Recovery V_HP Test Test Test Test V_SPR V_SPL VSS_P SP_OUTL VSS U-V_ U-V_ INSPKL O 0 0P_ EMI Solution R0 0_ 0 0P_.U_ EMI Solution SPK FRONT-L FRONT-R 0 U-V_ U-V_ FRONT-L- FRONT-R- V R0 R 0K/F_ 0K/F_ O R R0 0 0 G_Recovery FRONT-L- 0K/F_ 0P_ PREOUT-L FRONT-R- 0K/F_ 0P_ PREOUT-R U-V_ G_Recovery SP_INL PREOUT_L SP_INR PREOUT_R VREFSP Panasonic N SP_OUTL SP_OUTL SP_OUTL SP_OUTR SP_OUTR SP_OUTR 0 INSPKR- INSPKL- INSPKR SPK INSPKR- INSPKR INSPKL- INSPKL L L L L K0LL 0. K0LL 0. K0LL 0. K0LL 0. INSPKR-N INSPKRN INSPKL-N INSPKLN 0 *P_ *P_ 0 *P_ N SPEKER_H. *P_.U_ <> <> MP_MUTE# MUTE FUNTION EP HP_MUTE# R V U U0 TSH0FU *0_ TSH0FU MUTE_SPK MUTE_HP SP_STY SP_STY HP_STY HP_STY N N 0 _P 0 _SPL _SPR EP EP EP SP_OUTR HP_OUTL EP EP EP EP EP EP 0 HP_INL HP_INR HP_OUTR EP 0 EP EP N HPINL HPINR R0 R R R P_ 0K/F_ 0K/F_ 0K/F_ 0K/F_ HPL SURR-L SURR-R HPR HPL <>.U_.U_ HPR <> SURR-L SURR-R HP eep PEEP U-V_ EEP_ R O 0K_ MP_SPKR <> O V R *0_ V_V V_O O P_ P_ P -- ISOLTE Modify P to P_~ 00P_ R K_ *0U-.V_ R 0_ 0U-.V_.U_ O 0 U-V_ 00 U-V_ 0 U-V_ O 0 U-V_ U-V_ U-V_ Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev L & M/MP/SPK/MI Monday, February, 00 ate: Sheet of 0 PF created with FinePrint pdffactory Pro trial version

21 MI 0U V <0> MI_L <0> MI_R <0> LINE-L_ <0> LINE-R_ MI_L MI_R LINE-L_ LINE-R_ L L L L0 K0HS_ K0HS_ K0HS_ K0HS_ LINEINL_SYS LINEINR_SYS O O 0 0p/0V_NPO_ 0p/0V_NPO_ LINE IN MI_L MI_R MI_J# 0p/0V_NPO_ 0 0p/0V_NPO_ LINEIN_J# N Normal OPEN Jack N MI LUE Normal OPEN Jack LINEIN MI_J# O 0U LINEIN_J# *0U HPPLG# V O V O <0> HPL <0> HPR R /F_ HPL_SYS L K0HS_ R /F_ HPR_SYS L0 K0HS_ HeadPhone OUT/SPIF 0p/0V_NPO_ O 0p/0V_NPO_ HPPLG# HPL_SYS HPR_SYS SPIF_OUT O V_SP LK N 0 rive LE I SPIF Normal OPEN Jack Q TYU V_SP V 0K K HPPLG# <0> SPIF_OUT VR <0> SENSE SENSE R R R 0K/F_ 0K/F_.K/F_ MI_J# LINEIN_J# LINEOUT_J# <> IGVOL_UP <> IGVOL_N IGVOL_UP IGVOL_N VR VR_XRE0_NOLE V LINEOUT_J# V R 0K_ R HP_ON 0K_ Q N00E HPPLG# Q N00E O O Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev udio Jack ate: Monday, February, 00 Sheet of PF created with FinePrint pdffactory Pro trial version

22 WPE I/O RESS SETTING VPU V R-0 Index I/O ddress ata L LMG0SN_ VPU 0 0 XOR TREE TEST MOE.U_ 0.U_.U_.U_.U_.U_ U V V V V V V 0 0.U_.U_ E V.U_.U_ 0 ORE EFINE 0 Eh Fh Eh Fh SHM=0: Enable shared memory with host IOS R0 _POWERON R 0K_ R E_SOUT_R_EUG R *0K_ <,,> LFRME# <,> L0 <,> L <,> L <,> L For PILK <> LP_LK_E LP_LK_E <> LKRUN# <> GTE0 R <> RIN# _ <> E_SI# <> E_FPK# <> RE_KEY 0P_ For PIRESET <,> PLTRST# <,> USON# <> SERIRQ <> KSMI# <,> MX0 <> MX <> MX <> MX <> MX <> MX <> MX <> MX <,> MY0 <> MY <> MY <> MY <> MY <> MY <> MY <> MY <> MY <> MY <> MY0 <> MY <> MY <> MY <> MY <> MY <> MY <> MY <> MLK <> MT <> MLK_PU <> MT_PU <> TPLK <> TPT <> HG-EN S LP_LK_E SI#_R MLK MT MLK_PU MT_PU LFRME L0 L L L LLK GPIO/LKRUN G0 KRST ESI/GPIO GPIO/LRQ GPIO0/LPP LREST GPIO/PWUREQ SERIRQ GPIO/SMI KSIN0 KSIN KSIN KSIN KSIN KSIN KSIN KSIN KSOUT0/JENK KSOUT/TK KSOUT/TMS KSOUT/TI KSOUT/JEN0 K KSOUT/TO KSOUT/RY KSOUT KSOUT KSOUT KSOUT0 KSOUT KSOUT/GPIO KSOUT/GPIO KSOUT/GPIO KSOUT/GPIO/XOR_OUT GPIO0/KSOUT GPIO/KSOUT GPIO/SL GPIO/S GPIO/SL GPIO/S GPIO/PSLK GPIO/PST GPIO/PSLK GPIOPST GPIO/PSLK GPIO/PST LP SM PS/ / / GPI0/0 GPI/ GPI/ GPI/ GPIO0/ GPIO0/ GPI/0 GPI/ GPI/ GPI/ GPIO0/T GPIO0/ GPIO0 GPIO0/ GPIO/SL GPIO0/IRTX 0 GPIO/S 0 GPIO/_PWM GPIO/H_PWM GPIO/T GPIO0/F_PWM GPIO/TK GPIO GPIO/TMS 0 GPIO/TI GPIO/E_PWM GPIO/IRRXM/TRST GPO/SL GPIO0/TO GPIO/T GPIO/IRTX/RY GPIO/S GPIO GPO/TRIS 0 GPO/R0 GPIO 0 TIMER SPI GPIO/T GPIO0/T GPIO/T GPIO/_PWM GPIO/_PWM GPIO/_PWM GPIO/G_PWM GPIO/SPI_I GPO/SPI_O/SHM GPIO/SPI_SK GPIO/IRRX/SIN GPIO0/IRRX_IRSL0 GPIO/IRTX/SOUT IR GPIO/IRRXM/SIN_R GPIO/IRRXL GPIO/IRTX GPO/SOUT_R/R FIU F_SI F_SO 0 F_S0 F_SK HWPG NSWON#_R RT_SENSE# RF_EN IRRX T T0 T T T E_SOUT_R_EUG R _ R _.U_.U_ S SPI_SI_uR SPI_SO_uR SPI_S0#_uR SPI_SK_uR MTEMP <> PIE_WKE# <,,> SYS_I <> IGVOL_UP <> IGVOL_N <> -SET <> PUFN# <> PPE#_E <> V-SET <> IN <> NSWON# <> LI# <> SUS# <> SUSLE# <> TLE0# <> TLE# <> VRON <> MINON <,,0> MP_MUTE# <0> E_PROHOT# <> SUSON <,0> ENERGY_ET <> HP_MUTE# <0> /# <> S_ON <,0> PUMEMHOT# <> NSWON# <> T_POWERON# <> _POWERON <> FNSIG <> E_L_KLT_TRL <> NUMLE# <> PWRLE# <> PSLE# <> RT_SENSE# <> RF_EN <> ELL-SET <> RSMRST# <> SUS# <> PWROK_E <,> N_TEMP <0> SMUS PULL-UP ER I SPI FLSH SHM RF_EN R0 0K_ isabled ('') if using FWH device on LP. Enabled ('0') if using SPI flash for both system IOS and E firmware MLK_PU MT_PU VPU U0 SPI_SI_uR R0 SO SPI_SO_uR 0K_ SI SPI_SK_uR SK SPI_S0#_uR E VPU MLK_PU R.K_ MT_PU R.K_ MLK R.K_ MT R.K_ VPU U SL 0 S WP V L0 0.U_ WX0VSSIG VPU V HOL WP.U_ VSS E_KX KX/KLKIN GPIO/LKOUT 0 E_LOK T R00 Y 0M_ R K/F_ E_KX KX WPE 0 VORF V_POR VREF 0 V_POR# VREF_uR R0.K_ R 0_ VPU VPU INTERNL KEYOR STRIP SET VPU P_ P_ VORF_uR 0 V VPU MY0 R0 0K_ RT_SENSE# R0 *.K_ Internal pull-up V.KHZ L HZ000R_ U-V_ R R E E <> HWPG_NORE S 0K_ *0K_ <> HWPG_.V_N *S <> HWPG_SYS S HWPG <,0> HWPG_.V 0 *S <,> HWPG_.V S <0> HWPG_.V <0> HWPG_.V_S <,> PU_OREPG S *S *S Quanta omputer Inc. PROJET : Z0 Size ocument Number Rev E WPE_0G & SPI Monday, February, 00 ate: Sheet of PF created with FinePrint pdffactory Pro trial version

ZY5/ZY5D SYSTEM BLOCK DIAGRAM

ZY5/ZY5D SYSTEM BLOCK DIAGRAM PU ORE ISL PGE ZY/ZY SYSTEM LOK IGRM N ORE.V PGE N RUN.V PGE R II SMR_VTERM.VSUS(TPSREGR) PGE SYSTEM POWER ISL PGE INT or EV selector Resistor RII-SOIMM PGE RII-SOIMM PGE RII /00 MHz RII /00 MHz M Griffin

More information

Sputnik Block Diagram

Sputnik Block Diagram P STK UP LYER : TOP LYER : SGN LYER : IN LYER : IN LYER : V LYER : IN LYER : SGN RUN POWER SW PG, RII-SOIMM PG RII-SOIMM PG /TT ONNETOR TT HRGER PG PG RII mhz RII mhz Turion Sempron W/W M Socket S P PG,,

More information

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET GP0 GP0 GP0 P0 GP0 GP GP GP GP GP GP GP P GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP00 UINO ONE PIN EFINE GP0 GP GP GP GP GP GP GP GP0 GP GP

More information

KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power

KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power KEIm aseboard REV TE PGES ESRIPTION.0.0 Oct//0 ll INITIL REVISION RELESE..0 Feb//0 ll MP REVISION RELESE PGE ESRIPTION lock iagram, History SoM onnector L onnector Ethernet URT nalog Peripheral Power KONO

More information

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103 core Tiny0.sch M000 M000-etc.sch -etc.sch US HU US-HU.sch Tiny0SK 0 M_ VV V V V V V V V V V VN VSYN VLK VUS OTGI OTGM OTGP IN0 S_LK S_n S_T0 S_T OUT0 INT INT INT RST ( 红色 ) Tiny0 Tiny0 P Power Supply S

More information

Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz

Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz V V Way type onnector US Type onnector x.v.v Regulators Headers for all pins sorted by pin no. (unpopulated) Prototyping area with power and GNs (unpopulated) RS Transceiver US to Serial onverter Expansion

More information

RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7

RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7 Place as close to pins of U as possible. RS HIP 0-00 RS-x emo/evaluation oard: RS-000 Thursday, ecember, 00 Size ocument Number Rev ate: Sheet of P XI P0 P0 P0 P0 P00 PN P0 P0 P0 P0 P0 P0 P0 P0 P XO -XM

More information

HF SuperPacker Pro 100W Amp Version 3

HF SuperPacker Pro 100W Amp Version 3 HF SuperPacker Pro 00W mp Version Revised 0 0 V Stamps KOOR This is the third generation HF SuperPacker Pro 00W Version home construction project offered by HF Projects. This is a group construction project

More information

Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode

Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode Reference Schematic for LN-SPI/SQI+GPIO Mode onfigurations SPI/SQI+GPIO Mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM

More information

Generated by Foxit PDF Creator Foxit Software For evaluation only.

Generated by Foxit PDF Creator Foxit Software   For evaluation only. I_ST I_SLK K_% R K_% R L_0 L_ L_ L_ KEY TON_STHL /F NN_ NN_ P M VS OUTL P OUTR VR MIIN VREF V HOSI LOSI R X pf LOSO.KHZ M_% pf HOSO X pf MHz HOSI 0 pf POWER Generated by Foxit PF reator Foxit Software

More information

PTN3356 Evaluation and Applicaiton Board Rev. 0.10

PTN3356 Evaluation and Applicaiton Board Rev. 0.10 E PTN Evaluation and pplicaiton oard Rev. 0.0 REVISION STORY : ------------------------------------- 0. June 0, 0 - ase on PTN_ONLY_REV.SN 0. July, 0 - OM changes due to long lead time items, LEs 0. July,

More information

8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1

8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1 isclaimer: IT is providing this schematic for reference purposes only. lthough the schematic was taken from a known working design, it is being provided "as is" without any express or implied warranty

More information

REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK

REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK REVISION HISTORY Notes - Unless otherwise noted. Resistances values in Ohms. apacitance values in micrarads (uf). ll 0.uF and 0.0uF capactors are decoupling and should be placed near the I they are shown

More information

Quickfilter Development Board, QF4A512 - DK

Quickfilter Development Board, QF4A512 - DK Quickfilter evelopment oard, QF - K nalog Inputs - U +.V +.V J N hannel J N hannel J N hannel J N hannel U +.V +.V U +.V U +.V Prototyping rea J J Optional +V External Power x Header 0." US onnector U

More information

PCB NO. DM205A SOM-128-EX VER:0.6

PCB NO. DM205A SOM-128-EX VER:0.6 V. M0 M M M M M M M MQM0 MQS0N MQS0P M M M0 M M M M M MQM MQSN MQSP U RM R0 Q00 M0 U Q0 M T Q0 M R Q0 M U Q0 M U Q0 M T Q0 M T Q0 M T M0 M U QS0N M U QS0P M0 M W0 Q0 M W Q0 M V0 Q0 M U0 Q M W Q W Q 0 V

More information

CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS-

CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- SPST SW L 0uH.uF TP HEER NO STUFF TP 0 HEER NO STUFF TP TP pf Y.uF.uF 0 HEER NO STUFF 0 HEER NO STUFF MHz, 0ppm pf.uf (OUT) (IN) R 0K /W % 0uF OUT OUT OUT OUT KLT L 0 L_MISO L_MOSI L_SK S_S- L_S- L_- L_

More information

Virtex 5 FF1136 DUT. Single Ended Socket Clocks 2X. Differential SMA MGT Clocks 2X D. Differential SMA Clocks 2X. Upstream Connector.

Virtex 5 FF1136 DUT. Single Ended Socket Clocks 2X. Differential SMA MGT Clocks 2X D. Differential SMA Clocks 2X. Upstream Connector. PGE System Monitor ux PGE System Monitor PGE System ce Upstream PGE Upstream onnector PGE Single Ended Socket locks X PGE ifferential SM locks X PGE ifferential SM MGT locks X PGE - Power us and Switches

More information

ZCRMZN00100KITG. Crimzon Development Board Kit. Product User Guide. Introduction. Kit Contents. Applying Power to Development Board

ZCRMZN00100KITG. Crimzon Development Board Kit. Product User Guide. Introduction. Kit Contents. Applying Power to Development Board ZRMZN0000KITG rimzon evelopment oard Kit PUG000-0 Product User Guide Introduction Zilog s ZRMZN0000KITG rimzon evelopment oard Kit is designed for use as a target with the rimzon In-ircuit Emulator (ZRMZNIE0ZEMG).

More information

B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History

B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History 0-SH-0 R-0 VEG STP0 (VI to PTx) Reference esign P# 00- Revision History SHEMTI SHEET ate uthor Version omments 0. ontents, Revision History Sept., 00 Tony W. Rev. Initial schematic. 0. Overview Oct., 00

More information

NV11,4Mx16 DDR, RGB, INTERNAL DVI-I, AGP.

NV11,4Mx16 DDR, RGB, INTERNAL DVI-I, AGP. . NV.V 00PF 00PF 00PF 0.UF 0.UF 0.UF 0.UF 0UF 0UF 0 0.UF 0.UF.V TO- -pin package Semtech Z, Unisem US0 00 NV O- RG-PWR-IN.V@ /- 0mV 0UF 00PF 00PF 0 00PF 0UF 00PF 0UF 0 0.UF 0 00PF 0.UF 0 O0 U POWR SNS

More information

CONTENTS: REVISION HISTORY: NOTES:

CONTENTS: REVISION HISTORY: NOTES: ONTENTS: PGE - ONTENTS PGE - POWER, XOS PGE - SI, SI, JTG PGE - S/eMM, US, HMI, GPIO, OMPOSITE PGE - SOIMM REVISION HISTORY: V.0 - /0/0 NOTES: These reduced schematics omit core SMPS and LPR circuitry

More information

Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header

Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header esign Overview Page Power,Flash,Scard User switch,reset switch. Page Ethernet Page udio Page US Page JTG,OOTSW,LE,Header isclaimer: Schematic's are for reference only. provides no warranty for the use

More information

HOSCO HOSCI AS M AS M C1 18P C2 18P C1 18P C2 18P GND VCC3 GPIOK7 R82 R82 10K A20 10K. #OffHook. FmHook #TRANSLED. VxBP 0.1U 0.

HOSCO HOSCI AS M AS M C1 18P C2 18P C1 18P C2 18P GND VCC3 GPIOK7 R82 R82 10K A20 10K. #OffHook. FmHook #TRANSLED. VxBP 0.1U 0. 0 #E0 GPIOK #MWR #MR #FWE HOSI KEYI0 GPIO0 HOSO V V VREFI KEYI GPIO GPIO_ V KEYO GPIO #E OUTR MIIN VMI GPIO_0 #LON V #HOL 0 0 #E KEYO GPIO 0 KEYO0 GPIO GPIO_ GPIO_0 #MR #MWR V V V V TSEL #E #E0 V HOSI

More information

PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector.

PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector. R SPIF output Power LO R SPIF input x Flash POR PWM LE x R* Lightning() P x pin Type connector US pin For Lightning & P T QFN RE PLY H Sel T PLY x PM Ext. MU H Sel T RE x S NE OP R* Size ocument

More information

1 INDEX & POWER, RESET 2 RF, SERVO & MPEG - MT1389E 3 MEMORY - SDRAM, FLASH/EEPROM 4 VIDEO OUT 5 AUDIO DAC WMA8766

1 INDEX & POWER, RESET 2 RF, SERVO & MPEG - MT1389E 3 MEMORY - SDRAM, FLASH/EEPROM 4 VIDEO OUT 5 AUDIO DAC WMA8766 OMMON_H_V MT (LQFP) V emo oard for Sanyo Slim H PUH INX & PO, ST F, SVO & MPG - MT MMOY - SM, FLSH/POM VIO OUT UIO WM NM TYP VI igital V SUPPLY V igital.v MT FV Servo.V MT LO_V Laser iode.v F V PIKUP H

More information

DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1.

DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1. R * SPIF output x Power LO R * R R SPIF input x POR Flash PWM LE x PM00 Lightning() P 0x0 0pin Type connector US 0pin For Lightning & P T0 RE PLY0 PLY H Sel Stereo T0 PLY0 T0 0x PLY 0x PM00 R Ext. MU H

More information

PCIextend 174 User s Manual

PCIextend 174 User s Manual PIextend 7 User s Manual Preliminary M6- February Sycard Technology 8-F Miraloma Way Sunnyvale, 98 (8) 79- (8) 79- FX PIextend 7 User s Manual Page. Introduction Sycard Technology's PIextend 7 PI extender

More information

Reference Schematic for LAN9252-HBI-Multiplexed Mode

Reference Schematic for LAN9252-HBI-Multiplexed Mode Reference Schematic for LN-HI-Multiplexed Mode onfigurations HI Multiplexed mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM

More information

L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE

L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE LX UGHTER RS TLE OF ONTENTS SL NO. ONTENTS PGE NO REV TLE OF ONTENTS VERSION HISTORY VERSION.0.. LOK IGRM URT-0 INTERFE N US INTERFE URT INTERFE PROFI US & SOFT IR INTERFE SOFT URTS REV NO. NTURE OF HNGE

More information

Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1.

Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1. Project: ate Version Items V.0 RWN Y PORJET SIM800+SIM8M_VTS Reference ONTENT HEKE Y V.0 SHEET of 7 POWER POWER -0V F0 0 L0 VIN LO X0 SM0 SWRH07 uh T-PIN-X TVS0 Z0 + 0 VT U0 VZ=V,Pd=W SM7 00uF V GN VOUT

More information

Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0

Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0 Fiber LE RJ M RYSTL EEPROM SRM & FLSH POWER PWRJK Jumper for GPIOs URT Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev lock diagram.0 ate: Tuesday, November, 00 Sheet of ,, /ISGPIOSTP

More information

AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115

AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115 PL ENOER OUNTER / PWM MOTOR ONTROL / GLUE LOGI PL YPSS PITORS LE0 LE LE LE ESTOP_U ESTOP_IRQ _USY _IN _OUT _/S _/S _OUT _IN _SLK 0.uF +.V 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF P0.[0:] [0:] 0 P0. P0. P0. P0.

More information

Virtex 5 FF1738 DUT. Single Ended Socket Clocks 2X. Differential SMA Clocks 2X. Differential SMA MGT Clocks 2X D. Upstream Connector.

Virtex 5 FF1738 DUT. Single Ended Socket Clocks 2X. Differential SMA Clocks 2X. Differential SMA MGT Clocks 2X D. Upstream Connector. PGE System Monitor ux PGE System Monitor PGE System ce Upstream PGE Upstream onnector PGE Single Ended Socket locks X PGE ifferential SM locks X PGE ifferential SM MGT locks X PGE 0- Power us and Switches

More information

AXM88180-EVB-RTL8211E-1 SMDK2440 Demo Board Schematic Index

AXM88180-EVB-RTL8211E-1 SMDK2440 Demo Board Schematic Index XM0-EV-RTLE- SMK0 emo oard Schematic Index Page : Schematic Index (This Page) Page : RTLE GigaPHY MHz rystal RJ- Transformer Page : Host Interface onnector Power Page : History Page : X0 EEPROM Note:.Please

More information

D28 D28 1N4001 1N4001 R301 R375 R k. 10k R82 R82. 47k. 47k USB_IN. 20k. 20k R87 R87 +3V. C uF. C uF GND +1V8. C uF.

D28 D28 1N4001 1N4001 R301 R375 R k. 10k R82 R82. 47k. 47k USB_IN. 20k. 20k R87 R87 +3V. C uF. C uF GND +1V8. C uF. POWER_KEY POWER_OFF US_IN WKEUP H_ET HG_STTUS PLYKEY +VRT VT VUS +VRT LI_.V LI_.V VUS VT VTT VTT VTT +V +V +V +V VTT V +V T uf uf R k R k uf uf R k R k VIN VOUT U XPM U XPM Vbat ON ON ON ON KW ON/OFF KW

More information

DOCUMENT NUMBER PAGE SECRET

DOCUMENT NUMBER PAGE SECRET OUMENT NUMER PGE SERET / SERET OUMENT NUMER PGE / Spartan onfiguration SPI Flash Q S V W/VPP HOL VSS U MPVME R 0 R.K 0.U 9 IO_LP 0 IO_LN VREF_ G IO_L9P_ G IO_L9N_ F IO_L0P_ F IO_L0N_ IO_L9P_ IO_L9N_ 0

More information

Block Diagram SGTL5000 PG. 3. Power PG. 8. Communication PG.6. I2S Signals PG.7. Analog Inputs PG.4. Analog Outputs PG.5.

Block Diagram SGTL5000 PG. 3. Power PG. 8. Communication PG.6. I2S Signals PG.7. Analog Inputs PG.4. Analog Outputs PG.5. lock iagram I R Select I/SPI Mode Select MLK Source ommunication PG. US to I/SPI IS Signals PG. nalog Inputs PG. IS Interface Line-In / Microphone nalog Outputs PG. Headphone SGTL PG. igital Header P PSI

More information

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1% K POWER SW JP EXTERNL POWER FUSE 0. uf VT 0 uf R SM or LMMPX-J VIN VOUT U 0.0K % J R.K % 0uF REG_V 0 0.uF REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.

More information

#1 10P/DIL NORTH #3 #3 #3 #3 #3 #3 #3 #3 R198 RES0603 RES0603 DNP DNP DNP RES0603 RES0603 RES SDI_N 3-SDO_N 3-ALERT_N 3-CS_N 3-SCLK_N 3-CONV_N

#1 10P/DIL NORTH #3 #3 #3 #3 #3 #3 #3 #3 R198 RES0603 RES0603 DNP DNP DNP RES0603 RES0603 RES SDI_N 3-SDO_N 3-ALERT_N 3-CS_N 3-SCLK_N 3-CONV_N P REVISION REOR J SP88 0 - RE N_JK P 90-00_-POS TP # - Remove these components to stack north # - Populate these components to stack north Use k Resistors or adjust as needed Header - Molex 90-0 PITORS,

More information

AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%

AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1% K POWER SW JP EXTERNL POWER FUSE 0. uf VT + 0 uf SM or LMMPX-J REG_V VIN VOUT + 0uF 0 0.uF U R 0.0K % J R.K % REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.

More information

XIO2213ZAY REFERENCE DESIGN

XIO2213ZAY REFERENCE DESIGN XIOZY REFERENE ESIGN XIOZY Reference Size ocument Number Rev ate: Wednesday, September, 00 Sheet of TP+ TP- TP+ TP- TPIS TP+ TP- TP+ TP- TPIS TP0+ TP0- TP0+ TP0- TPIS0 REFLK+ REFLK- V_ V_ V_ORE PLLV_ORE

More information

3.3V_MCU D N5 D N2 BAV99 D N4 BAV99 D N13 3 BAV99. ESD solution 0.01U TP1 TP2 R4 75 R3 75 R5 75 TP3 TP4 TP6 TP8 R+ G+ B+ R 35 TP11. A-detect C 77 0.

3.3V_MCU D N5 D N2 BAV99 D N4 BAV99 D N13 3 BAV99. ESD solution 0.01U TP1 TP2 R4 75 R3 75 R5 75 TP3 TP4 TP6 TP8 R+ G+ B+ R 35 TP11. A-detect C 77 0. .V_MU.V_MU N V0LT P V N V N V N V N V 0.0U ES solution 0 0.0U J 0.0U J 0.0U J PV TP 0.U U 0 V WP SL VSS S T0 R 0 0 R R.K.K _WP_ R.K SU_SL SU_S SU_S R.V TP TP TP TP0 G J 0 00 TP TP TP TP TP TP R R R R R+

More information

SYMETRIX INC th Avenue West Lynnwood, WA USA REV: DATE:

SYMETRIX INC th Avenue West Lynnwood, WA USA REV: DATE: R 0K0 RST U S_ PF/0V PF/0V 0FS FS T T 0SLK N SOT N SOT Y mhz U LS0 debug port 0 do not stuff R WR S PS X/Y IN/IN IR 0IR MO J R M R 0K0 R0 K00 R 0K0 dsck dr dsi dso / G 0 U LS0 R 0K0 SI_RX SI_TX SI_LK TFS

More information

COVER PAGE, TOP 04 ~ 05 VGA, LED, 7SEGMENT

COVER PAGE, TOP 04 ~ 05 VGA, LED, 7SEGMENT LTER YLONE III EP evelopment & Education OR SHEMTI ONTENT PGE TOP MEMORY OVER PGE, TOP SRM,FLSH 0 ~ 0 0 ~ 0 ISPLY VG, LE, SEGMENT 0 ~ 0 IN/OUT LOK, PS, RS, UTTON, SWITH, ONNETOR,S R 0 ~ FPG yclone II EP

More information

Virtex 5 FF1760 DUT. Differential SMA Clocks 2X D. Single Ended Socket Clocks 2X. Upstream Connector. Upstream. Power Bus and Switches 5V

Virtex 5 FF1760 DUT. Differential SMA Clocks 2X D. Single Ended Socket Clocks 2X. Upstream Connector. Upstream. Power Bus and Switches 5V PGE System Monitor ux PGE System Monitor PGE System ce Upstream PGE Upstream onnector PGE Single Ended Socket locks X PGE ifferential SM locks X PGE -0 Power us and Switches V OR V JK RIK VINT VINT JK

More information

Note: Please refer to AX110xx Network SoC Application Design Note for more detailed information.

Note: Please refer to AX110xx Network SoC Application Design Note for more detailed information. PGE PGE X00 & X00 hip H/W onfiguration Pins MHz rystal RJ- onnector o H ebugger onnector I onfiguration EEPROM (T0) Power and y-pass apacitors Serial us Schematic: I : I EEPROM SPI : T EEPROM (optional)

More information

C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5.

C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5. Size FSM No. WG No. Rev of 9 Galen Street Floor M 0 US MP0EMO Schematic -- MU and Symbol V V P P P P P 9 P0 0 P P P P0 VE V REFYP V P PK P P P 9 P 0 P0 P P P V P P P P9 P P P0 P P 9 P 0 P P P9 P P P P

More information

Revisions. 2 Notes. 4 FXLC95000CL / MCU Circuit 5 Power and Battery Charger Circuit. KITFXLC95000EVM Drawn by:

Revisions. 2 Notes. 4 FXLC95000CL / MCU Circuit 5 Power and Battery Charger Circuit. KITFXLC95000EVM Drawn by: Table of ontents Notes lock iagram FXL000L / MU ircuit Power and attery harger ircuit Rev escription Revisions Original Release Remove signal line U- pin and add additional signal line between J-pin0 and

More information

R2 44.2K_1% 5DVCC 5DVCC GND COMP SS24 DW1. EC2 470uF/16V. 470uF/16V 内内内内内内 DW2; 去去 U103,L9 33V. 33V C15 NC/10uF 33V C17 D2 NC/UDZ33B-33V

R2 44.2K_1% 5DVCC 5DVCC GND COMP SS24 DW1. EC2 470uF/16V. 470uF/16V 内内内内内内 DW2; 去去 U103,L9 33V. 33V C15 NC/10uF 33V C17 D2 NC/UDZ33B-33V JK_P JP V V L 0u/N F FUSE() FUSE E 0uF/V E. V L 0u/N V 00nF 00nF V, R 00K 00nF U MP IN EN SS OMP 0nF S SW F 0.nF R K SW L u R.K_% R 0K_% V E 0uF/V V,,, ST-V V 00nF.uF 00P SS W ST-V E 0uF/V E 00nF TO U

More information

Service Information. Service. Service. Service FW-V220. Product Service Group CE Audio A02-160

Service Information. Service. Service. Service FW-V220. Product Service Group CE Audio A02-160 Service Service Service W-V0 0-0 Product Service Group udio Service Information lready published Service Informations: ORRTION TO SRVI MNUL elow are corrections to the circuit diagram parts list: OMI OR

More information

INDEX/ RESET& EEPROM JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z SF_CE SF_SO SF_CLK SF_SI SF_CE SF_SO SF_CLK SF_SI PC_SCL PC_SDA SCL SDA RST

INDEX/ RESET& EEPROM JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z SF_CE SF_SO SF_CLK SF_SI SF_CE SF_SO SF_CLK SF_SI PC_SCL PC_SDA SCL SDA RST N Updata /N P. R.K R 00 R 00 R.K P_SL P_S V R K SF_E U PMVF00 E SO WP VSS V HOL SK SI SF_LK V 0.UF/V SF_E SF_LK P_SL P_S SL S V SL' S' SF_E SF_LK P_SL P_S SL S V SL' S' U T 0 V WP SL S SL' S' 0.UF/V R

More information

Intel Edison. 7V to 15V Brick Power Supply. 4.4V power supply and battery recharger UART 1 USB 0TG. EDISON BREAKOUT BOARD Title Title page

Intel Edison. 7V to 15V Brick Power Supply. 4.4V power supply and battery recharger UART 1 USB 0TG. EDISON BREAKOUT BOARD Title Title page Intel Edison reakout Sept/0 V to V rick Power Supply V power supply and battery recharger SPI GPIO Intel Edison PWM I S URT 0 0" header US 0TG URT Level Shifter URT US FTI P P lient US Micro Type- lient

More information

PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]

PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31] V. V. V. V. PI_RX URT LK URT TX PI_RX _TS_EXPHR _RX_EXPHR _RX_EXPHR Uarts URT TS URT RTS URT TX URT RX PS LOK PS T PS LOK PS T URT TX URT RX URT TX URT RX V. V. Ethernet ETH RX[0:] ETH RXV ETH RXER ETH

More information

SVS 5V & 3V. isplsi_2032lv

SVS 5V & 3V. isplsi_2032lv PU 000pF 000pF 000pF 0 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 0 000pF 000pF 000pF 000pF 000pF 000pF 000pF FLSH.0uF.0uF.0uF 0.0uF ata uffer.0uf.0uf.0uf.0uf SVS V & V.0uF.0uF.0uF isplsi_0lv.0uf.0uf

More information

A B C D TXD[15:0] TXD10 TXPAR 2.2K R38 RA12 1 RA13 AD10 +3V J98 PHY_INT HSERR R70 PRST TXPAR. ATM Physical Local Bus. Local Bus Interface.

A B C D TXD[15:0] TXD10 TXPAR 2.2K R38 RA12 1 RA13 AD10 +3V J98 PHY_INT HSERR R70 PRST TXPAR. ATM Physical Local Bus. Local Bus Interface. S J TXR0 TXR TXR TXR[:0] TXR TXR LK TX[:0] TX0 TX TX0 TX TX TX TX TX TX TX TX TX TX TX TX TX R 0K R 0K J J0 PIV R 0K TXPR R0. H/E0 H/E H/E TXLV TXSO J J HRST HLK HPERR HGNT HISEL HEVSEL HSTOP HTRY HIRY

More information

Changed in Rev.3. Title. Revision: Size: A4 Number:

Changed in Rev.3. Title. Revision: Size: A4 Number: ontent:. R Memory. Nand Flash, I, SPI Memory, S card. Ethernet M. Ethernet Phy 0. Ethernet Phy. RS-, ebug RS-, User leds, Relay leds. N0, N, External RT. US, US power switch. L onnector, Expansion onnector,

More information

A B C D REVISIONS +3V J39 PHY_INT TXD15 TXPAR PRST AC16 AC21 AD22 AF22 AE22 AF17 AC22 AE16 AE21 AD18 AE7 AD17 AE19 AE20 AF20 AC20 A16 B13 TXD14

A B C D REVISIONS +3V J39 PHY_INT TXD15 TXPAR PRST AC16 AC21 AD22 AF22 AE22 AF17 AC22 AE16 AE21 AD18 AE7 AD17 AE19 AE20 AF20 AC20 A16 B13 TXD14 A ISIONS ZONE LTR ESRIPTION ATE APPROVE A INITIAL RELEASE --_0:0 J 0 0 0,,,, AF JP PAR [:0] ON PIV 0 SO LAV EN LK PHYS M LK STAT_A M0 M R R R R R R R 0K J J AR AR[:0] AR AR AR AR0 AR AR[:0] AR AR AR AR0

More information

FREEDOM KE02Z. 1 Title 2 Block Diagram 3 KE02Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 02/01/13

FREEDOM KE02Z. 1 Title 2 Block Diagram 3 KE02Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 02/01/13 Table of ontents Title lock iagram KEZ MU OpenS INTERFE I/O Headers and Power Supply Rev X escription Initial raft Revisions. Remove Motor ontrol onnector J. Remap J, J, J, J pinout. dd one series resister

More information

All use SMD component if possible

All use SMD component if possible R0 0K MF SW0 NEXT R0 0R LE0 STNY & POWER ON GN R0 SW0 PREV R 0 MF R 0 MF R 0K MF R0 K MF SW0 FF GN SNP OFF OR GN Q0 S Q0 S LE R k R k 00n R 0K MF M0 R0 K MF SW0 FR +V() Q0 R 0K MF GN R0 0 R 0 GN VF_on_off

More information

2.5V 1.2V / 1.5V CORE 3.3V I/O MOUNTING HOLES GROUND TESTPOINTS +5.0V DC IN. SoC Solutions FB2 R K C12 15 PF FERRITE_BEAD C14 C C13 2.

2.5V 1.2V / 1.5V CORE 3.3V I/O MOUNTING HOLES GROUND TESTPOINTS +5.0V DC IN. SoC Solutions FB2 R K C12 15 PF FERRITE_BEAD C14 C C13 2. +.0V IN J PJ-0 _ONN VUS JP JUMPERT VUS_FP 00 F FERRITE_E..V U TPS0 GN F TGN PF R.K % VP. R K %.V /.V ORE.V I/O U TPS0 JP VP JP HR VP_GL U TPS0 R.K LM0EM -. JP HR VORE_GL VORE. GN F TGN 0 PF R.K % R K %.

More information

MSP430F16x Processor

MSP430F16x Processor MSP0x Processor V_. V_ V_. U Vcc Vcc R 0K SW, ETHER_T_00, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0 P.0/TLK P./T0 P./T P./T P./SMLK P./T0 P./T P./T /RST/NMI 0.u P UTTON_

More information

U1-1 R5F72115D160FPV

U1-1 R5F72115D160FPV pf R NF_ X MHz, pf ON_XTL ON_EXTL R R NF_,,,, R NF_ R NF_ R R,,,, M M M_LK M_LK SEMn TI TMS TK TRSTn K R K R K R K R EXTL XTL M M M_LK M_LK TESTM SEMn TI TMS_WTX TK_WSK TRSTn_WRX U- RFFPV VREF VREFVSS

More information

EFM8BB3 USB Type-C 60 W Charger. Revision History. Board Function. Rev. Description. Title Page. A00 Prototype version. EFM8BB3 & User Interface

EFM8BB3 USB Type-C 60 W Charger. Revision History. Board Function. Rev. Description. Title Page. A00 Prototype version. EFM8BB3 & User Interface EFM US Type- 0 W harger History oard Function Title Page EFM & User Interface oard Power Page Rev. escription 00 Prototype version. 0 Initial release version. VUS Voltage Regulator ebug MU ebug Misc. P

More information

VCC 52 VCC 21 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD

VCC 52 VCC 21 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD POWER ELETRONIS **- Switching Power Regulation** V and.v outputs are isolated from High Voltage, but not each other Isolated Power Supply power.sch FTI US URT FTI US URT ftdi_uart.sch Safety Loop Wiring

More information

ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B

ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B IS_IRQ V._0._0._0 O NOT IS_IRQ R K_0._0.0_0 J J.0_0 0 RV_RESET V RV_RESET V TP J IS TEST._0 TP V X [0..] [0..] GN GN -I/O H K RESRV V 0 IRQ V -V REQ -V U 0WS 0 0 V 0 -IO_HRY._0 GN -I/O H RY 0 -SMEMW EN

More information

SCHEMATIC AD9265 CMOS EVALUATION BOARD REV. DRAWING NO. AD9265CE01A REVISIONS DESCRIPTION JUMPER TABLE RELAY CONTROL CHART A A DE N V C L O

SCHEMATIC AD9265 CMOS EVALUATION BOARD REV. DRAWING NO. AD9265CE01A REVISIONS DESCRIPTION JUMPER TABLE RELAY CONTROL CHART A A DE N V C L O THIS RWING IS THE PROPERTY OF NLOG EVIES IN. IT IS NOT TO E REPROUE OR OPIE, IN WHOLE OR IN PRT, OR USE IN FURNISHING INFORMTION TO OTHERS, OR FOR NY OTHER PURPOSE ETRIMENTL TO THE INTERESTS OF NLOG EVIES.

More information

RTL8211DG-VB/8211EG-VB Schematic

RTL8211DG-VB/8211EG-VB Schematic RTL8G-V/8EG-V Schematic REV..8 Page Index. Page. PHY. MI. M. Power. History RTL8G/8EG Size ocument Number Rev.8 TITLE PGE ate: Sheet of External clock and rystal RTL8G/8EG GMII/RGMII Interface LK_M ENSWREG

More information

3JTech PP TTL/RS232. User s Manual & Programming Guide

3JTech PP TTL/RS232. User s Manual & Programming Guide JTech PP-00 TTL/RS User s Manual & Programming Guide Revision. J Tech o., Ltd. Fu-Hsing N. Rd., F Taipei, Taiwan Tel: +--00 9 info@jtech.com.tw JTech (J Eng.), Inc. E. Valley lvd., Suite ity of Industry,

More information

Revisions. TWR-LCD-RGB Drawn by: Initial Release 15-JUL-11

Revisions. TWR-LCD-RGB Drawn by: Initial Release 15-JUL-11 Table of ontents Notes lock iagram isplay and Tower onnectors MU & apacitive Touch kt Rev X X escription Revisions Initial Release ate -JUL- pproved hanged Power L colours-jul- Removed J and J dded J &

More information

VCC 21 VCC 52 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD

VCC 21 VCC 52 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD POWER ELETRONIS **- Switching Power Regulation** V and.v outputs are isolated from High Voltage, but not each other Isolated Power Supply power.sch FTI US URT FTI US URT ftdi_uart.sch SLOOP_TRL HRG_TRL

More information

Power. Video out. LGDC Subsystem

Power. Video out. LGDC Subsystem Power LE_UX# LG Evaluation System: Mainboard Revision: P Reference I: 00 # Video out LG Subsystem _N[..0] SM[..0] I[..0] LE_UX# _N[..0] SM[..0] I[..0] LE_UX# _N[..0] SM[..0] I/O ISP_LK I[..0] ISP_[..0]

More information

A L A BA M A L A W R E V IE W

A L A BA M A L A W R E V IE W A L A BA M A L A W R E V IE W Volume 52 Fall 2000 Number 1 B E F O R E D I S A B I L I T Y C I V I L R I G HT S : C I V I L W A R P E N S I O N S A N D TH E P O L I T I C S O F D I S A B I L I T Y I N

More information

XR21B1422/1424 POWER & USB 1.0 Date: Thursday, February 13, 2014

XR21B1422/1424 POWER & USB 1.0 Date: Thursday, February 13, 2014 ON V_US M P GN SH SH US _WURTH_ R ZERO.JTN R US US R n N.K_P.KLTN Q U_, V_N TP SISTETN INRUSH IRUIT x Header_KN n N R ZERO.JTN ZERO.JTN Notes: o not install R if URT Vcc_Reg is connected to V (Vcc_US),.Uf,.V,

More information

R5 330K R49 100K Q4 BC549 R12 2K2 U2B TL074 R50 100K R28 3K3. VR7 47KB via J38 R48 100K C BASSDRUM_TRIG. VR6 10K via J39 R29 100K R51 22K Q11 BC559

R5 330K R49 100K Q4 BC549 R12 2K2 U2B TL074 R50 100K R28 3K3. VR7 47KB via J38 R48 100K C BASSDRUM_TRIG. VR6 10K via J39 R29 100K R51 22K Q11 BC559 00 - SS RUM SSRUM_TRIG nf R K R K N R R K R 0 R K R K nf N R R K 0.uF EY R K R 0K R VR via J R U TL0 R R0 R VR via J EPTH R U TL0 R K PITH VR K via J R R K 0 R 0K R K nf N U TL0 R K R0 K R K R ISTORTION

More information

PCnet-FAST+ Am79C PQFP

PCnet-FAST+ Am79C PQFP NOTE: Place bypass caps close to power pins. EEPROM Pnet-FST+ m 0 PFP EEPROM Revision ate rawn omments 0 S Initial Release. NetPHY-LP LT Reference esign 0// S // // RF NetPHY-LP_LT_ Wednesday, ugust, NetPHY-LP

More information

POWER Size Document Number Rev Date: Friday, December 13, 2002

POWER Size Document Number Rev Date: Friday, December 13, 2002 R0 [ /W 0 0.00uF/00V - D0 KP0M L0 L D0 N 0 00uF/00V 0 0.uF R0 M [ /W R0 M [ /W R0 M [ /W R0 M [ /W 0 0.00uF/KV D0 PS0R 0 0uF R0 00K [ W D0 FR0 R0 0 [ /W O O T0 O,, POWER X'FMR 0, D0 DQ0 R [ /W 0.00uF/00V

More information

VREF XREF=1/A1,1/B2,7/A2 C103 AVDD 0.1U VDDCORE DRVDD VDDIO ENC+ ENC- AIN+ OVR EC2 XREF=2/B2 XREF=2/B2 XREF=2/B2 XREF=2/A1 XREF=1/A1,7/B1 XREF=2/B2

VREF XREF=1/A1,1/B2,7/A2 C103 AVDD 0.1U VDDCORE DRVDD VDDIO ENC+ ENC- AIN+ OVR EC2 XREF=2/B2 XREF=2/B2 XREF=2/B2 XREF=2/A1 XREF=1/A1,7/B1 XREF=2/B2 --00_: RV;E,F,G,H,J,K,L,M,N,P,R V;H,H,J,J,K,K,L,L,M,M,N,N,P,P V;,,,,,,,E,E,F,F,G,G SMOE MOE S EXP EXP EXP0 HIPI HIIPI HIPI HIPI0 EXTFILTER GN_ GN_0 IN- IN+ EN- EN+ VREF V_ES N RY PLK PULK LK SYN SYN SYN

More information

E N_c M/MPMV/MP LOK IRM TTERY TYPE Sub block iagram / OM option SP POWER SEQENE... PU M Turion F/ PU P LF LF LF HOST US VI ual H. RT & TV ON LF V ON Nvidia Nx series TI Mx series LVS & INV ON R SRM //

More information

Renesas Starter Kit for RL78/G13 CPU Board Schematics

Renesas Starter Kit for RL78/G13 CPU Board Schematics Renesas Starter Kit for RL/G PU oard Schematics REV REF TE RWN Y 0.0 raft.0.0 TES.00 Release.0.0 YOI.0 Release 0.0.0 YOI PGE ESRIPTION INEX RL/G Microcontroller Switches, LEs, RESET, PSU E, Serial Port

More information

2 Notes 3 MC9S08LG32CLK 4 Touch Sensors 1 5 Touch Sensors 2 6 Power 7 OSBDM 8 USB COM

2 Notes 3 MC9S08LG32CLK 4 Touch Sensors 1 5 Touch Sensors 2 6 Power 7 OSBDM 8 USB COM Table of ontents Notes MS0LGLK Touch Sensors Touch Sensors Power OSM US OM L Revisions Rev escription X First raft X Replaced, M RN with sigle resistors Updated Power section Swapped LE_ER, with ER, to

More information

CPU AML8613 USB HOST JTAG KEY CARD Block RCA-3 AUDIO 2CH COAX OUTPUT. pin140/tms pin141/tdi pin142/tck pin143/tdo

CPU AML8613 USB HOST JTAG KEY CARD Block RCA-3 AUDIO 2CH COAX OUTPUT. pin140/tms pin141/tdi pin142/tck pin143/tdo R- VS/RG OX OUTPUT UIO H L/R UIO MPLIFIER R JTG L/R IE PU ML SPI FLSH WQ0/KHL0 (bit/bit/bit Option) SRM ML-TG/ ML-TG/ IN.V/. LO -. - MP0.V/00m.V/0m US HOST IR Remote in ard Reader (S/MM/MS) US HOST US

More information

Desired Part Placement. Max current set to 3A (motor Drive is 2.5A) SCI-DRV8814-MVK Mike Claassen B1 Dawn Ritz 40V. VDC_In GND. Board Test Points TP1

Desired Part Placement. Max current set to 3A (motor Drive is 2.5A) SCI-DRV8814-MVK Mike Claassen B1 Dawn Ritz 40V. VDC_In GND. Board Test Points TP1 SI_x_NLG_H_[:] P P SI_x_SPI_MISO SI_x_SPI_MOSI SI_x_SPI_LK SI_x_SPI_S FE/SI_OM_ FE/SI_OM_ FE/SI_OM_ FE/SI_OM_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_

More information

DISPLAY 1 DISPLAY 2 a. a b. a f. a f. b g. c d. c d. 16 x 2 HD44780 BASED ALPHANUMERIC DISPLAY LCD 16 X 2

DISPLAY 1 DISPLAY 2 a. a b. a f. a f. b g. c d. c d. 16 x 2 HD44780 BASED ALPHANUMERIC DISPLAY LCD 16 X 2 SEGMENT LE ISPLY R MUX MUX MUX MUX R nf SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ U R xt P P P P P P P P MX MX ss SL S P P P P P P P P nf S SEG_SL SEG_S SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_I_SL_

More information

Revision History. EFR32 Mighty Gecko Dual PHY Radio Board. 2.4 GHz 13dBm / MHz 14 dbm, DCDC to PAVDD. Board Function Page. Rev.

Revision History. EFR32 Mighty Gecko Dual PHY Radio Board. 2.4 GHz 13dBm / MHz 14 dbm, DCDC to PAVDD. Board Function Page. Rev. EFR Mighty Gecko ual PHY Radio oard. GHz dm / 868-9 MHz dm, to PV oard Function Page Title Page History Rev. escription. GHz RF, ntenna & Power 00 Prototype version. SubGHz RF, ntenna & Power EFR, PRO

More information

MT9V128(SOC356) 63IBGA HB DEMO3 Card

MT9V128(SOC356) 63IBGA HB DEMO3 Card MT9V(SO) IG H MO ard Page escription Page lock iagram Pinout Sensor Power Supply VideoOut_lock_Reset xternal Interface Rev Who ate escription Rev 0.0 jwrede 0/0/0 ase Schematic for ustom esign Rev 0. aralex

More information

+12V R16 100K +12V R17 100K R19 R18 100K 100K AVPP BVPP C21. C20 0.1uF. 0.1uF NOTES:

+12V R16 100K +12V R17 100K R19 R18 100K 100K AVPP BVPP C21. C20 0.1uF. 0.1uF NOTES: +V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R0 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V 0.uF U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V

More information

CAN 1 CAN 2. CoiNel Technology Solutions LLP GND GND GND GND GND GND J1 JUMPER J2 JUMPER. 100nF. 100nF R2 120 R1 120 VDD 3 CAN1_H CAN2_H

CAN 1 CAN 2. CoiNel Technology Solutions LLP GND GND GND GND GND GND J1 JUMPER J2 JUMPER. 100nF. 100nF R2 120 R1 120 VDD 3 CAN1_H CAN2_H V N N V N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H N_L N_L J ON N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H

More information

X-USBPD-C-SHIELD. 2 Block Diagram 3 Type-C Connector 4 USB3/USB2 5 PTN5110 PD TCPC 6 Shield Headers 7 PD Source and Sink LS 8 3V3, 5V0, 1V8 Supplies

X-USBPD-C-SHIELD. 2 Block Diagram 3 Type-C Connector 4 USB3/USB2 5 PTN5110 PD TCPC 6 Shield Headers 7 PD Source and Sink LS 8 3V3, 5V0, 1V8 Supplies Table of ontents lock iagram Type- onnector US/US PTN0 P TP Shield Headers P Source and Sink LS V, V0, V Supplies Rev escription ate pproved Prototype Release -Mar- K ring up to NL and make updates requested

More information

AML7266-H. Feature table. Block Thursday, February 12, 2009 AMLOGIC AML7266-H. Main Chip: Internal: Video: Audio: Interfaces: UART USB HOST RJ45

AML7266-H. Feature table. Block Thursday, February 12, 2009 AMLOGIC AML7266-H. Main Chip: Internal: Video: Audio: Interfaces: UART USB HOST RJ45 ON Y Pb Pr is(smk,sk,slrk,s) MP U V V pin con to Mainboard IR MI MI U WM SMK,SK,SLRK MII_(ST) URT JTG con U ML-H SPI FLSH U MXL-G U NN FLSH KFGU Gb SL +.V/. POR LO U +.V RJ RMII Eth PHY U LN US HOST RMII

More information

LO_TX LO_TX MIXER_OUT MIXER_OUT VCC5V VCC5V VCC3V3 VCC3V3 VCC5V_TX VCC5V_TX VCC5V VCC5V VCC12V_TX VCC12V_TX VCC3V3 VCC3V3 AGND

LO_TX LO_TX MIXER_OUT MIXER_OUT VCC5V VCC5V VCC3V3 VCC3V3 VCC5V_TX VCC5V_TX VCC5V VCC5V VCC12V_TX VCC12V_TX VCC3V3 VCC3V3 AGND R White R Red _TX_Q_P J 0-0 0 _TX_I_P _TX_I_N _TX_Q_P _TX_Q_N L _TX_I_P _TX_I_N.R -d ttenuator.r.r 00pF_0V JP SM _TX_Q_P _TX_Q_N _TX_Q_P _TX_Q_N GN VV VV VV_TX VV VV VV_TX Modulator L L PowerSupply J POWER

More information

For max 243 R2OUT is low when R2IN is disconnected enabling the MAX 489 (RS-485) This will not work if MAX232 is used!

For max 243 R2OUT is low when R2IN is disconnected enabling the MAX 489 (RS-485) This will not work if MAX232 is used! JP RS_SELET V For max ROUT is low when RIN is disconnected enabling the MX (RS-) This will not work if MX is used! V On Front Panel -F (To Pg.) RS- RE_ RE_ RV_Y RV_Z 0.uF V U MXUK STR U- H G U MX 0 Y Z

More information

B1 AC V+ J2 120V J5V AC_HI -V_RLY A_ON +V DGND A_ON2 J1 230V uF/25V AC_LO J3 120V AC V- 2KPB06M DW G-S-290 R1 499R TE ND J ON

B1 AC V+ J2 120V J5V AC_HI -V_RLY A_ON +V DGND A_ON2 J1 230V uF/25V AC_LO J3 120V AC V- 2KPB06M DW G-S-290 R1 499R TE ND J ON 0 _HI _LO F J 0V J 0V J 0V T T-00-N V V- KP0M 00uF/V _ON V N JV J ON -V_LY _ON V N W-0---S-0 _ON N PW000-SFH P.O. OX 0, NL. PTOOUH, ONTIO N KJ Y PHON (0) - FX (0) -0 WWW.YSTON. LT 00 igital Power Supply

More information

H-LCD700 Service Manual

H-LCD700 Service Manual H-L00 Service Manual FULT ESIPTION: SOUN onfirm the volume isn t in silent mode before check. heck I0 () plug has audio output or not Speaker damaged heck I0 has supply V or not heck power heck I0 () plug

More information

FREEDOM KL25Z. 1 Title 2 Block Diagram 3 KL25Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 04/10/12 M.

FREEDOM KL25Z. 1 Title 2 Block Diagram 3 KL25Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 04/10/12 M. Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Rev X escription Revisions Initial raft ate 0/0/ pproved M. NORMN Release to production 0/0/ M. NORMN X hanges made

More information

05 - Adaptacion Puerto Serie RXD_UC R35 0 DTR_UC R36 0 RI_UC Adaptacion Puerto Serie Señalizacion GSM R37 0 INFO_NETLIGHT R38 0

05 - Adaptacion Puerto Serie RXD_UC R35 0 DTR_UC R36 0 RI_UC Adaptacion Puerto Serie Señalizacion GSM R37 0 INFO_NETLIGHT R38 0 0 - limentacion 0 - onector Externo 0 - daptacion Puerto Serie 0 - Modem SIM00 TT_VOLTGE VN_ TX TX_U RX_GSM RX_GSM HRGE_STTUS P. RX RX_U TX_GSM TX_GSM ST_ ST_ P. P. P. P. R 0 R 0 TR_U RI_U TR_GSM TR_GSM

More information

PCBA Rev 80.L9581G001 PCBA P/N: PCB P/N: PCB Rev 00.L9581G001. Title Content Size Document Number Rev C. A Date: Tuesday, December 15, 2009 FLD1.

PCBA Rev 80.L9581G001 PCBA P/N: PCB P/N: PCB Rev 00.L9581G001. Title Content Size Document Number Rev C. A Date: Tuesday, December 15, 2009 FLD1. ontent : P0_ontent P0_lock_iagram P0_FPG_I/O_ P0_FPG_I/O_ P0_FPG_Power&Memory P0_External_onnector P0_M_REG P0_I_Level_Shift P0_MU P0_Power pprover Jim esigner enson rawer enson P P/N: P Rev 0.LG00 P P/N:

More information

CPU Thermal Sensor GMT781-1 EXT.CLOCK GEN ICS954226AG-T. 533 MHZ Memory Dual channel DDR II CHANNEL A DDR II CHANNEL B 1X PCI-E<PORT1> 2.

CPU Thermal Sensor GMT781-1 EXT.CLOCK GEN ICS954226AG-T. 533 MHZ Memory Dual channel DDR II CHANNEL A DDR II CHANNEL B 1X PCI-E<PORT1> 2. NRL lok IGRM PU YONH/MERON eleron u-fpg PIN PU Thermal Sensor GMT- EXT.LOK GEN ISG-T attery In / & harge FS RT x -SU -Pin L " Square XG RT Hx LVS MHZ N LISTOG GML R II HNNEL R II HNNEL MHZ MHZ Memory ual

More information

5V_EXT J3-1 J3-1 5CSX_4A_IO39 5CSX_4A_IO37 5CSX_4A_IO40 UART0_CTS 5CSX_4A_IO32 UART0_RTS 5CSX_4A_IO29. 5CSX_IOp0 5CSX_IOn0. 5CSX_IOp1 5CSX_IOn1

5V_EXT J3-1 J3-1 5CSX_4A_IO39 5CSX_4A_IO37 5CSX_4A_IO40 UART0_CTS 5CSX_4A_IO32 UART0_RTS 5CSX_4A_IO29. 5CSX_IOp0 5CSX_IOn0. 5CSX_IOp1 5CSX_IOn1 JTG hain US to URT L RJ Socket PHY Micro S ard Socket HPS IO 空置 00-00 Soaseoard.(Final) PHY connect_.v V_EXT JTG_FPG_TO S_LK connect_.v SX IO N_RX connect_.v URT_TS URT_RTS RT_T S_ S_M S_T S_T S_T S_T0

More information

Sirius-Rx-232. Sirius-Tx-232. SIRIUS-Rx. STATUS Prog RC-5. SIRIUS-Rx. Prog RCA-5 DAB-SDA DAB-SCL STAYUS AM-SMETER POWER-ON POWER-ON CE-PLL

Sirius-Rx-232. Sirius-Tx-232. SIRIUS-Rx. STATUS Prog RC-5. SIRIUS-Rx. Prog RCA-5 DAB-SDA DAB-SCL STAYUS AM-SMETER POWER-ON POWER-ON CE-PLL UIO-OUT& U&.SH Sirius-Tx- +V-SY Sirius-Rx- -S -SL - S MU MU.SH M&M M&M.SH M ST M-SMETER E-PLL +V- +V- T-IN T-IN T-LK +V-STY +V-STY T-OUT ate: -Sep-00 Sheet of ile: :\aa\t. rawn y: RS-Tx RS-Rx R- STYUS

More information

Revisions. TRK-KEA128 Drawn by: Nov Original Release A. INZUNZA

Revisions. TRK-KEA128 Drawn by: Nov Original Release A. INZUNZA Table of ontents Title Page Notes Rev X escription Original Release Revisions ate Nov--0 pproved Production Release ec--0 Production Release Feb--0 Microcontroller Solutions Group 0 William annon rive

More information